On Fri, Sep 16, 2011 at 11:17 PM, Frank Rowand frank.row...@am.sony.com wrote:
On 09/16/11 00:31, Munegowda, Keshava wrote:
On Fri, Sep 16, 2011 at 11:17 AM, Munegowda, Keshava
keshava_mgo...@ti.com wrote:
On Fri, Sep 16, 2011 at 6:10 AM, Frank Rowand frank.row...@am.sony.com
wrote:
On
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Laurent Pinchart
Sent: Monday, September 19, 2011 3:29 AM
To: Martin Hostettler
Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-
me...@vger.kernel.org;
On Sun, Sep 18, 2011 at 11:58:55PM +0200, Laurent Pinchart wrote:
Hi Martin,
On Saturday 17 September 2011 11:34:57 Martin Hostettler wrote:
Adds board support for an MT9M032 based camera to omap3evm.
Sigend-off-by: Martin Hostettler mar...@neutronstar.dyndns.org
---
On Fri, 2011-09-16 at 18:11 +0530, K, Mythri P wrote:
Hi,
Sequence with HPD:
1.Register for HPD connect.
2.Enable display
3.Notify DRM/Audio/Kernel component that wants to listen to this event.
Why would you enable the display even if there's no monitor connected?
And when the
Hi Tony,
On Mon, 2011-09-12 at 14:20 +0300, Tomi Valkeinen wrote:
This patch set ports all the OMAP2/3 boards, except N8x0, that use the old
omapfb to use the newer DSS2 driver. Only board files are changed, the panel
driver additions are done in separate patch set. Applying this set without
Hi Martin,
On Monday 19 September 2011 08:10:19 mar...@neutronstar.dyndns.org wrote:
On Sun, Sep 18, 2011 at 11:58:55PM +0200, Laurent Pinchart wrote:
On Saturday 17 September 2011 11:34:57 Martin Hostettler wrote:
Adds board support for an MT9M032 based camera to omap3evm.
On Sunday 18 September 2011 11:45:16 Randy Dunlap wrote:
We have fallbacks to Andrew and/or GregKH currently, but GregKH is not
consistent or timely with applying drivers/misc/ patches. It deserves
better.
[added him to Cc: list]
I do try to handle patches sent to me for misc/ in
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On Thu, Sep 15, 2011 at 6:52 PM, Keshava Munegowda
keshava_mgo...@ti.com wrote:
From: Benoit Cousson b-cous...@ti.com
Following 4 hwmod structures are added:
UHH hwmod of usbhs with uhh base address and functional clock,
EHCI hwmod with irq and base address,
OHCI hwmod with irq and base
-Original Message-
From: Artem Bityutskiy [mailto:dedeki...@gmail.com]
Sent: Monday, September 19, 2011 10:26 AM
To: Saxena, Parth
Cc: linux-...@lists.infradead.org; Basheer, Mansoor Ahamed; linux-
o...@vger.kernel.org
Subject: Re: [PATCH] ti816x: add support for nand on ti8168
On Mon, 2011-09-19 at 17:04 +0530, Saxena, Parth wrote:
Artem,
I will re-post this patch to linux-omap list and Tony. Can I add your name in
the 'Acked-by' section?
No, I did not review this patch.
--
Best Regards,
Artem Bityutskiy
--
To unsubscribe from this list: send the line
On Mon, Sep 19, 2011 at 10:47:50AM +0200, Arnd Bergmann wrote:
On Sunday 18 September 2011 11:45:16 Randy Dunlap wrote:
We have fallbacks to Andrew and/or GregKH currently, but GregKH is not
consistent or timely with applying drivers/misc/ patches. It deserves
better.
[added him to
On 9/17/2011 6:05 PM, Grant Likely wrote:
On Fri, Sep 16, 2011 at 04:43:18PM +0200, Benoit Cousson wrote:
Split the omap_device_build_ss into two smaller functions
that will allow to populate a platform_device already allocated by
device-tree.
The functionality of the omap_device_build_ss is
On 9/17/2011 6:13 PM, Grant Likely wrote:
On Fri, Sep 16, 2011 at 04:43:19PM +0200, Benoit Cousson wrote:
Add a notifier called during device_add phase. If an of_node is present,
retrieve the hwmod entry in order to populate properly the omap_device
structure.
For the moment the resource from
Add partition table for NAND device on TI8168 EVM
and initialise the NAND module.
Signed-off-by: Saxena, Parth parth.sax...@ti.com
Signed-off-by: Basheer, Mansoor Ahamed mansoor.aha...@ti.com
---
This patch is tested on top of linux-omap/master and
Hemant's patches submitted recently.
Hi Tero,
On Fri, Sep 16, 2011 at 9:35 PM, Tero Kristo t-kri...@ti.com wrote:
Introduce a chained interrupt handler mechanism for the PRCM
interrupt, so that individual PRCM event can cleanly be handled by
handlers in separate drivers. We do this by introducing PRCM event
names, which are then
On Fri, Sep 16, 2011 at 9:35 PM, Tero Kristo t-kri...@ti.com wrote:
Hello,
This patch set is the version 8 for the OMAP PRCM chain interrupt handler.
The driver is providing a chain handler for PRCM interrupt events, which
can be then individually used by different drivers. Currently PRCM
Hi Keshava,
On Thu, Sep 15, 2011 at 06:52:45PM +0530, Keshava Munegowda wrote:
From: Keshava Munegowda keshava_mgo...@ti.com
The Hwmod structures and Runtime PM features are implemented
For EHCI and OHCI drivers of OMAP3 and OMAP4.
The global suspend/resume of EHCI and OHCI
is validated on
On Mon, Sep 19, 2011 at 7:26 PM, Samuel Ortiz sa...@linux.intel.com wrote:
Hi Keshava,
On Thu, Sep 15, 2011 at 06:52:45PM +0530, Keshava Munegowda wrote:
From: Keshava Munegowda keshava_mgo...@ti.com
The Hwmod structures and Runtime PM features are implemented
For EHCI and OHCI drivers of
Russell King - ARM Linux wrote on Saturday, September 17, 2011 8:04 PM:
On Sat, Sep 17, 2011 at 07:58:20PM +0530, Pedanekar, Hemant wrote:
But since I had submitted v1 (see [1]) and am working on v2 post review,
can you please suggest how to go about it as I will need the above for
adding
On Fri, Sep 16, 2011 at 7:43 PM, Greg KH gre...@suse.de wrote:
On Fri, Sep 16, 2011 at 07:21:41PM +0530, ABRAHAM, KISHON VIJAY wrote:
Sergei,
Thanks for your comments.
On Fri, Sep 16, 2011 at 3:18 PM, Sergei Shtylyov sshtyl...@mvista.com
wrote:
Hello.
On 15-09-2011 18:19, Kishon
On Thursday 15 September 2011, Grant Likely wrote:
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 21574bd..1836cdf 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2,10 +2,9 @@
# Multifunction miscellaneous devices
#
-menuconfig MFD_SUPPORT
-
On 9/19/2011 3:11 PM, Cousson, Benoit wrote:
On 9/17/2011 6:05 PM, Grant Likely wrote:
On Fri, Sep 16, 2011 at 04:43:18PM +0200, Benoit Cousson wrote:
[...]
- pr_debug(omap_device: %s: building with %d hwmods\n, pdev_name,
- oh_cnt);
+ /* Set the dev_name early to allow dev_xxx in
On Monday 19 September 2011, Greg KH wrote:
That sounds good to me, I'll be glad to collect the patches and push
them to Linus for both of those trees (might as well keep them in the
same git tree, no need to separate them, right?) and I'll rely on you
for review and acking them. Much like I
-Original Message-
From: Laurent Pinchart [mailto:laurent.pinch...@ideasonboard.com]
Sent: Friday, September 16, 2011 6:36 PM
To: Ravi, Deepthy
Cc: linux-me...@vger.kernel.org; t...@atomide.com; li...@arm.linux.org.uk;
linux-omap@vger.kernel.org;
On Sun, Sep 11, 2011 at 12:10:04AM +0800, Shawn Guo wrote:
On Thu, Sep 01, 2011 at 11:57:54PM +0800, Shawn Guo wrote:
On Thu, Sep 01, 2011 at 04:34:51PM +0100, Russell King - ARM Linux wrote:
On Thu, Sep 01, 2011 at 11:33:43PM +0800, Shawn Guo wrote:
This is also the case on i.MX6Q,
On Wed, Sep 07, 2011 at 04:48:28PM +0100, Lorenzo Pieralisi wrote:
@@ -29,8 +48,7 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned
long))
* resume (indicated by a zero return code), we need to switch
* back to the correct page tables.
*/
- ret =
This is a re-post of the previous patch series, but with an additional
TLB flush to ensure that hte global TLB entry in the page tables is
flushed out. This is a flush of all TLB entries, but it could probably
be more targetted if we need to.
Original cover mail follows:
Some systems (such as
Ensure that the return value from __cpu_suspend is non-zero when
aborting. Zero indicates a successful suspend occurred.
Tested-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
---
arch/arm/kernel/sleep.S |2 ++
1 files changed, 2
Preallocate a page table and setup an identity mapping for the MMU
enable code. This means we don't have to borrow a page table to
do this, avoiding complexities with L2 cache coherency.
Tested-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
On Mon, Sep 19, 2011 at 08:26:08PM +0530, T Krishnamoorthy, Balaji wrote:
On Fri, Sep 16, 2011 at 7:43 PM, Greg KH gre...@suse.de wrote:
On Fri, Sep 16, 2011 at 07:21:41PM +0530, ABRAHAM, KISHON VIJAY wrote:
Sergei,
Thanks for your comments.
On Fri, Sep 16, 2011 at 3:18 PM, Sergei
Hi Keshava,
On 9/19/2011 4:01 PM, Munegowda, Keshava wrote:
On Mon, Sep 19, 2011 at 7:26 PM, Samuel Ortizsa...@linux.intel.com wrote:
Hi Keshava,
On Thu, Sep 15, 2011 at 06:52:45PM +0530, Keshava Munegowda wrote:
From: Keshava Munegowdakeshava_mgo...@ti.com
The Hwmod structures and Runtime
* Pedanekar, Hemant hema...@ti.com [110918 20:32]:
Tony,
Kernel boots fine on TI816X (should also boot on TI814X) with your patch
and patches (including OSC clock fix) from series
http://www.spinics.net/lists/linux-omap/msg57011.html
OK good to hear, I assume I can add your Tested-by
* DebBarma, Tarun Kanti tarun.ka...@ti.com [110918 04:53]:
But we can map the interrupt registers separately and then have
the rest start from func_base that is different based on the timer
version. Rebasing the rest of the dmtimer hwmod patches on this
should be fairly easy, mostly just
* Mohammed, Afzal af...@ti.com [110918 21:48]:
Hi Tony,
On Sat, Sep 17, 2011 at 07:05:31, Tony Lindgren wrote:
Afzal, care to check if that works for AM335X/TI816X/TI814X?
With following patch over yours, AM335X (the only board with me) boots up
fine.
Thanks for catching that, will
We need to ensure that state is pushed out from the L2 cache when
suspending so that the resume paths can access their data before the
MMU and caches have been re-initialized. Add the necessary calls to
__cpu_suspend_save().
Tested-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by:
Convert some of the sleep.S guts to C code, which makes it easier to
use our macros and to add L2 cache handling. We provide a helper
function, __cpu_suspend_save(), which deals with saving the common
state, setting up for resume, and flushing caches.
The remainder left as assembly code is the
There is no need to save and restore the context ID register on ARMv6
and ARMv7 with a temporary page table as we write the context ID
register when we switch back to the real page tables for the thread.
Moreover, the temporary page tables do not contain any non-global
mappings, so the context ID
Only use the preallocated page table during the resume, not while
suspending. This avoids the overhead of having to switch unnecessarily
to the resume page table in the suspend path.
Tested-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
---
We don't require cpu_resume_turn_mmu_on as we can combine the ldr
instruction with the following code provided we ensure that
cpu_resume_mmu is aligned for older CPUs. Note that we also align
to a 32-byte boundary to ensure that the code can't cross a section
boundary.
Tested-by: Santosh
Hi
On Sun, 18 Sep 2011, Laurent Pinchart wrote:
Hi Martin,
On Saturday 17 September 2011 11:34:57 Martin Hostettler wrote:
Adds board support for an MT9M032 based camera to omap3evm.
Sigend-off-by: Martin Hostettler mar...@neutronstar.dyndns.org
---
arch/arm/mach-omap2/Makefile
On Mon, Sep 19, 2011 at 11:37:37AM +0530, Hiremath, Vaibhav wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Laurent Pinchart
Sent: Monday, September 19, 2011 3:29 AM
To: Martin Hostettler
Cc: Tony
-Original Message-
From: Taneja, Archit
Sent: Friday, September 16, 2011 12:09 PM
To: Valkeinen, Tomi
Cc: Hiremath, Vaibhav; linux-omap@vger.kernel.org; Taneja, Archit; linux-
me...@vger.kernel.org; Molnar, Lajos
Subject: [PATCH v2 1/3] OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha
-Original Message-
From: Taneja, Archit
Sent: Friday, September 16, 2011 12:09 PM
To: Valkeinen, Tomi
Cc: Hiremath, Vaibhav; linux-omap@vger.kernel.org; Taneja, Archit
Subject: [PATCH v2 2/3] OMAPDSS: DISPC: VIDEO3 pipeline support
Add support for VIDEO3 pipeline on OMAP4:
- Add
-Original Message-
From: mar...@neutronstar.dyndns.org [mailto:mar...@neutronstar.dyndns.org]
Sent: Tuesday, September 20, 2011 12:55 AM
To: Hiremath, Vaibhav
Cc: Laurent Pinchart; Tony Lindgren; linux-omap@vger.kernel.org; linux-
me...@vger.kernel.org;
OK, it looks like the second half of the answer was in a second email...
that makes sense:-)
On 9/15/2011 9:22 AM, Munegowda, Keshava wrote:
On Thu, Sep 15, 2011 at 11:25 AM, Munegowda, Keshava
keshava_mgo...@ti.com wrote:
On Wed, Sep 14, 2011 at 10:20 PM, Cousson, Benoitb-cous...@ti.com
Keshava,
I've just replied to your previous v8 version about the comments you
didn't take into account.
I just have one minor nit on that one I missed previously, plus a couple
of clarifications.
On 9/15/2011 3:22 PM, Munegowda, Keshava wrote:
From: Benoit Coussonb-cous...@ti.com
Following
* Tomi Valkeinen tomi.valkei...@ti.com [110919 00:05]:
Hi Tony,
On Mon, 2011-09-12 at 14:20 +0300, Tomi Valkeinen wrote:
This patch set ports all the OMAP2/3 boards, except N8x0, that use the old
omapfb to use the newer DSS2 driver. Only board files are changed, the panel
driver
From: Nicole Chalhoub n-chalh...@ti.com
While there is CPU load, program a C-state specific one-shot timer in
order to give CPUidle another opportunity to pick a deeper C-state
instead of spending potentially long idle times in a shallow C-state.
Long winded version:
When going idle with a high
Tony Lindgren wrote on Monday, September 19, 2011 11:11 PM:
device driver)
* Pedanekar, Hemant hema...@ti.com [110918 20:32]:
Tony,
Kernel boots fine on TI816X (should also boot on TI814X) with your patch
and patches (including OSC clock fix) from series
On Mon, Sep 19, 2011 at 05:22:22PM +0100, Russell King - ARM Linux wrote:
On Sun, Sep 11, 2011 at 12:10:04AM +0800, Shawn Guo wrote:
On Thu, Sep 01, 2011 at 11:57:54PM +0800, Shawn Guo wrote:
On Thu, Sep 01, 2011 at 04:34:51PM +0100, Russell King - ARM Linux wrote:
On Thu, Sep 01, 2011
On Mon, Sep 19, 2011 at 05:37:41PM +0100, Russell King - ARM Linux wrote:
This is a re-post of the previous patch series, but with an additional
TLB flush to ensure that hte global TLB entry in the page tables is
flushed out. This is a flush of all TLB entries, but it could probably
be more
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