On Wed, May 16, 2012 at 10:21 PM, Kevin Hilman khil...@ti.com wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh Shilimkar wrote:
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
Santosh,
Tero Kristo t-kri...@ti.com writes:
On Thu, May 17, 2012 at 4:35 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG is when MPU Domain OFF wake up sequence that can compromise
IVA and Tesla execution.
At wakeup from MPU OFF on HS device only
On Thu, May 17, 2012 at 4:47 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
On HS devices on the way out of MPU OSWR and OFF ROM code wrongly
overwrites the CM L3INSTR registers. So to avoid this, save them and
restore on the
On Thu, May 17, 2012 at 4:28 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The SAR RAM is maintained during Device OFF mode.
so why is this patch bothering to save and restore it?
SAR RAM is maintained(not
On Thu, May 17, 2012 at 4:12 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
SAR/ROM code restores only CORE DPLL to its original state
post wakeup from OFF mode.
The rest of the DPLL's in OMAP4 platform (MPU/IVA/ABE/USB/PER)
On Thu, May 17, 2012 at 4:18 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
Restore all CM1/2 module registers as they are lost in OFF mode.
Save and restore?
Also, as in the previous patch. Can this be done using cluster PM
On Thu, May 17, 2012 at 4:06 AM, Kevin Hilman khil...@ti.com wrote:
+Jean for functional power states
Tero Kristo t-kri...@ti.com writes:
This patch adds device off support to OMAP4 device type.
Description is rather thin for a patch that is doing so much.
OFF mode is disabled by default,
On Thu, May 17, 2012 at 5:45 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
Transition When CS1 Is Used On EMIF which impacts OMAP443x silicon
The
From: Rob Clark r...@ti.com
Now that dmabuf mmap support is in dmabuf-next, here is support for it
in omapdrm. Also some basic support to import dmabuf's. For now it
can only re-import dmabuf's that it exported itself, mainly because I
don't yet need anything else and also because at the moment
From: Rob Clark r...@ti.com
Add support for mmap'ing buffers via dmabuf. For handling mmap of
cached buffers correctly, fault handling and PTE shootdown are used
to track dirty pages and automagically handle cache flushes before
dma access to the buffer.
Signed-off-by: Rob Clark r...@ti.com
---
From: Rob Clark r...@ti.com
This adds support to re-import omapdrm's own buffers. Importing buffers
allocated by other drivers can be added later, but for now is not needed
(we don't yet have any other exportering drivers to test with).
Signed-off-by: Rob Clark r...@ti.com
---
On Thu, May 17, 2012 at 12:34 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, May 17, 2012 at 4:12 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
SAR/ROM code restores only CORE DPLL to its original state
post
Jean,
On Tuesday 08 May 2012 02:10 PM, Jean Pihet wrote:
Paul,
On Mon, May 7, 2012 at 11:28 AM, Paul Walmsley p...@pwsan.com wrote:
Hi
On Wed, 18 Apr 2012, jean.pi...@newoldbits.com wrote:
From: Jean Pihet j-pi...@ti.com
Introduce functional (or logical) states for power domains and the
clkdm assocations with clocks in the clock framework are useful
only for 'gate' clocks which have enable/disable ops populated.
Get rid of the clkdm_names populated in any other type of clocks.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/clock2420_data.c | 16
On 5/16/2012 3:34 PM, Jon Hunter wrote:
Hi Benoit,
On 05/16/2012 04:28 AM, Cousson, Benoit wrote:
Hi Jon,
On 5/16/2012 1:35 AM, Jon Hunter wrote:
From: Jon Hunterjon-hun...@ti.com
In order to migrate the dmtimer driver to support device-tree I found
that it
was first necessary to clean-up
Hi,
On Thu, May 10 2012, T Krishnamoorthy, Balaji wrote:
On Tue, May 8, 2012 at 5:05 PM, Venkatraman S svenk...@ti.com wrote:
Cleanups for the legacy omap mmc driver to remove clutter and
make it well behaved as module.
Venkatraman S (3):
mmc: omap: convert to per instance workqueue
mmc:
Hi Tony,
This is the updated DTS patch for Vatiscite OMAP4 SOM support
Regatds,
Uri Yosef
Signed-off-by: Uri Yosef ur...@variscite.com
---
arch/arm/boot/dts/omap4-var_som.dts | 96 +++
1 files changed, 96 insertions(+), 0 deletions(-)
create mode 100644
On Thu, May 10, 2012 at 11:00:53AM -0600, Stephen Warren wrote:
To solve Russell's HW, we need some way of representing the mux directly
in DT irrespective of how the DMA controller or DMA client specify what
they're connected to. Anything else isn't representing the HW in DT.
Note that it's
On Wed, May 16, 2012 at 07:42:20PM +, Arnd Bergmann wrote:
On Wednesday 16 May 2012, Jassi Brar wrote:
The assumed model of the DMAC, in this binding, has P peripheral
interfaces (P request signals) that could request a data transfer
and C physical channels that actually do the data
Hi Dmitry,
Gentle Ping on this..
~Sourav
On Wed, May 9, 2012 at 3:37 PM, Poddar, Sourav sourav.pod...@ti.com wrote:
Hi Dmitry,
On Wed, May 9, 2012 at 3:14 PM, Poddar, Sourav sourav.pod...@ti.com wrote:
Hi Dmitry,
I did some minor fixes to the patch which you suggested above and
the keypad
On Thu, May 17, 2012 at 02:22:23PM +0100, Russell King - ARM Linux wrote:
DMA on the other hand seems to have cases where you can make a choice
between two or more providers of the service. The impression that I'm
getting from this thread is that it's difficult to describe that kind
of
On Thu, May 17, 2012 at 7:57 AM, Ming Lei ming@canonical.com wrote:
The flag of IRQF_ONESHOT should be passed to request_threaded_irq,
otherwise the following failure message should be dumped because
hardware handler is defined as NULL:
[ 3.383483] genirq: Threaded irq requested with
On Thu, May 17, 2012 at 02:52:36PM +0100, Mark Brown wrote:
On Thu, May 17, 2012 at 02:22:23PM +0100, Russell King - ARM Linux wrote:
DMA on the other hand seems to have cases where you can make a choice
between two or more providers of the service. The impression that I'm
getting from
Hi,
On Thu, May 17 2012, S, Venkatraman wrote:
On Thu, May 17, 2012 at 7:57 AM, Ming Lei ming@canonical.com wrote:
The flag of IRQF_ONESHOT should be passed to request_threaded_irq,
otherwise the following failure message should be dumped because
hardware handler is defined as NULL:
[
Hi Sourav,
On Thu, May 17, 2012 at 07:01:49PM +0530, Poddar, Sourav wrote:
Hi Dmitry,
Gentle Ping on this..
The patch has been committed to my 'next' branch for 3.5 on 05/11/12:
http://git.kernel.org/?p=linux/kernel/git/dtor/input.git;a=commit;h=f77621cc640a7c50b3d8c5254ecc5d91eaa99d0d
Hi Paul,
On 05/16/2012 06:30 PM, Paul Walmsley wrote:
Hello Jon,
On Wed, 16 May 2012, Jon Hunter wrote:
I have been looking into this and in order to get rid for the above
function pointer we would need to move at a minimum the following
functions from omap-mach2/clkt_clksel.c into the
Hi Tarun,
On 05/17/2012 12:07 AM, DebBarma, Tarun Kanti wrote:
On Thu, May 17, 2012 at 1:44 AM, Jon Hunter jon-hun...@ti.com wrote:
Hi Benoit,
On 05/16/2012 04:28 AM, Cousson, Benoit wrote:
Hi Jon,
On 5/16/2012 1:35 AM, Jon Hunter wrote:
From: Jon Hunterjon-hun...@ti.com
In order to
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 12:34 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, May 17, 2012 at 4:12 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
SAR/ROM code
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 4:28 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The SAR RAM is maintained during Device OFF mode.
so why is this patch bothering to
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 4:35 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG is when MPU Domain OFF wake up sequence that can compromise
IVA and Tesla
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 5:45 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
Transition When CS1
On Thu, 17 May 2012, Jon Hunter wrote:
Yes that's right. What is your preference here, the options are ...
1. Move the clkt_clksel.c file to arch/arm/plat-omap and change the
omap2_xxx API names to omap_xxx.
2. Add the functions in clkt_clksel.c to arch/arm/plat-omap/clock.c and
get rid of
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Wed, May 16, 2012 at 10:21 PM, Kevin Hilman khil...@ti.com wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh Shilimkar wrote:
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman
Hi Michal,
On Sat, Mar 17, 2012 at 8:39 AM, Ohad Ben-Cohen o...@wizery.com wrote:
IOW: you can probably just wait a bit until this patch is ready and
take it into your tree. It will most likely bring back the behavior you
need :)
Does something like the attached help ?
Thanks,
Ohad.
On 05/16/2012 03:16 PM, Jassi Brar wrote:
On 17 May 2012 01:12, Arnd Bergmann a...@arndb.de wrote:
...
More importantly, you make it very hard to add devices in a board file
to a dma controller that already has descriptions for some channels,
because you cannot easily extend the chan-map
Jon Hunter jon-hun...@ti.com writes:
From: Jon Hunter jon-hun...@ti.com
The OMAP2+ timer code has a definition for the maximum number of timers that
OMAP2+ devices have. This defintion is not used anywhere in the code and
appears to be left over. Furthermore the definition is not accurate
Tarun, Santosh,
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
We do checking for bank-enabled_non_wakeup_gpios in order
to skip redundant operations. Somehow, the check got missed
while doing the cleanup series.
Just to make sure that we do context restore correctly in
* Kevin Hilman khil...@ti.com [120517 15:29]:
I just noticed that this patch has caused some strange problems, notably
with the GPIO IRQ used by smsc911x NIC (Overo, Zoom3, 2430SDP, etc. etc.)
The patch itself is OK, but it has exposed a bug in other parts of the
context restore path that
On Thu, 17 May 2012 15:21:07 -0700, Kevin Hilman khil...@ti.com wrote:
Tarun, Santosh,
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
We do checking for bank-enabled_non_wakeup_gpios in order
to skip redundant operations. Somehow, the check got missed
while doing the cleanup series.
Tony Lindgren t...@atomide.com writes:
* Kevin Hilman khil...@ti.com [120517 15:29]:
I just noticed that this patch has caused some strange problems, notably
with the GPIO IRQ used by smsc911x NIC (Overo, Zoom3, 2430SDP, etc. etc.)
The patch itself is OK, but it has exposed a bug in other
* Ohad Ben-Cohen o...@wizery.com [120516 02:58]:
Hi Tony,
Two important fixes from Juan that are necessary to utilize the DSP on
OMAP4, and a trivial hwspinlock cleanup.
I tried to keep things as simple as possible, but please tell me if
you want this pull request anyway differently (e.g.
* Kevin Hilman khil...@ti.com [120517 17:00]:
Argh, then $SUBJECT patch here has caused brokeness in multiple ways.
It managed to break both runtime suspend and runtime resume at the same
time. :(
The change added by this patch to runtime_suspend effectively disables
the fix I did in
On Thu, May 17, 2012 at 8:55 PM, Dmitry Torokhov
dmitry.torok...@gmail.com wrote:
Hi Sourav,
On Thu, May 17, 2012 at 07:01:49PM +0530, Poddar, Sourav wrote:
Hi Dmitry,
Gentle Ping on this..
The patch has been committed to my 'next' branch for 3.5 on 05/11/12:
Thanks.
The IRQ52 on OMAP2+ is not a shared interrupt line. If IRQF_SHARED
is passed to request_irq and dev_id is set as NULL, request_irq will
return -EINVAL.
This patch just removes the flag of IRQF_SHARED to make the irq
registration successful.
Cc: Kevin Hilman khil...@ti.com
Cc: Tony Lindgren
On Fri, May 18, 2012 at 5:26 AM, Kevin Hilman khil...@ti.com wrote:
Tony Lindgren t...@atomide.com writes:
* Kevin Hilman khil...@ti.com [120517 15:29]:
I just noticed that this patch has caused some strange problems, notably
with the GPIO IRQ used by smsc911x NIC (Overo, Zoom3, 2430SDP,
On Fri, May 18, 2012 at 3:51 AM, Kevin Hilman khil...@ti.com wrote:
Tarun, Santosh,
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
We do checking for bank-enabled_non_wakeup_gpios in order
to skip redundant operations. Somehow, the check got missed
while doing the cleanup series.
Just to
On Thu, May 17, 2012 at 10:12 PM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 4:28 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The SAR RAM is
On Thu, May 17, 2012 at 10:15 PM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 4:35 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG is
On Thu, May 17, 2012 at 10:17 PM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 5:45 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for
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