[PATCH] mmc: omap: Use DIV_ROUND_UP instead of open coded

This also makes the intention more clear. Signed-off-by: Axel Lin axel@ingics.com --- drivers/mmc/host/omap.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index 5c2e58b..711981e 100644 ---

Re: [PATCHv3 07/14] HSI: Add common DT binding for HSI client devices

On Fri 2014-04-25 22:59:27, Sebastian Reichel wrote: On Fri, Apr 25, 2014 at 08:25:36PM +0200, Sebastian Reichel wrote: On Sat, Apr 19, 2014 at 09:16:12PM +0200, Pavel Machek wrote: On Sat 2014-03-29 01:31:43, Sebastian Reichel wrote: Implement and document generic DT bindings for HSI

Re: [PATCHv3 07/14] HSI: Add common DT binding for HSI client devices

On Sun, Apr 27, 2014 at 12:57:55PM +0200, Pavel Machek wrote: On Fri 2014-04-25 22:59:27, Sebastian Reichel wrote: On Fri, Apr 25, 2014 at 08:25:36PM +0200, Sebastian Reichel wrote: On Sat, Apr 19, 2014 at 09:16:12PM +0200, Pavel Machek wrote: On Sat 2014-03-29 01:31:43, Sebastian

[PATCH 6/6] ARM: dts: am4372: Add clock names for cpsw and cpts

Add CPSW fck and CPTS clock and clock names for AM4372 Signed-off-by: George Cherian george.cher...@ti.com --- arch/arm/boot/dts/am4372.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 36d523a..c2779f6 100644 ---

[PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync

Enable the Annex F Time Sync explicitly for DRA7x and AM4372. With this enabled the L2 PTP is working. while at that rename TS_BIT8 to TS_TTL_NONZERO Signed-off-by: George Cherian george.cher...@ti.com --- drivers/net/ethernet/ti/cpsw.c | 8 +--- 1 file changed, 5 insertions(+), 3

[PATCH 3/6] drivers: net: cpsw: Enable CPTS for DRA7xx and AM4372

Enable cpts hardware time stamping for Dra7xx and AM4372. This enables PTPv2 for DRA7xx and AM4372. Signed-off-by: George Cherian george.cher...@ti.com --- drivers/net/ethernet/ti/cpsw.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c

[PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk

cpsw_cpts_rft_clk has got the choice of 3 clocksources -dpll_core_m4_ck -dpll_core_m5_ck -dpll_disp_m2_ck By default dpll_core_m4_ck is selected, witn this as clock source the CPTS doesnot work properly. It gives clockcheck errors while running PTP. clockcheck: clock jumped backward or

[PATCH 1/6] drivers: net: cpts: Remove hardcoded clock name for CPTS

CPTS refclk name is hardcoded, which makes it fail in case of DRA7x Remove the hardcoded clock name for CPTS refclk and get the same from DT. Signed-off-by: George Cherian george.cher...@ti.com --- drivers/net/ethernet/ti/cpts.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-)

[PATCH 2/6] ARM: dts: am33xx: Add clock names for cpsw and cpts

Add CPSW fck and CPTS clock and clock names Signed-off-by: George Cherian george.cher...@ti.com --- arch/arm/boot/dts/am33xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 9770e35..d1e2b36 100644 ---

[PATCH 0/6] Add CPTS support for AM437x

The series adds CPTS support for AM4372. Patch 1 - CPTS clock name harcoding in the driver is removed. Easier to pass the clock name from dt rather than hardcoding in driver. Also in prepration for DRA7x CPTS support. Patch 2 - DT changes w.r.t clock changes for AM33xx.

OMAP baseline test results for v3.15-rc3

Here are some basic OMAP test results for Linux v3.15-rc3. Logs and other details at: http://www.pwsan.com/omap/testlogs/test_v3.15-rc3/20140427213739/ Test summary Build: uImage: Pass ( 3/ 3): omap1_defconfig, omap1_defconfig_1510innovator_only,