I has been some time, but I have an update to share.
On Sun, May 17, 2015 at 8:06 AM, Alan Stern st...@rowland.harvard.edu wrote:
You might be able to learn more from ftrace. See the instructions in
Documentation/trace/ftrace.txt. The irqsoff tracer may be the best
one to try.
I used ftrace
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031:
Linux 4.1-rc1 (2015-04-26 17:59:10 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/ohad/hwspinlock.git
tags/hwspinlock-4.2
for you to fetch changes up to
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031:
Linux 4.1-rc1 (2015-04-26 17:59:10 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/ohad/remoteproc.git
tags/remoteproc-4.2
for you to fetch changes up to
The sDMA requests are routed through the DMA crossbar and without the
crossbar only peripherals using DMA request 0-127 can be used.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
Hi Tony,
as you have suggested:
http://permalink.gmane.org/gmane.linux.ports.arm.omap/125999
the DTS
Hi,
On 24/06/2015 at 11:26:54 -0500, Nishanth Menon wrote :
I am wrong here - code just returns 0 and ignores err. So, how about
the following patch instead: (Alexandre, please do let me know if the
entire series needs to be reposted):
Can you resend just that one as v3? I'll take it right
On Wed 2015-07-01 03:34:22, Tony Lindgren wrote:
* Pavel Machek pa...@ucw.cz [150701 03:02]:
On Wed 2015-07-01 09:22:55, Pali Rohár wrote:
On Tuesday 30 June 2015 23:59:33 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150630 02:55]:
I will try 4.2 at the end of week.
Hi,
On 06/08/2015 04:22 PM, Peter Ujfalusi wrote:
Hi,
Changes since v01:
- Drop change in compatible for the crossbar driver and do the configuration
based on the DT structure.
The ti-dma-crossbar driver in it's current form can work when it is used with
sDMA (omap-dma). On DRA7x
On Wed 2015-07-01 09:22:55, Pali Rohár wrote:
On Tuesday 30 June 2015 23:59:33 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150630 02:55]:
I will try 4.2 at the end of week.
At least today's 4.1.0-11549-g05a8256 boots just fine on my n900.
Regards,
Tony
So,
* Pavel Machek pa...@ucw.cz [150701 03:02]:
On Wed 2015-07-01 09:22:55, Pali Rohár wrote:
On Tuesday 30 June 2015 23:59:33 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150630 02:55]:
I will try 4.2 at the end of week.
At least today's 4.1.0-11549-g05a8256 boots
* Tony Lindgren t...@atomide.com [150701 00:34]:
This should be OK for most cases as the GPIO interrupt devices are
typically on some external bus like I2C or GPMC. The hurting case
would be bitbanging GPIO devices, like the CBUS I2C driver.
Thinking about it the CBUS I2C driver does not need
Tony Lindgren t...@atomide.com writes:
Hi,
* Tony Lindgren t...@atomide.com [150616 04:48]:
Hi,
Here's a late pull request that would be good to get into v4.2.
This series mostly just drops code that's now unnecessary, and
also fixes potential interrupt re-entrancy issues that the old
On Tuesday 30 June 2015 23:59:33 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [150630 02:55]:
I will try 4.2 at the end of week.
At least today's 4.1.0-11549-g05a8256 boots just fine on my n900.
Regards,
Tony
So, Pavel can you re-test? Maybe there can be problem with some
* Sebastian Andrzej Siewior bige...@linutronix.de [150630 09:39]:
On 06/30/2015 12:55 PM, Grygorii Strashko wrote:
May be you have some thought?
If I remember it properly, you must not sleep but you do so on wakeup.
At least you take spinlocks (spinlocks not raw_spinlocks). One question
* Michael Allwright michael.allwri...@upb.de [150630 06:46]:
Two things seem a bit strange here, 1. The power change statement to
0.7V, I think this should be 1.8V, right? At least this is what I see
on the other MMC buses. 2. The set clock statement seems to repeat 4
times before giving up
AES_CTRL_REG is used to configure AES mode. Before configuring
any mode we need to make sure all other modes are reset or else
driver will misbehave. So mask all modes before configuring
any AES mode.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes.c | 13
Now the driver supports gcm mode, add omap-aes-gcm
algo info to omap-aes driver.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c
index
OMAP AES hw supports aes gcm mode.
Adding support for GCM mode in omap-aes driver.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/Makefile |3 +-
drivers/crypto/omap-aes-gcm.c | 304 +
drivers/crypto/omap-aes.c | 238
Adding simple speed tests for a range of block sizes for Async AEAD crypto
algorithms.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
crypto/tcrypt.c | 233 +++
crypto/tcrypt.h |1 +
2 files changed, 234 insertions(+)
diff --git
Check if the inputs are not aligned, if not process
the input before starting the hw acceleration.
Similarly after completition of hw acceleration.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes-gcm.c | 82 +
1 file changed,
Its not necessary that assoc data and plain text is passed always.
Add these checks before processing the input.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes-gcm.c | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git
OMAP AES driver returns an error if the data is not aligned with
AES_BLOCK_SIZE bytes.
But OMAP AES hw allows data input upto 1 byte aligned, but still
zeros are to be appended and complete AES_BLOCK_SIZE has to be written.
And correct length has to be passed in LENGTH field.
Adding support for
Add aead_request_cast() api to get pointer to aead_request
from cryto_async_request.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
include/linux/crypto.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/crypto.h b/include/linux/crypto.h
index 10df5d2..20fac3d
Use BIT()/GENMASK() macros for all register definitions instead of
hand-writing bit masks.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git
Add support for PIO mode for GCM mode.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/crypto/omap-aes-gcm.c | 10 ++
drivers/crypto/omap-aes.c | 24 ++--
drivers/crypto/omap-aes.h |3 ++-
3 files changed, 26 insertions(+), 11 deletions(-)
This series does some basic cleanup and adds support for
AES GCM mode for omap aes driver.
Also adds a test case for async aead algos.
Tested on BeagelBoneBlack: http://pastebin.ubuntu.com/11808341/
Lokesh Vutla (10):
crypto: omap-aes: Add support for lengths not aligned with
* Pali Rohár pali.ro...@gmail.com [150630 02:55]:
I will try 4.2 at the end of week.
At least today's 4.1.0-11549-g05a8256 boots just fine on my n900.
Regards,
Tony
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