Re: [PATCH v11 2/9] ARM: l2c: use l2c_write_sec() for restoring latency and filter regs

Hello, On 2015-01-05 18:20, Nishanth Menon wrote: On 13:19-20150105, Marek Szyprowski wrote: All four register for latency and filter settings cannot be written in non-secure mode and they should go through l2c_write_sec(). More on this can be found in CoreLink Level 2 Cache Controller L2C-310

Re: [PATCH v11 3/9] ARM: l2c: Refactor the driver to use commit-like interface

Hello, On 2015-01-05 18:22, Nishanth Menon wrote: On 13:19-20150105, Marek Szyprowski wrote: From: Tomasz Figa t.f...@samsung.com Certain implementations of secure hypervisors (namely the one found on Samsung Exynos-based boards) do not provide access to individual L2C registers. This makes

[PATCH v12 8/9] ARM: EXYNOS: Add support for non-secure L2X0 resume

accessing l2x0_saved_regs] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm

[PATCH v12 7/9] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa t.f...@samsung.com [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked

[PATCH v12 6/9] ARM: l2c: Add support for overriding prefetch settings

and necessary support in the driver. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto v3.18-rc1, added error message when prefetch related dt property has been provided without any value] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Tested-by: Nishanth Menon n...@ti.com

[PATCH v12 9/9] ARM: dts: exynos4: Add nodes for L2 cache controller

From: Tomasz Figa t.f...@samsung.com This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene

[PATCH v12 3/9] ARM: l2c: Refactor the driver to use commit-like interface

those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto 'ARM: l2c: use l2c_write_sec() for restoring latency and filter regs' patch] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Tested-by: Nishanth Menon n...@ti.com Acked-by: Tony Lindgren t

[PATCH v12 2/9] ARM: l2c: use l2c_write_sec() for restoring latency and filter regs

for r3p3, but it should be uniform for all revisions. Reported-by: Nishanth Menon n...@ti.com Suggested-by: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Tested-by: Nishanth Menon n...@ti.com Acked-by: Nishanth Menon n...@ti.com Acked-by: Tony Lindgren t

[PATCH v12 4/9] ARM: l2c: Add interface to ask hypervisor to configure L2C

the hardware according to specified parameters. This patch adds such. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Tested-by: Nishanth Menon n...@ti.com Acked-by: Nishanth Menon n...@ti.com Acked-by: Tony Lindgren t...@atomide.com --- arch

[PATCH v12 0/9] Enable L2 cache support on Exynos4210/4x12 SoCs

message about missing properties values Changes since v4: (https://lkml.org/lkml/2014/8/26/461) - rewrote the code accessing l2x0_saved_regs from assembly code - added comment and reworked unconditional call to SMC_CMD_L2X0INVALL Patch summary: Marek Szyprowski (2): ARM: OMAP2+: use common

[PATCH v12 5/9] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

, even though it can be already set earlier. This patch fixes this by making the assignment conditional, depending on whether current .write_sec callback is NULL. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Tested-by: Nishanth Menon n

[PATCH v12 1/9] ARM: OMAP2+: use common l2cache initialization code

This patch implements generic DT L2C initialisation (the one from init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c. Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Tested-by: Nishanth Menon n...@ti.com

[PATCH v11 2/9] ARM: l2c: use l2c_write_sec() for restoring latency and filter regs

for r3p3, but it should be uniform for all revisions. Reported-by: Nishanth Menon n...@ti.com Suggested-by: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 16 1 file changed, 8 insertions(+), 8 deletions

[PATCH v11 8/9] ARM: EXYNOS: Add support for non-secure L2X0 resume

accessing l2x0_saved_regs] Sigend-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm

[PATCH v11 1/9] ARM: OMAP2+: use common l2cache initialization code

This patch implements generic DT L2C initialisation (the one from init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c. Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-omap2/board

[PATCH v11 9/9] ARM: dts: exynos4: Add nodes for L2 cache controller

From: Tomasz Figa t.f...@samsung.com This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene

[PATCH v11 6/9] ARM: l2c: Add support for overriding prefetch settings

and necessary support in the driver. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto v3.18-rc1, added error message when prefetch related dt property has been provided without any value] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- Documentation/devicetree

[PATCH v11 7/9] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa t.f...@samsung.com [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked

[PATCH v11 3/9] ARM: l2c: Refactor the driver to use commit-like interface

those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto 'ARM: l2c: use l2c_write_sec() for restoring latency and filter regs' patch] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 210

[PATCH v11 4/9] ARM: l2c: Add interface to ask hypervisor to configure L2C

the hardware according to specified parameters. This patch adds such. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/include/asm/outercache.h | 3 +++ arch/arm/mm/cache-l2x0.c | 6 ++ 2 files changed, 9 insertions

[PATCH v11 5/9] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

, even though it can be already set earlier. This patch fixes this by making the assignment conditional, depending on whether current .write_sec callback is NULL. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/kernel/irq.c | 3

[PATCH v11 0/9] Enable L2 cache support on Exynos4210/4x12 SoCs

: Marek Szyprowski (2): ARM: OMAP2+: use common l2cache initialization code ARM: l2c: use l2c_write_sec() for restoring latency and filter regs Tomasz Figa (7): ARM: l2c: Refactor the driver to use commit-like interface ARM: l2c: Add interface to ask hypervisor to configure L2C ARM: l2c

[PATCH v10 3/8] ARM: l2c: Add interface to ask hypervisor to configure L2C

the hardware according to specified parameters. This patch adds such. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/include/asm/outercache.h | 3 +++ arch/arm/mm/cache-l2x0.c | 6 ++ 2 files changed, 9 insertions

[PATCH v10 6/8] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa t.f...@samsung.com [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked

[PATCH v10 0/8] Enable L2 cache support on Exynos4210/4x12 SoCs

accessing l2x0_saved_regs from assembly code - added comment and reworked unconditional call to SMC_CMD_L2X0INVALL Patch summary: Marek Szyprowski (1): ARM: OMAP2+: use common l2cache initialization code Tomasz Figa (7): ARM: l2c: Refactor the driver to use commit-like interface ARM: l2c: Add

[PATCH v10 5/8] ARM: l2c: Add support for overriding prefetch settings

and necessary support in the driver. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto v3.18-rc1, added error message when prefetch related dt property has been provided without any value] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- Documentation/devicetree

[PATCH v10 7/8] ARM: EXYNOS: Add support for non-secure L2X0 resume

accessing l2x0_saved_regs] Sigend-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm

[PATCH v10 8/8] ARM: dts: exynos4: Add nodes for L2 cache controller

From: Tomasz Figa t.f...@samsung.com This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene

[PATCH v10 4/8] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

, even though it can be already set earlier. This patch fixes this by making the assignment conditional, depending on whether current .write_sec callback is NULL. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/kernel/irq.c | 3

[PATCH v10 2/8] ARM: l2c: Refactor the driver to use commit-like interface

those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 210 ++- 1 file changed, 115 insertions(+), 95 deletions(-) diff --git a/arch/arm/mm/cache

[PATCH v10 1/8] ARM: OMAP2+: use common l2cache initialization code

This patch implements generic DT L2C initialisation (the one from init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c. Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-omap2/board

Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)

I did it right: https://lkml.org/lkml/2014/12/23/158 Please test, because I have no access to Omap hardware. Best regards -- Marek Szyprowski, PhD Samsung RD Institute Poland -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord

Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)

On 2014-12-11 10:29, Russell King - ARM Linux wrote: On Wed, Dec 10, 2014 at 10:42:33AM +0100, Marek Szyprowski wrote: I assume that now it won't be possible to get l2c patches back to -next, so I will resend them (again...) with the omap related fix. What, you mean you don't know

Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)

) else cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); - return __l2c_init(data, aux_val, aux_mask, cache_id); + r = __l2c_init(data, aux_val, aux_mask, cache_id); + pr_err(%s: %d\n, __func__, r); + return r; } Best regards -- Marek Szyprowski, PhD

Re: [PATCH v9 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

Hello, On 2014-11-27 23:51, Russell King - ARM Linux wrote: On Mon, Nov 17, 2014 at 12:48:22PM +0100, Marek Szyprowski wrote: This is an updated patchset, which intends to add support for L2 cache on Exynos4 SoCs on boards running under secure firmware, which requires certain initialization

[PATCH v9 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

This is an updated patchset, which intends to add support for L2 cache on Exynos4 SoCs on boards running under secure firmware, which requires certain initialization steps to be done with help of firmware, as selected registers are writable only from secure mode. First four patches extend

[PATCH v9 4/7] ARM: l2c: Add support for overriding prefetch settings

and necessary support in the driver. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto v3.18-rc1, added error message when prefetch related dt property has been provided without any value] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- Documentation/devicetree

[PATCH v9 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

This is an updated patchset, which intends to add support for L2 cache on Exynos4 SoCs on boards running under secure firmware, which requires certain initialization steps to be done with help of firmware, as selected registers are writable only from secure mode. First four patches extend

[PATCH v9 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller

From: Tomasz Figa t.f...@samsung.com This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene

[PATCH v9 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume

accessing l2x0_saved_regs, rebased onto v3.18-rc3] Sigend-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene@samsung.com --- arch/arm/mach-exynos/Makefile | 1 + arch/arm/mach-exynos/sleep.S | 48

[PATCH v9 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

, even though it can be already set earlier. This patch fixes this by making the assignment conditional, depending on whether current .write_sec callback is NULL. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/kernel/irq.c | 3

[PATCH v9 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C

the hardware according to specified parameters. This patch adds such. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/include/asm/outercache.h | 3 +++ arch/arm/mm/cache-l2x0.c | 6 ++ 2 files changed, 9 insertions

[PATCH v9 1/7] ARM: l2c: Refactor the driver to use commit-like interface

those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 210 ++- 1 file changed, 115 insertions(+), 95 deletions(-) diff --git a/arch/arm/mm/cache

[PATCH v9 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa t.f...@samsung.com [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL, rebased onto v3.18-rc3] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd

Re: [PATCH v8 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

Hello, On 2014-11-14 15:51, Arnd Bergmann wrote: On Friday 14 November 2014 15:11:58 Marek Szyprowski wrote: I assume that after all comments from previous versions, no more changes are needed to this patchset and I would really like to have it queued to v3.19. Arnd, Olof: could you take

Re: [PATCH v8 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

Hello, On 2014-11-13 14:18, Marek Szyprowski wrote: This is an updated patchset, which intends to add support for L2 cache on Exynos4 SoCs on boards running under secure firmware, which requires certain initialization steps to be done with help of firmware, as selected registers are writable

[PATCH v8 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume

accessing l2x0_saved_regs] Sigend-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index e3c373082bbe

[PATCH v8 1/7] ARM: l2c: Refactor the driver to use commit-like interface

those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 210 ++- 1 file changed, 115 insertions(+), 95 deletions(-) diff --git a/arch/arm/mm/cache

[PATCH v8 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller

From: Tomasz Figa t.f...@samsung.com This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/boot/dts/exynos4210.dtsi | 9 + arch/arm/boot/dts

[PATCH v8 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

, even though it can be already set earlier. This patch fixes this by making the assignment conditional, depending on whether current .write_sec callback is NULL. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/kernel/irq.c | 3

[PATCH v8 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C

the hardware according to specified parameters. This patch adds such. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/include/asm/outercache.h | 3 +++ arch/arm/mm/cache-l2x0.c | 6 ++ 2 files changed, 9 insertions

[PATCH v8 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa t.f...@samsung.com [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-exynos/firmware.c | 50

[PATCH v8 4/7] ARM: l2c: Add support for overriding prefetch settings

and necessary support in the driver. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto v3.18-rc1, added error message when prefetch related dt property has been provided without any value] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- Documentation/devicetree

[PATCH v8 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

This is an updated patchset, which intends to add support for L2 cache on Exynos4 SoCs on boards running under secure firmware, which requires certain initialization steps to be done with help of firmware, as selected registers are writable only from secure mode. First four patches extend

[PATCH v7 0/8] Enable L2 cache support on Exynos4210/4x12 SoCs

: Marek Szyprowski (1): ARM: l2c: unify L2C-310 OF initialization error messages Tomasz Figa (7): ARM: l2c: Refactor the driver to use commit-like interface ARM: l2c: Add interface to ask hypervisor to configure L2C ARM: l2c: Get outer cache .write_sec callback from mach_desc only

[PATCH v7 4/8] ARM: l2c: shorten warning about incorrect associativity

Warning message about missing/incorrect associativity was a bit too long, so shorten it to fit a single line. Suggested-by: Russell King - ARM Linux li...@arm.linux.org.uk Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 4 ++-- 1 file changed, 2 insertions

[PATCH v7 8/8] ARM: dts: exynos4: Add nodes for L2 cache controller

From: Tomasz Figa t.f...@samsung.com This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/boot/dts/exynos4210.dtsi | 9 + arch/arm/boot/dts

[PATCH v7 2/8] ARM: l2c: Add interface to ask hypervisor to configure L2C

the hardware according to specified parameters. This patch adds such. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/include/asm/outercache.h | 3 +++ arch/arm/mm/cache-l2x0.c | 6 ++ 2 files changed, 9 insertions

[PATCH v7 6/8] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa t.f...@samsung.com [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-exynos/firmware.c | 50

[PATCH v7 3/8] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

, even though it can be already set earlier. This patch fixes this by making the assignment conditional, depending on whether current .write_sec callback is NULL. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/kernel/irq.c | 3

[PATCH v7 1/8] ARM: l2c: Refactor the driver to use commit-like interface

those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 210 ++- 1 file changed, 115 insertions(+), 95 deletions(-) diff --git a/arch/arm/mm/cache

[PATCH v7 7/8] ARM: EXYNOS: Add support for non-secure L2X0 resume

accessing l2x0_saved_regs] Sigend-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index e3c373082bbe

[PATCH v7 5/8] ARM: l2c: Add support for overriding prefetch settings

and necessary support in the driver. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto v3.18-rc1, added error message when prefetch related dt property has been provided without any value] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- Documentation/devicetree

[PATCH v6 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

This is an updated patchset, which intends to add support for L2 cache on Exynos4 SoCs on boards running under secure firmware, which requires certain initialization steps to be done with help of firmware, as selected registers are writable only from secure mode. First four patches extend

[PATCH v6 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

, even though it can be already set earlier. This patch fixes this by making the assignment conditional, depending on whether current .write_sec callback is NULL. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/kernel/irq.c | 3

[PATCH v6 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume

accessing l2x0_saved_regs] Sigend-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index e3c373082bbe

[PATCH v6 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa t.f...@samsung.com [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-exynos/firmware.c | 50

[PATCH v6 4/7] ARM: l2c: Add support for overriding prefetch settings

and necessary support in the driver. Signed-off-by: Tomasz Figa t.f...@samsung.com [mszyprow: rebased onto v3.18-rc1, added error messages when property value is missing] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- Documentation/devicetree/bindings/arm/l2cc.txt | 10 + arch/arm/mm

[PATCH v6 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller

From: Tomasz Figa t.f...@samsung.com This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/boot/dts/exynos4210.dtsi | 9 + arch/arm/boot/dts

[PATCH v6 1/7] ARM: l2c: Refactor the driver to use commit-like interface

those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 210 ++- 1 file changed, 115 insertions(+), 95 deletions(-) diff --git a/arch/arm/mm/cache

[PATCH v6 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C

the hardware according to specified parameters. This patch adds such. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/include/asm/outercache.h | 3 +++ arch/arm/mm/cache-l2x0.c | 6 ++ 2 files changed, 9 insertions

Re: [PATCH v6 4/7] ARM: l2c: Add support for overriding prefetch settings

Hello, On 2014-10-27 12:14, Russell King - ARM Linux wrote: On Mon, Oct 27, 2014 at 12:05:47PM +0100, Marek Szyprowski wrote: From: Tomasz Figa t.f...@samsung.com Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch settings configured in registers leading to crashes

[PATCH v5 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs

This is an updated patchset, which intends to add support for L2 cache on Exynos4 SoCs on boards running under secure firmware, which requires certain initialization steps to be done with help of firmware, as selected registers are writable only from secure mode. First four patches extend

[PATCH v5 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310

this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa t.f...@samsung.com [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-exynos/firmware.c | 50

[PATCH v5 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller

From: Tomasz Figa t.f...@samsung.com This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/boot/dts/exynos4210.dtsi | 9 + arch/arm/boot/dts

[PATCH v5 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume

accessing l2x0_saved_regs] Sigend-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index e3c373082bbe

[PATCH v5 4/7] ARM: l2c: Add support for overriding prefetch settings

and necessary support in the driver. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- Documentation/devicetree/bindings/arm/l2cc.txt | 10 +++ arch/arm/mm/cache-l2x0.c | 39 ++ 2 files changed

[PATCH v5 1/7] ARM: l2c: Refactor the driver to use commit-like interface

those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/mm/cache-l2x0.c | 210 ++- 1 file changed, 115 insertions(+), 95 deletions(-) diff --git a/arch/arm/mm/cache

[PATCH v5 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL

, even though it can be already set earlier. This patch fixes this by making the assignment conditional, depending on whether current .write_sec callback is NULL. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/kernel/irq.c | 3

[PATCH v5 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C

the hardware according to specified parameters. This patch adds such. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com --- arch/arm/include/asm/outercache.h | 3 +++ arch/arm/mm/cache-l2x0.c | 6 ++ 2 files changed, 9 insertions

Re: [PATCH 0/5] OMAP IOMMU fixes and IOMMU architecture questions

, Mar 14, 2014 at 12:00:16PM +0100, Laurent Pinchart wrote: Hi Suman, (CC'ing Joerg Roedel and Marek Szyprowski for the core IOMMU discussion) On Thursday 13 March 2014 21:33:37 Suman Anna wrote: On 03/07/2014 06:46 PM, Laurent Pinchart wrote: Hello, This patch set fixes miscellaneous

RE: Converting OMAP's custom vram allocator

Hello, On Friday, September 07, 2012 12:55 PM Tomi Valkeinen wrote: On Fri, 2012-09-07 at 07:55 +0200, Marek Szyprowski wrote: Hello, On Wednesday, September 05, 2012 12:09 PM Tomi Valkeinen wrote: OMAP has a custom video ram allocator, which I'd like to remove and use

RE: Converting OMAP's custom vram allocator

for solving this quite common use case. Best regards -- Marek Szyprowski Samsung Poland RD Center -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

RE: [RFC PATCH v2 4/8] media: videobuf2: introduce VIDEOBUF2_PAGE memops

only a pointer to kernel virtual mapping, but you pass a struct page * there. (snipped) Best regards -- Marek Szyprowski Samsung Poland RD Center -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info

RE: Changing IOMMU-API for generic DMA-mapping supported by the hardware

(). Each IOMMU implementation can provide these calls based on internal bitmap allocator which will also cover the issue with reserved ranges. What do you think about such solution? Best regards -- Marek Szyprowski Samsung Poland RD Center -- To unsubscribe from this list: send the line unsubscribe