On Wed, 2012-04-11 at 20:44 -0600, Paul Walmsley wrote:
This is useful not only for OMAP4 and AM3517/3505, but also will probably
be useful for the C6x chips that Mark Salter is working on.
I have been keeping an occasional eye on these patches but I don't see
any usefulness for the currently
On Tue, 2011-11-22 at 13:11 +, Arnd Bergmann wrote:
On Tuesday 22 November 2011, Mike Turquette wrote:
+static void clk_hw_gate_set_bit(struct clk *clk)
+{
+ struct clk_hw_gate *gate = to_clk_hw_gate(clk);
+ u32 reg;
+
+ reg = __raw_readl(gate-reg);
+ reg
On Wed, 2011-08-31 at 20:35 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 07:19:33PM +0100, Rob Herring wrote:
On 08/31/2011 12:51 PM, Will Deacon wrote:
Another thing that Marc and I tried on OMAP4 was not bringing up the
secondary
CPU during boot (by commenting out most of
On Wed, 2011-08-31 at 09:49 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why this write buffer issue did not happen at UP ARM V7
platform, whose dma buffer
also uncache, but bufferable?
Which CPU was on this platform?
Using
On Wed, 2011-08-31 at 16:21 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 02:43:33PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 09:49 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why this write buffer issue did
On Wed, 2011-08-31 at 13:49 -0500, Rob Herring wrote:
An outer_sync will only drain the write buffer of the L2. It does not
flush the cache though. If the write buffer does in fact keep data as
long as possible (until it needs a free slot or the line is full), then
long delays to write out
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
+/*
+ * Writing to dma coherent memory on ARM may be delayed via L2
+ * writing buffer, so introduce the helper which can flush L2 writing
+ * buffer into memory immediately, especially used to flush ehci
+ * descriptor to
On Tue, 2011-08-30 at 13:15 -0400, Alan Stern wrote:
On Tue, 30 Aug 2011, Mark Salter wrote:
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
+/*
+ * Writing to dma coherent memory on ARM may be delayed via L2
+ * writing buffer, so introduce the helper which can
On Mon, 2011-08-29 at 23:55 +0800, Ming Lei wrote:
If writing to coherent memory can't reach physical memory immediately on
other ARCHs, the problem can still happen on these ARCHs. But I am
not sure if there are these kind of ARCHs except for ARM.
If there is write buffering which prevents
