USE_PM_CLK_RUNTIME_OPS is introduced so we don't repeat the same code
to do runtime_suspend and runtime_resume across users of PM clocks.
Use it to remove the boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
Reviewed-by: Kevin Hilman khil...@linaro.org
Acked-by: Santosh
Most users of PM clocks do the exact same thing in runtime callbacks.
Provide default callbacks and cleanup the existing users (keystone/davinci
/omap1/sh)
Rajendra Nayak (5):
PM / clock_ops: Provide default runtime ops to users
arm: keystone: remove boilerplate code and use
USE_PM_CLK_RUNTIME_OPS is introduced so we don't repeat the same code
to do runtime_suspend and runtime_resume across users of PM clocks.
Use it to remove the boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
Reviewed-by: Kevin Hilman khil...@linaro.org
Acked-by: Santosh
USE_PM_CLK_RUNTIME_OPS is introduced so we don't repeat the same code
to do runtime_suspend and runtime_resume across users of PM clocks.
Use it to remove the boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
Reviewed-by: Kevin Hilman khil...@linaro.org
Acked-by: Santosh
USE_PM_CLK_RUNTIME_OPS is introduced so we don't repeat the same code
to do runtime_suspend and runtime_resume across users of PM clocks.
Use it to remove the boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
Reviewed-by: Kevin Hilman khil...@linaro.org
Acked-by: Santosh
Most users of PM clocks do the extact same things in the runtime
suspend/resume callbacks. Provide them USE_PM_CLK_RUNTIME_OPS so
as to avoid/remove boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
Reviewed-by: Kevin Hilman khil...@linaro.org
Acked-by: Santosh Shilimkar ssant
On Tue, Apr 21, 2015 at 1:25 AM, santosh shilimkar
santosh.shilim...@oracle.com wrote:
On 4/20/2015 4:21 PM, Kevin Hilman wrote:
Rajendra Nayak rna...@codeaurora.org writes:
Most users of PM clocks do the exact same thing in runtime callbacks.
Probably because they were all copied from
Most users of PM clocks do the exact same thing in runtime callbacks.
Provide default callbacks and cleanup the existing users
(keystone/davinci/omap1/sh)
Rajendra Nayak (5):
PM / clock_ops: Provide default runtime ops to users
arm: keystone: remove boilerplate code and use
Most users of PM clocks do the extact same things in the runtime
suspend/resume callbacks. Provide them USE_PM_CLK_RUNTIME_OPS so
as to avoid/remove boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
drivers/base/power/clock_ops.c | 38
USE_PM_CLK_RUNTIME_OPS is introduced so we don't repeat the same code
to do runtime_suspend and runtime_resume across users of PM clocks.
Use it to remove the boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
arch/arm/mach-keystone/pm_domain.c | 33
USE_PM_CLK_RUNTIME_OPS is introduced so we don't repeat the same code
to do runtime_suspend and runtime_resume across users of PM clocks.
Use it to remove the boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
drivers/sh/pm_runtime.c | 47
USE_PM_CLK_RUNTIME_OPS is introduced so we don't repeat the same code
to do runtime_suspend and runtime_resume across users of PM clocks.
Use it to remove the boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
arch/arm/mach-omap1/pm_bus.c | 37
USE_PM_CLK_RUNTIME_OPS is introduced so we don't repeat the same code
to do runtime_suspend and runtime_resume across users of PM clocks.
Use it to remove the boilerplate code.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
arch/arm/mach-davinci/pm_domain.c | 32
...@ti.com
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v1:
* changed the clock domain to pcie_clkdm
* Added PCIe as a slave port for l3_main.
Looks good to me,
Reviewed-by: Rajendra Nayak rna...@ti.com
Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402
...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Tested-by: Kishon Vijay Abraham I kis...@ti.com
Looks good to me, feel free to add
Reviewed-by: Rajendra Nayak rna...@ti.com
---
Please find the bootlog with these hwmod patches
http
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I
On Thursday 19 June 2014 01:20 AM, Roger Quadros wrote:
This module is needed for the SATA and PCIe PHYs.
Signed-off-by: Roger Quadros rog...@ti.com
Tested-by: Roger Quadros rog...@ti.com
Reviewed-by: Rajendra Nayak rna...@ti.com
---
v2:
- added .main_clk to hwmod.
- moved interface
.mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.
Signed-off-by: Roger Quadros rog...@ti.com
Tested-by: Roger Quadros rog...@ti.com
Reviewed-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 6
On Tuesday 27 May 2014 02:25 PM, Rajendra Nayak wrote:
Without the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
53200
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
53200
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div
On Friday 09 May 2014 06:07 PM, Sekhar Nori wrote:
From: Lokesh Vutla lokeshvu...@ti.com
RTCSS on DRA7 provides a precise real-time clock.
Add hwmod entry for this IP.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Sekhar Nori nsek...@ti.com
Reviewed-by: Rajendra Nayak rna
On Wednesday 18 June 2014 01:32 PM, Roger Quadros wrote:
On 04/23/2014 08:35 PM, Roger Quadros wrote:
From: Nikhil Devshatwar nikhil...@ti.com
Add hwmods for ocp2scp3 and sata modules.
From what I see this is actually adding the ocp2scp3 data and fixing up some
of the sata data which is
against TRM version vP, looks good to me.
Reviewed-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index
On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
This module is needed for the SATA and PCIe PHYs.
Signed-off-by: Roger Quadros rog...@ti.com
Tested-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +
1 file changed, 25
a divider clock,
with the default divider set to 2. l4 then derived from l3 is a fixed factor
clock, but the fixed divider is 2 and not 1. Which means the l3 clock is
half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch)
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/boot
On Monday 26 May 2014 04:14 PM, Archit Taneja wrote:
Generally, IP blocks/modules within a clock domain each have their own
CM_x_CLKCTRL register, each having it's own MODULEMODE field to manage the
module.
DSS clockdoain, however, has multiple modules in it, but only one register
named
On Monday 19 May 2014 08:57 PM, Nishanth Menon wrote:
Currently the files in /sys/devices/soc0/ show no information about
DRA7. Few userspace programs do depend on this information to make SoC
specific support. So update logic to detect the relevant information and
provide to userspace.
opt_clks
for all such instances.
The modules (like GPIO and DSS) which do have this need to handle optional
clocks during a ocp softreset are marked with a flag
'HWMOD_CONTROL_OPT_CLKS_IN_RESET'
so its easy to identify the ones which don't have this requirement.
Signed-off-by: Rajendra Nayak rna
On Tuesday 20 May 2014 11:01 AM, Archit Taneja wrote:
Hi,
On Friday 16 May 2014 01:44 PM, Tomi Valkeinen wrote:
On 12/05/14 18:48, Tony Lindgren wrote:
Also, I'm wondering why we still have .clk and .opt_clks entries in the
hwmod data for am43xx and omap5 which are both device tree based
On Friday 09 May 2014 05:26 PM, Tomi Valkeinen wrote:
From: Sathya Prakash M R sath...@ti.com
Add DSS hwmod data for AM43xx.
Signed-off-by: Sathya Prakash M R sath...@ti.com
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 104
On Monday 19 May 2014 03:42 PM, Tomi Valkeinen wrote:
On 19/05/14 12:24, Rajendra Nayak wrote:
On Friday 09 May 2014 05:26 PM, Tomi Valkeinen wrote:
From: Sathya Prakash M R sath...@ti.com
Add DSS hwmod data for AM43xx.
Signed-off-by: Sathya Prakash M R sath...@ti.com
Signed-off-by: Tomi
On Monday 19 May 2014 04:40 PM, Tomi Valkeinen wrote:
On 19/05/14 13:28, Rajendra Nayak wrote:
Yeah, thats what it looks like to me. l3_gclk is the 200Mhz clock derived
from
core-m4 post divider and l3s_gclk/l4ls_gclk are half of that at 100Mhz,
derived
using a fixed divider of 2
On Thursday 08 May 2014 05:38 AM, Paul Walmsley wrote:
Hi Rajendra,
On Wed, 23 Apr 2014, Rajendra Nayak wrote:
The patches fix some opt clock handling in gpio and in
hwmod.
Rajendra Nayak (2):
gpio: omap: prepare and unprepare the debounce clock
ARM: OMAP2+: hwmod: Don't leave
On Wednesday 23 April 2014 11:41 AM, Rajendra Nayak wrote:
Replace the clk_enable()s with a clk_prepare_enable() and
the clk_disables()s with a clk_disable_unprepare()
This never showed issues due to the OMAP platform code (hwmod)
leaving these clocks in clk_prepare()ed state by default
On Thursday 08 May 2014 02:56 PM, Javier Martinez Canillas wrote:
Hello Rajendra,
On Thu, May 8, 2014 at 9:06 AM, Rajendra Nayak rna...@ti.com wrote:
On Wednesday 23 April 2014 11:41 AM, Rajendra Nayak wrote:
Replace the clk_enable()s with a clk_prepare_enable() and
the clk_disables()s
On Thursday 08 May 2014 05:34 PM, Javier Martinez Canillas wrote:
Hello Rajendra,
On Thu, May 8, 2014 at 1:10 PM, Rajendra Nayak rna...@ti.com wrote:
On Thursday 08 May 2014 02:56 PM, Javier Martinez Canillas wrote:
Hello Rajendra,
On Thu, May 8, 2014 at 9:06 AM, Rajendra Nayak rna
On Tuesday 06 May 2014 09:58 PM, Tony Lindgren wrote:
* Rajendra Nayak rna...@ti.com [140429 04:22]:
On Tuesday 29 April 2014 04:48 PM, Arnd Bergmann wrote:
On Tuesday 29 April 2014 16:35:13 Rajendra Nayak wrote:
@@ -393,7 +395,12 @@ IS_OMAP_TYPE(3430, 0x3430)
#if defined
On Tuesday 29 April 2014 04:35 PM, Rajendra Nayak wrote:
changes in v4:
-1- used full SoC names in compatibles eg ti,dra742 and ti,dra722
-2- Created a seperate patch for replacing __initdata with __initconst
changes in v3:
Removed wildcards from compatible strings and duplicates from
The only difference from the dra74x devices is the missing .smp entry.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch
Use of const init definition must use __initconst so replace
all such instances where __initdata is used.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm
Use the corresponding compatibles to identify the devices.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/soc.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 30abcc8..5ff724e 100644
--- a/arch/arm
core Cortex A15 devices belonging to the
DRA7 family (Similar to the DRA74x devices which are dual core Cortex
A15 based)
The patches (based off 3.15-rc3) add minimal DT/kernel modifications to add
boot support on DRA722 device reusing all the kernel data for DRA742 device.
Rajendra Nayak (5
ti,dra752 is neither documented nor correct, since the device is actually a
dra742 device as rightly documented in dt bindings.
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/dra7-evm.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion
DRA722 is part of DRA72x family which are single core cortex A15 devices
with most infrastructure IPs otherwise same as whats on the DRA74x family.
So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively.
Also add a minimal dra72-evm dts file.
Signed-off-by: Rajendra Nayak rna
On Tuesday 29 April 2014 04:48 PM, Arnd Bergmann wrote:
On Tuesday 29 April 2014 16:35:13 Rajendra Nayak wrote:
@@ -393,7 +395,12 @@ IS_OMAP_TYPE(3430, 0x3430)
#if defined(CONFIG_SOC_DRA7XX)
#undef soc_is_dra7xx
+#undef soc_is_dra74x
+#undef soc_is_dra72x
#define soc_is_dra7xx
On Thursday 24 April 2014 06:43 PM, Arnd Bergmann wrote:
On Thursday 24 April 2014, Rajendra Nayak wrote:
-- DRA742
- compatible = ti,dra7xx, ti,dra7
+- DRA74x
+ compatible = ti,dra74, ti,dra7
+
+- DRA72x
+ compatible = ti,dra72, ti,dra7
Actually, what I meant was that you should
, and limit this patch to just what the patch subject says.
Sure, I will, if that helps.
regards
Suman
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 45
---
1 file changed, 31 insertions(+), 14 deletions(-)
diff
On Monday 28 April 2014 02:20 PM, Arnd Bergmann wrote:
On Monday 28 April 2014 11:39:22 Rajendra Nayak wrote:
DRA742 EVM: Software Developement Board for DRA742
compatible = ti,dra7-evm, ti,dra742, ti,dra74, ti,dra7
DRA722 EVM: Software Development Board for DRA722
compatible = ti,dra72-evm
Use the corresponding compatibles to identify the devices.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/soc.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 30abcc8..5ff724e 100644
--- a/arch/arm
[] __initdata = {
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 45 ---
1 file changed, 31 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board-generic.c
index b8920b6
DRA72x is a single core cortex A15 device with most infrastructure IPs otherwise
same as whats on the DRA74x devices.
So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively.
Also add a minimal dra72-evm dts file.
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc: linux
ti,dra752 is neither documented nor correct, since the device is actually a
dra742 device as rightly documented in dt bindings.
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/dra7-evm.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion
) add minimal DT/kernel modifications to add
boot support for DRA72x devices reusing all the kernel data for DRA74x devices.
Rajendra Nayak (4):
ARM: dts: dra7-evm: Remove the wrong and undocumented compatible
ARM: dts: Add support for DRA72x family of devices
ARM: OMAP2+: Add machine entry
The patches fix some opt clock handling in gpio and in
hwmod.
Rajendra Nayak (2):
gpio: omap: prepare and unprepare the debounce clock
ARM: OMAP2+: hwmod: Don't leave the optional clocks in
clk_prepare()ed state
arch/arm/mach-omap2/omap_hwmod.c | 13 ++---
drivers/gpio/gpio
-by: Rajendra Nayak rna...@ti.com
Cc: linux-g...@vger.kernel.org
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
drivers/gpio/gpio-omap.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers
At hwmod init, theres no reason why optional clocks should be left in
clk_prepare()ed state as these are actually directly controlled by the
drivers themselves. Let the drivers prepare/unprepare as well as enable/
disable them.
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson bcous
On Friday 14 March 2014 02:50 PM, Rajendra Nayak wrote:
DRA752 device is wrongly documented as DRA742 device. Fix the typo.
Thanks to Nishanth for pointing out that the device part number is infact
DRA742. The compatible sting infact seems to have a typo. I'll fix
that up a post a v2
devices.
Rajendra Nayak (4):
ARM: dts: dra7-evm: Remove the wrong and undocumented compatible
ARM: dts: Add support for DRA72x family of devices
ARM: OMAP2+: Add machine entry for dra72x devices
ARM: DRA7: Add support for soc_is_dra74x() and soc_is_dra72x()
varients
.../devicetree
ti,dra752 is neither documented nor correct, since the device is actually a
dra742 device as rightly documented in dt bindings.
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/dra7-evm.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion
[] __initdata = {
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 46 +--
1 file changed, 33 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board-generic.c
index b8920b6
DRA72x is a single core cortex A15 device with most infrastructure IPs otherwise
same as whats on the DRA74x devices.
So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively.
Also add a minimal dra72-evm dts file.
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc: linux
Use the corresponding compatibles to identify the devices.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/soc.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 30abcc8..b8a4834 100644
--- a/arch/arm
On Wednesday 23 April 2014 03:21 PM, Arnd Bergmann wrote:
On Wednesday 23 April 2014 14:32:54 Rajendra Nayak wrote:
#ifdef CONFIG_SOC_DRA7XX
-static const char *dra7xx_boards_compat[] __initdata = {
+static const char *dra74x_boards_compat[] __initconst = {
+ ti,dra74x,
ti
On Saturday 15 March 2014 07:51 AM, Suman Anna wrote:
Hi Rajendra,
On 03/14/2014 04:20 AM, Nayak, Rajendra wrote:
The only difference from the dra75x devices is the missing .smp entry.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 18
/msg94220.html
[2] http://www.spinics.net/lists/linux-omap/msg98490.html
Cc: Nishanth Menon n...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Suman Anna s-a...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |3 ++-
1 file changed
DRA752 device is wrongly documented as DRA742 device. Fix the typo.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
.../devicetree/bindings/arm/omap/omap.txt |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt
b
DRA72x is a single core cortex A15 device with most infrastructure IPs otherwise
same as whats on the DRA75x devices.
So move the cpu nodes into dra75x.dtsi and dra72x.dtsi respectively.
Also add a minimal dra72-evm dts file.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
.../devicetree
DRA72x devices are single core Cortex A15 devices belonging to the
DRA7 family (Similar to the DRA75x devices which are dual core Cortex
A15 based)
The patches add minimal DT/kernel modifications to add boot support for
DRA72x devices resuing all the kernel data for DRA75x devices.
Rajendra
The only difference from the dra75x devices is the missing .smp entry.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board
On Monday 17 February 2014 04:45 AM, Vaibhav Bedia wrote:
Use the correct register offset for issuing the
reset command in OMAP5. Since dev_inst is set dynamically
OMAP4 should not be affected by this change.
Signed-off-by: Vaibhav Bedia vaibhav.be...@gmail.com
Acked-by: Rajendra Nayak rna
On Friday 14 February 2014 04:49 AM, Tony Lindgren wrote:
* Lokesh Vutla lokeshvu...@ti.com [140207 02:24]:
From: Rajendra Nayak rna...@ti.com
The SyncTimer in AM43x is clocked using the following two sources:
1) An inaccuarte 32k clock (CLK_32KHZ) derived from PER DPLL, causing system
[]..
so a bit more work is needed. Maybe also rebase these against
omap-for-v3.14/dt too?
Will do.
Rebased on top of omap-for-v3.14/omap3-board-removal. Patches are on my
k.org tree:
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git wip/omap-fix-intc
It needs a minor build
On Friday 20 December 2013 12:32 AM, Tero Kristo wrote:
On 12/19/2013 08:26 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131219 03:26]:
Divider clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.
This seems to
On Friday 20 December 2013 03:59 PM, Tero Kristo wrote:
On 12/20/2013 12:07 PM, Rajendra Nayak wrote:
On Friday 20 December 2013 12:32 AM, Tero Kristo wrote:
On 12/19/2013 08:26 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131219 03:26]:
Divider clock can now be registered to use
use uart1 for console, boot fails with DEBUG_LL enabled.
Reported-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2
With clocks for OMAP moving to DT, its now possible to pass the 'main_clk'
data for each device from DT instead of having it in hwmod.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions
With support to parse clock data from DT, move all main and optional
clock information from hwmod to DT.
We still retain clocks in hwmod for devices which do not have a DT node.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/boot/dts/omap4.dtsi | 100
/devicetree/msg13455.html
[3] http://www.spinics.net/lists/arm-kernel/msg288036.html
[4] http://www.spinics.net/lists/arm-kernel/msg288023.html
Rajendra Nayak (3):
ARM: OMAP2+: Add support to parse 'main_clk' info from DT
ARM: OMAP2+: Add support to parse optional clk info from DT
ARM: OMAP4: dts
With clocks for OMAP moving to DT, its now possible to pass all optional clock
data for each device from DT instead of having it in hwmod.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 65 --
1 file changed, 63 insertions
the unchecked dereference of arch_pwrdm.
Reported-by: Dan Carpenter dan.carpen...@oracle.com
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/powerdomain.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2
On Tuesday 05 November 2013 06:44 PM, Sricharan R wrote:
Enable the crossbar IP support for DRA7xx soc.
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/mach-omap2
i2c is defined.
Thanks Nishanth.
Acked-by: Rajendra Nayak rna...@ti.com
V1: https://patchwork.kernel.org/patch/3046671/
Nishanth Menon (2):
ARM: dts: OMAP3+: Add i2c aliases
ARM: dts: AM33xx+: Add i2c aliases
arch/arm/boot/dts/am33xx.dtsi |3 +++
arch/arm/boot/dts/am4372.dtsi
On Monday 21 October 2013 05:56 PM, Mike Turquette wrote:
Quoting Paul Walmsley (2013-10-19 10:16:50)
On Fri, 11 Oct 2013, Tero Kristo wrote:
Some drivers require direct access to the autoidle functionality of the
interface clocks. Added clock APIs for these, so that the drivers do not
need
the same if the i2c dev interface have no
consistent numbering. Provide alias to allow ordering the i2c devices
correctly.
This looks good Nishanth. Shouldn't we just go ahead and fix these for
all OMAPs/AMxx devices which would have the same problem as OMAP5 ;)
Acked-by: Rajendra Nayak rna
On Tuesday 15 October 2013 12:57 PM, Benoit Cousson wrote:
Hi Rajendra,
On 09/10/2013 18:45, Benoit Cousson wrote:
+ A couple of DT maintainers
On 09/10/2013 18:41, Rajendra Nayak wrote:
On Wednesday 09 October 2013 08:43 PM, Benoit Cousson wrote:
Hi Rajendra,
On 09/10/2013 12:11
On Wednesday 09 October 2013 12:54 PM, Paul Walmsley wrote:
Hi Benoît, Rajendra,
On Tue, 20 Aug 2013, Rajendra Nayak wrote:
Now that we have DT bindings to specify which devices on the SoC should not
be reset or idled, get rid of the same information existing as part of the
hwmod data
On Wednesday 09 October 2013 01:49 PM, Benoit Cousson wrote:
Hi Rajendra,
On 09/10/2013 09:37, Rajendra Nayak wrote:
On Wednesday 09 October 2013 12:54 PM, Paul Walmsley wrote:
Hi Benoît, Rajendra,
On Tue, 20 Aug 2013, Rajendra Nayak wrote:
Now that we have DT bindings to specify which
on OMAP4 panda es, AM335x EVM and AM335x EVM-SK
[1] http://www.mail-archive.com/linux-omap@vger.kernel.org/msg94349.html
Rajendra Nayak (5):
ARM: OMAP2+: hwmod: cleanup HWMOD_INIT_NO_RESET usage
ARM: dts: omap: Add new bindings for OMAP
ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DT
Now that we have DT bindings to specify which devices should not
be reset and idled during init, make hwmod extract the information
(and store them in internal flags) from Device tree.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 23
Do not reset GPIO0 at boot-up because GPIO0 is used
on AM335x EVM-SK to control VTT regulators on DDR3.
Without this EVM-SK boards fail to boot-up because
of DDR3 corruption.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/boot/dts/am335x-evmsk.dts |4
1 file changed, 4
For modules/IPs/hwmods which do not have
-1- sys-class-reset()
and
-2- hardreset lines
and
-3- No way to do an ocp reset (no sysc control)
the flag 'HWMOD_INIT_NO_RESET' is not much useful.
Cleanup all such instances across various hwmod data files.
Signed-off-by: Rajendra Nayak rna...@ti.com
to pass this information from DT.
Update the am33xx/omap4 and omap5 dtsi files with the
new bindings for modules which either should not be
idled. reset or both. A later patch would cleanup the
same information that exists today as part of the hwmod
data files.
Signed-off-by: Rajendra Nayak rna
as part of GPMC driver
in the kernel, and hence the flag is left as is in hwmod, which can be
removed once the driver does what its expected to.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |4 ++--
arch/arm/mach-omap2/omap_hwmod_44xx_data.c |4
On Wednesday 09 October 2013 08:43 PM, Benoit Cousson wrote:
Hi Rajendra,
On 09/10/2013 12:11, Rajendra Nayak wrote:
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should
On Tuesday 08 October 2013 11:45 PM, Tony Lindgren wrote:
* Rajendra Nayak rna...@ti.com [131003 23:50]:
On Tuesday 01 October 2013 12:34 PM, Afzal Mohammed wrote:
Hi Paul, Benoit, Tony,
This series adds PRCM support (except clock tree) for AM43x SoC's.
Please consider this for inclusion
This split and reuse looks much better and readable now.
For the complete series,
Acked-by: Rajendra Nayak rna...@ti.com
3. Instances where clock domain or clock topology has changed in the few
cases, have separate structures for AM335x and AM43x
4. To handle scenarios where register offsets
[]..
+
+#define pr_fmt(fmt) %s: fmt, __func__
+
+#ifdef DEBUG
+#define prn(num) printk(#num =%d\n, num)
+#define prx(num) printk(#num =%x\n, num)
+#else
+#define prn(num) do { } while (0)
+#define prx(num) do { } while (0)
+#endif
+
+#include linux/err.h
+#include linux/module.h
On Thursday 29 August 2013 10:50 PM, Kevin Hilman wrote:
Rajendra Nayak rna...@ti.com writes:
In order to handle errata I688, a page of sram was reserved by doing a
static iotable map. Now that we use gen_pool to manage sram, we can
completely remove all of these static mappings and use
On Wednesday 28 August 2013 03:54 PM, Sekhar Nori wrote:
On Wednesday 28 August 2013 11:53 AM, Rajendra Nayak wrote:
On Tuesday 27 August 2013 04:53 PM, Sekhar Nori wrote:
On Tuesday 27 August 2013 03:41 PM, Rajendra Nayak wrote:
Use drivers/misc/sram.c driver to manage SRAM on all DT only
general purpose allocator apis instead of
OMAP private ones to manage and use SRAM.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi|5 ++---
arch/arm/boot/dts/am4372.dtsi|5 +
arch/arm/boot/dts/omap4.dtsi |5 +
arch/arm/boot/dts
Remove the empty am33xx_sram_init() function.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/sram.c |7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 4bd0968..305fc2b 100644
--- a/arch/arm/mach-omap2
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