From: Rajendra Nayak rna...@ti.com
patch adds IO Daisychain support for OMAP4 as per section 3.9.4 in OMAP4430
Public TRM.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Tested-by: Govindraj.R govindraj.r...@ti.com
---
Changes done in V3:
1. Moved
As IO Daisy chain sequence is triggered via hwmod mux, there is no need to
control it from cpuidle path for OMAP3.
Also as omap3_disable_io_chain is no longer being used, just remove the
function.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Tested-by: Govindraj.R govindraj.r...@ti.com
, module specific interrupt handler will not triggered for the
second time
Also look at detailed explanation given by Rajendra at
http://www.spinics.net/lists/linux-serial/msg04480.html
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Tested-by: Govindraj.R govindraj.r...@ti.com
---
arch/arm/mach
PM_WKST_WKUP.ST_IO bit by writing 1 to it.
Step [e] [c] in each case can be skipped, as these are handled
by the PRCM interrupt handler later.
[1] http://focus.ti.com/pdfs/wtbu/OMAP36xx_ES1.x_PUBLIC_TRM_vV.zip
Signed-off-by: Mohan V moh...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
IO Daisychain has to be enabled only if the corresponding omap has
io chain wake up capability.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Tested-by: Govindraj.R govindraj.r...@ti.com
---
arch/arm/mach-omap2/prm2xxx_3xxx.c | 26 ++
1 files changed, 14 insertions
/io_daisy_chain_rebased
Mohan V (1):
ARM: OMAP3 PM: correct enable/disable of daisy io chain
Rajendra Nayak (1):
ARM: OMAP4 PM: Add IO Daisychain support
Vishwanath BS (5):
ARM: OMAP3 PM: Move IO Daisychain function to omap3 prm file
ARM: OMAP3 PM: Enable IO Wake up
ARM: OMAP3PLUS PM: Add IO Daisychain
Enable IO Wake up for OMAP3 as part of PM Init.
Currently this has been managed in cpuidle path which is not the right place.
Subsequent patch will remove IO Daisy chain handling in cpuidle path once daisy
chain is handled as part of hwmod mux.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
From: Rajendra Nayak rna...@ti.com
patch adds IO Daisychain support for OMAP4 as per section 3.9.4 in OMAP4430
Public TRM.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Tested-by: Govindraj.R govindraj.r...@ti.com
---
arch/arm/mach-omap2/prm44xx.c
Since IO Daisychain modifies only PRM registers, it makes sense to move it to
PRM File.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Tested-by: Govindraj.R govindraj.r...@ti.com
---
arch/arm/mach-omap2/pm34xx.c | 30 +-
arch/arm/mach-omap2/prm2xxx_3xxx.c
Enable IO Wake up for OMAP3 as part of PM Init.
Currently this has been managed in cpuidle path which is not the right place.
Subsequent patch will remove IO Daisy chain handling in cpuidle path once daisy
chain is handled as part of hwmod mux.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Rajendra Nayak (1):
ARM: OMAP4 PM: Add IO Daisychain support
Vishwanath BS (5):
ARM: OMAP3 PM: Move IO Daisychain function to omap3 prm file
ARM: OMAP3 PM: Enable IO Wake up
ARM: OMAP3PLUS PM: Add IO Daisychain support via hwmod mux
ARM: OMAP3 PM: Remove IO Daisychain control from cpuidle
IO Daisychain has to be enabled only if the corresponding omap has
io wake up capability.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/prm2xxx_3xxx.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c
b/arch
PM_WKST_WKUP.ST_IO bit by writing 1 to it.
Step [e] [c] in each case can be skipped, as these are handled
by the PRCM interrupt handler later.
[1] http://focus.ti.com/pdfs/wtbu/OMAP36xx_ES1.x_PUBLIC_TRM_vV.zip
Signed-off-by: Mohan V moh...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
As IO Daisy chain sequence is triggered via hwmod mux, there is no need to
control it from cpuidle path for OMAP3.
Also as omap3_disable_io_chain is no longer being used, just remove the
function.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/pm34xx.c | 15
From: Rajendra Nayak rna...@ti.com
patch adds IO Daisychain support for OMAP4 as per section 3.9.4 in OMAP4430
Public TRM.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/prm44xx.c | 33
Since IO Daisychain modifies only PRM registers, it makes sense to move it to
PRM File.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/pm34xx.c | 33 +
arch/arm/mach-omap2/prm2xxx_3xxx.c | 35
, module specific interrupt handler will not triggered for the
second time
Also look at detailed explanation given by Rajendra at
http://www.spinics.net/lists/linux-serial/msg04480.html
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
This has been tested on OMAP3 using Chain Handler + UART
on a wrong register which is fixed in this patch.
Also omap3_enable_io_chain is made non static as it's going to be used in
subsequent patches.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/pm.h |1 +
arch/arm/mach-omap2/pm34xx.c |6 +++---
2 files changed, 4
Enable IO Wake up for OMAP3 as part of PM Init.
Currently this has been managed in cpuidle path which is not the right place.
Subsequent patch will remove IO Daisy chain handling in cpuidle path once daisy
chain is handled as part of hwmod mux.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
as it is not really
enabling daisychain feature rather it triggers WUCLK CTRL.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |9 +++--
arch/arm/mach-omap2/pm.c |9 +
arch/arm/mach-omap2/pm.h |3 ++-
arch/arm/mach-omap2
From: Rajendra Nayak rna...@ti.com
patch adds IO Daisychain support for OMAP4 as per section 3.9.4 in OMAP4430
Public TRM.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/pm.h |1 +
arch/arm/mach-omap2/pm44xx.c | 36
[1].
[1]: git://gitorious.org/runtime_3-0/runtime_3-0.git v6_uart_runtime
Rajendra Nayak (1):
OMAP4 PM: Add IO Daisychain support
Vishwanath BS (3):
OMAP3 PM: Fix IO Daisychain sequence
OMAP3 PM: Enable IO Wake up
OMAP3PLUS PM: Add IO Daisychain support via hwmod mux
arch/arm/mach-omap2
Datamanual]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
Patch is generated against latest lo master.
Changes in V2: Updated the commit log as per Nishant's comments.
Patch has some checkpatch warnings related to line over 80 chars. They have
been
From: Keerthy j-keer...@ti.com
Patch adds hwmod entry for 4460 thermal sensor module. Thermal sensor module
is part of Control module sharing its address space and clocked via Bandgap
Functional Clock. Adding a seperate hwmod entry for thermal sensor will
enable thermal sensor driver to manage
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
Patch is generated against Patch series [PATCH v2 0/6] OMAP4: Add 4460 base
support from Rajendra and boot tested on 4460 and 4430 SDP.
Changes in V2: Updated the commit log as per Nishant's comments
arch/arm/mach-omap2/control.h
Rajendra.
[n...@ti.com: cleanups and updates from Datamanual]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/control.h |1 +
arch/arm/mach-omap2/omap_opp_data.h |9 ++-
arch/arm/mach-omap2
) and tested on OMAP ZOOM3
and OMAP4430 SDP with Smartreflex enabled.
Vishwanath BS (3):
OMAP PM: Seggregate Voltage layer parameters
OMAP PM: Add support for bypassing VP/VC in Voltage layer
OMAP PM: Add Board specific parameters for OMAP Volatge layer
arch/arm/mach-omap2/board-4430sdp.c
Currently Voltage layer assumes that all PMICs use VP/VC for Voltage scaling.
There can be some instances where PMIC would want to bypass VP/VC for voltage
scaling. So make VOltage layer flexible enough to handle this.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2
with different kinds of PMIC
and boards.
TODO: Provide infrastructure to use VC I2C (I2C4) for PMIC configuration (useful
for cases where PMIC is connected to OMAP only via I2C4.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/omap_opp_data.h |8 ++
arch/arm
This patch adds board specific parameters for ZOOM3 and OMAP4430 SDP Boards.
The same needs to be done for other OMAP3 and OMAP4 boards once the approach
is accepted.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/board-4430sdp.c | 52 +++
arch
This patch series has some fixes/optimization for OMAP3 cpuidle code.
Tested on ZOOM3 for cpuidle and suspend/resume with OFF mode enabled.
Patches are rebased to latest kevin's pm branch
(commit id: b6fb54bc4bfc396a9b982d76c1c954c974290a1a)
Vishwanath BS (3):
OMAP3 PM: Deny clock gating only
will be
initialized at omap_init_power_states. So update_states will operated only on
enabled C states.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 29 +++--
1 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/arch/arm
inactive
* C5 . MPU CSWR + Core CSWR
* C7 . MPU OFF + Core OFF
Thanks to Nicole Chaloubn-chalh...@ti.com and Vincent Bour v-b...@ti.com
for their investigation.
Tested on ZOOM3 board using latest pm branch.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/board-3630sdp.c
Currently clock gating for MPU and core are denied whenever C1 state is
selected. It should be denied only when safe state is selected.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 20 ++--
1 files changed, 10 insertions(+), 10
options in defconfig
Vishwanath BS (7):
OMAP: Introduce accessory APIs for DVFS
OMAP: Implement Basic DVFS
OMAP: Introduce dependent voltage domain support
OMAP: Introduce device scale implementation
OMAP3: cpufreq driver changes for DVFS support
OMAP2PLUS: Replace voltage values
and basic data structures are allocated and
initialized as part of this.
This patch is based on Thara's previous DVFS implementation, but with major
rework.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/Makefile |2 +-
arch/arm
some routine error
checks and finally calls into the device specific set_rate
and get_rate APIs populated through omap_device_populate_rate_fns.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/plat-omap/include/plat/omap_device.h |9
From: Thara Gopinath th...@ti.com
This patch disables smartreflex for a particular voltage
domain when the the voltage domain and the devices belonging
to it is being scaled and re-enables it back once the scaling
is done.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Vishwanath BS
patch from Thara.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/dvfs.c | 87 +++-
1 files changed, 86 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/dvfs.c b/arch/arm/mach-omap2
This patch adds omap_device_scale API which can be used to generic
device rate scaling.
Based on original patch from Thara.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/dvfs.c | 116
arch
From: Thara Gopinath th...@ti.com
In OMAP3, for perfomrance reasons when VDD1 is at voltage above
1.075V, VDD2 should be at 1.15V for perfomrance reasons. This
patch introduce this cross VDD dependency for OMAP3 VDD1.
Signed-off-by: Thara Gopinath th...@ti.com
This patch has checkpatch warnings
Currently voltage values on opp tables are hardcoded. As these voltage values
are anyway defined in voltage.h as macros, opp table can reuse these values.
This will avoid opp table and voltage layer having conflicting values.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
This patch has 2 line
From: Thara Gopinath th...@ti.com
This patch enables Smartreflex and Cpu Freq in the
omap2plus defconfig.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/configs/omap2plus_defconfig |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git
From: Thara Gopinath th...@ti.com
This patch also introduces omap3_mpu_set_rate, omap3_iva_set_rate,
omap3_l3_set_rate, omap3_mpu_get_rate, omap3_iva_get_rate,
omap3_l3_get_rate as device specific set rate and get rate
APIs for OMAP3 mpu, iva and l3_main devices. This patch also
calls into
to voltage.h as it needs to be used in the dvfs layer for dependency
voltage handling.
Based on original patch from Thara.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/dvfs.c| 87 +
arch/arm/mach-omap2/voltage.c
From: Thara Gopinath th...@ti.com
This patch adds voltage domain info in the relevant
device hwmod structures so as to enable OMAP3 DVFS
support.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |3 +++
1 files changed, 3 insertions(+), 0
Changes in the omap cpufreq driver for DVFS support.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/plat-omap/cpu-omap.c | 35 ---
1 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/plat-omap/cpu-omap.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
mode change 100644 = 100755 arch/arm/plat-omap/cpu-omap.c
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
old mode 100644
new
mpu/dma latency request.
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
The changes are rebased to latest kevin's origin/pm branch and tested
on OMAP ZOOM3.
---
V2: aligned the implementation with latest PM QOS APIs
This patch adds comments on precatution to be taken if Global Warm reset is
used as the means to trigger sysem reset.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/prcm.c | 28
1 files changed, 28
This patch adds comments on precatution to be taken if Global SW reset is
used as the means to trigger sysem reset.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/prcm.c | 26 ++
1 files changed, 26 insertions
This patch adds comments on precatution to be taken if Global Warm reset is
used as the means to trigger sysem reset.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/prcm.c | 28
1 files changed, 28
This patch has done some clean up of omap3 sleep code.
Basically all possible hardcodings are removed and code is Reorganized
into more logical buckets for better readability and instrumentation.
Tested on ZOOM3.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Kevin Hillman khil
This patch series has some clean up in OMAP3 sleep code.
Patches have been rebased to latest kevin's pm branch.
Vishwanath BS (2):
OMAP3 PM: move omap3 sleep to ddr
OMAP3 PM: sleep code clean up
arch/arm/mach-omap2/pm34xx.c |9 +-
arch/arm/mach-omap2/sleep34xx.S
. With these changes, gain is
in power consumption is observed on some use cases.
Thanks to Nicole Chaloubn-chalh...@ti.com and Vincent Bour v-b...@ti.com
for their investigation.
Tested on ZOOM3 board using latest pm branch.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Signed-off-by: Nicole Chalhoub
system suspend as
pm_runtime_set_suspended is not called from i2c_device_pm_suspend.
This issue is fixed by removing pm_runtime_set_active call from resume path
which
is not necessary.
This fix has been tested on OMAP4430.
Signed-off-by: Partha Basak p-bas...@ti.com
Signed-off-by: Vishwanath BS
tested on OMAP4430.
Signed-off-by: Partha Basak p-bas...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Rafael J. Wysocki r...@sisk.pl
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Ben Dooks ben-li...@fluff.org
---
drivers/i2c/i2c-core.c | 12 ++--
1 files changed, 10
on top of i581 errata WA available@
https://patchwork.kernel.org/patch/102673/
Tested on OMAP3630 ZOOM3.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b0a5d09..5b48b6c
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch
From: Vishwanath BS vishwanath...@ti.com
OMAP3430/3630 has a Silicon bug because of which SDRC is
released from IDLE even before Core DPLL has locked. This leads
to undefined behaviour of SDRC DLL.
Bug Descritpion: The root cause of the issue is that SDRC IDLEREQ
is deasserted before DPLL3 has
.
Signed-off-by: Teerth Reddy tee...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 9537f6f..ac731b2
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -27,6 +27,7 @@
#include plat/prcm.h
OMAP3430/3630 has a Silicon bug because of which SDRC is released from
IDLE even before Core DPLL has locked. This leads to undefined behaviour
of SDRC DLL. This patch has workaround for the same.
Description of WA for 3430:
Initialization:
Disable DPLL3 automatic mode by default. Issue
opp_find_freq_floor should return the lower enabled* OPP from a starting freq
from a start opp list. But current code returns next lower opp. This patch fixes
this issue.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
diff --git a/arch/arm/plat-omap/opp.c b/arch/arm/plat-omap/opp.c
index
It is found that system is not very stable with current 1GHz OPP configuration
(a...@1g, i...@880m, v...@1.31v) and it has been recommended to
use below configuration for stable 1GHz OPP.
(a...@1g, i...@800m, v...@1.35v).
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
diff --git a/arch
frequency for the specific OPP.
Typically these settings are to be done in bootloaders.
All the patches have been tested on OMAP3630 ZOOM3 platform.
Comments adressed in V3:
1. Used clk_set_rate API instead of directly writing to registers
2. Split the patch into 2 patches.
Vishwanath BS (4
frequency for the specific OPP.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock3xxx_data.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index d5153b6
Whenever VDD1 OPP is changed, MPU and Bypass clock dividers should be
adjusted such that MPU/IVA is never overclocked when DPLL1/DPLL2 is in
bypass mode
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/resource34xx.c | 18 --
1 files changed, 16
is always less than
maximum supported frequency for the specific OPP
Tested on 3630 ZOOM3.
changes in V2 : Rebased to new OPP implementation
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/cm-regbits-34xx.h |4
Vishwanath BS (3):
OMAP3: Introduce 3630 DPLL4 HSDivider changes
OMAP3: add support for 192Mhz DPLL4M2 output
arch/arm/mach-omap2/clock.h |4 +
arch/arm/mach-omap2/clock34xx_data.c| 240 ---
arch/arm/mach-omap2/clock44xx_data.c|1 +
arch
.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx_data.c| 140 +--
arch/arm/mach-omap2/cm-regbits-34xx.h |5 +
arch/arm/plat-omap/include/plat/clock.h |5 +-
3 files changed, 141 insertions(+), 9 deletions(-)
diff --git
changes done are 1. Added a feature called
omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node
called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive it's
clock from omap_192m_alwon_ck
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch
.
Tested with 3630 ZOOM3 and OMAP3430 ZOOM2
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Richard Woodruff r-woodru...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock.h |4 ++
arch/arm/mach-omap2
in V5:
1. Comments from Eduardo Valentin, cosmetic changes and splitting of the patch
for freqsel changes
2. Comments from Paul regarding updation of Clock nodes
Comments Addressed in V6:
1. Cosmetic changes based on Comments from Alex and Paul
Vishwanath BS (4):
OMAP3: introduce DPLL4 Jtype
DPLL_FREQSEL field in CLKEN_PLL register is no longer valid for
OMAP3630. So remove
references to that.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/dpll3xxx.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2
is 3630.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx_data.c| 140 +--
arch/arm/mach-omap2/cm-regbits-34xx.h |8 ++-
arch/arm/plat-omap/include/plat/clock.h |5 +-
3 files changed, 143 insertions(+), 10 deletions
changes done are 1. Added a feature called
omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node
called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive it's
clock from omap_192m_alwon_ck
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Richard Woodruff r-woodru...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock.h |4 ++
arch/arm/mach-omap2/clock34xx_data.c| 32
in V5:
1. Comments from Eduardo Valentin, cosmetic changes and splitting of the patch
for freqsel changes
2. Comments from Paul regarding updation of Clock nodes
Comments Addressed in V6:
1. Cosmetic changes based on Comments from Alex and Paul
Vishwanath BS (4):
OMAP3: introduce DPLL4 Jtype
DPLL_FREQSEL field in CLKEN_PLL register is no longer valid for OMAP3630. So
remove
references to that.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/dpll.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/dpll.c b
updation of Clock nodes
Vishwanath BS (4):
OMAP3: introduce DPLL4 Jtype
OMAP3: Remove FreqSel for 3630
OMAP3: Introduce 3630 DPLL4 HSDivider changes
OMAP3: add support for 192Mhz DPLL4M2 output
arch/arm/mach-omap2/clock.h |4 +
arch/arm/mach-omap2/clock34xx_data.c
changes done are 1. Added a feature called
omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node
called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive it's
clock from omap_192m_alwon_ck
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch
is 3630.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx_data.c| 140 +--
arch/arm/mach-omap2/cm-regbits-34xx.h |8 ++-
arch/arm/plat-omap/include/plat/clock.h |5 +-
3 files changed, 143 insertions(+), 10 deletions
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Richard Woodruff r-woodru...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock.h |4 ++
arch/arm/mach-omap2/clock34xx_data.c| 32
power
savings in MP3 usecase (where Core enters retention where as PER does not).
Tested OMAP3430 ZOOM2
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3868cdf..13c5dfb
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b
in V4:
1. Remove sd_div_mask and dco_sel_mask
2. Remove reference to FREQSEL for 3630
3. Avoid dynamically overwriting Fields in Clock nodes
Vishwanath BS (4):
introduce DPLL4 Jtype
Remove FreqSel for 3630
Introduce 3630 DPLL4 HSDivider changes
add support for 192Mhz DPLL4M2 output
arch
Frequency Selection field is no longer valid for OMAP3630. So remove
references to that.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/dpll.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach
type is 3630.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx_data.c| 125 ++-
arch/arm/mach-omap2/cm-regbits-34xx.h |8 ++-
arch/arm/plat-omap/include/plat/clock.h |1 +
3 files changed, 132 insertions(+), 2 deletions
changes done are
1. Added a feature called omap3_has_192mhz_clk and enabled for 3630
2. Added a new clock node called omap_192m_alwon_ck
3. Made omap_96m_alwon_fck to derive it's clock from omap_192m_alwon_ck
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Richard Woodruff r-woodru...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock.h |4 ++
arch/arm/mach-omap2/clock34xx_data.c| 26
sd_div_mask and dco_sel_mask
2. Remove reference to FREQSEL for 3630
3. Avoid dynamically overwriting Fields in Clock nodes
Vishwanath BS (3):
OMAP3: introduce DPLL4 Jtype
OMAP3: Correct width for CLKSEL Fields
OMAP3: add support for 192Mhz DPLL4M2 output
arch/arm/mach-omap2/clock.h
DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
3630. This patch has changes to accommodate this in CM dynamically based
on chip version.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx_data.c| 153
On 3630, DPLL4M2 o/p can be 96MH or 192MHz (for SGX to run at 192). This
patch has changes to support this feature.
96MHz clock is generated by dividing 192Mhz clock by 2 using
CM_CLKSEL_CORE register.
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch
to this is removed for 3630.
Tested with 3630 ZOOM3 and OMAP3430 ZOOM2
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Richard Woodruff r-woodru...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock.h |3 ++
arch/arm
-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/cm-regbits-34xx.h |4 ++--
arch/arm/mach-omap2/pm34xx.c | 19 +++
arch/arm/mach-omap2/resource34xx.c| 20
3 files changed, 41 insertions(+), 2 deletions(-)
mode change 100644
Series
V2: Fixed Line wrap issue and incorporated comments for adding 192MHz Feature
Richard Woodruff (1):
OMAP3: introduce DPLL4 Jtype
Vishwanath BS (3):
OMAP3: Clock Type change for OMAP3 Clocks
OMAP3: Correct width for CLKSEL Fields
OMAP3: add support for 192Mhz sgx clock
arch/arm
under CK_363X
3. Clock nodes which have changes for 3630 are marked as CK_3XXX | CK_363X
4. Clock nodes which are unchanged for 3630 are retained as CK_3XXX
5. 3630 specific Clock rates are marked as RATE_IN_363X
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
In omap34xx_clks, CK_343X type is used by all OMAP3 family of
processors. It makes more sense to name clock type as CK_3XXX since it
is common to all OMAP3 processors.
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock.h
Walmsley p...@pwsan.com
Signed-off-by: Richard Woodruff r-woodru...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx.c | 51 ++-
arch/arm/mach-omap2/cm-regbits-34xx.h |6
Series
V2: Fixed Line wrap issue and incorporated comments for adding 192MHz Feature
Richard Woodruff (1):
OMAP3: introduce DPLL4 Jtype
Vishwanath BS (3):
OMAP3: Clock Type change for OMAP3 Clocks
OMAP3: Correct width for CLKSEL Fields
OMAP3: add support for 192Mhz sgx clock
arch/arm
-by: Richard Woodruff r-woodru...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx.c | 51 ++-
arch/arm/mach-omap2/cm-regbits-34xx.h |6 +++-
arch/arm/mach-omap2/id.c
DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
3630.This patch has changes to accommodate this in CM dynamically based on
chip version.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx.c | 18 --
arch/arm/mach-omap2
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