Add missing OMAP keypad reg property information.
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 45 +++---
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c2c798c..4501038
From: Lokesh Vutla lokeshvu...@ti.com
Add watchdog timer dt node for OMAP5 devices.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm
() them in early init code.
So this patch makes prevet calling the _init_mpu_rt_base() conditional
based on sysc availability.
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |3 ++-
1 file changed, 2 insertions
Add l3-noc node for OMAP4 and OMAP5 devices.
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |5 +
arch/arm/boot/dts/omap5.dtsi |5 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts
On Wednesday 20 March 2013 10:13 AM, Andy Gross wrote:
Remove DMM device creation via the hwmod entry. The DMM device will
now be enumerated as part of the device tree information for the
processor.
Signed-off-by: Andy Gross andy.gr...@ti.com
---
OMAP4 is still not made DT only so I
On Wednesday 20 March 2013 10:13 AM, Andy Gross wrote:
Add DMM bindings for OMAP4 and OMAP5 devices.
Signed-off-by: Andy Gross andy.gr...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |7 +++
arch/arm/boot/dts/omap5.dtsi |7 +++
2 files changed, 14 insertions(+), 0 deletions(-)
On Friday 15 March 2013 10:30 AM, Will Deacon wrote:
On Thu, Mar 14, 2013 at 01:08:00PM +0530, Santosh Shilimkar wrote:
Will,
Hi guys,
I'm out of the office at the moment and have really terrible connectivity,
so I can't do too much until next week. However, I don't think adding
On Monday 18 March 2013 08:37 PM, Will Deacon wrote:
Hi Santosh,
On Mon, Mar 18, 2013 at 06:51:30AM +, Santosh Shilimkar wrote:
On Friday 15 March 2013 10:30 AM, Will Deacon wrote:
Furthermore, I was under the impression that hw_breakpoint did actually
work on panda, which implies
On Wednesday 20 February 2013 08:57 PM, Santosh Shilimkar wrote:
From: Rajendra Nayak rna...@ti.com
OMAP5 does not have freqsel either, so add the missing
checks for !soc_is_omap54xx()
Reported-by: Archit Taneja arc...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm
Benoit,
On Wednesday 20 February 2013 09:08 PM, Santosh Shilimkar wrote:
Few updates for OMAP5 found during testing OMAP5 DT builds. Couple
of patches were already posted on the list. The series also contains
a patch which adds DMA request, IRQ lines and IO address space
DT extraction
On Friday 15 March 2013 06:15 PM, Benoit Cousson wrote:
Hi Santosh,
On 03/15/2013 11:24 AM, Santosh Shilimkar wrote:
Benoit,
On Wednesday 20 February 2013 09:08 PM, Santosh Shilimkar wrote:
Few updates for OMAP5 found during testing OMAP5 DT builds. Couple
of patches were already posted
On Wednesday 13 March 2013 11:12 PM, Kevin Hilman wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
Kevin,
On Wednesday 13 February 2013 02:25 PM, Santosh Shilimkar wrote:
Current CPU PM code code make use of common cpu_suspend() path for all the
CPU power states which
On Thursday 14 March 2013 12:01 AM, Thomas Gleixner wrote:
On Wed, 13 Mar 2013, Santosh Shilimkar wrote:
On Wednesday 13 March 2013 07:49 PM, Thomas Gleixner wrote:
Though making the rating of the dummy lower is definitely a good
thing, so a real hardware device which is detected later can
On Wednesday 13 March 2013 10:16 PM, Benoit Cousson wrote:
Hi Sourav,
I've just applied your branch after a minor subject cleanup for consistency.
git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
for_3.10/dts
Thanks for the tree Benoit. I shall update my v2 DT
just warn once rather
than continuous warnings in the notifier. Patch is end of the
email.
Regards,
Santosh
From b8db63f786719aef835f1ef4e20f3b3406b99b62 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar santosh.shilim...@ti.com
Date: Thu, 14 Mar 2013 13:03:25 +0530
Subject: [PATCH] ARM
(Looping Greg KH.)
Greg,
On Wednesday 20 February 2013 09:14 PM, Santosh Shilimkar wrote:
On Wednesday 20 February 2013 08:54 PM, Kevin Hilman wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
UART IP slave idle handling now taken care by runtime pm backend(hwmod
layer)
so remove
On Thursday 14 March 2013 04:59 PM, Hiremath, Vaibhav wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Paul Walmsley
Sent: Tuesday, March 12, 2013 10:10 PM
To: linux-omap@vger.kernel.org
Cc:
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Its a regression so hopefully can get into the 3.9-rcx. Noticed
this one on A15 platform. A9 platform the issue may not be seen
since the local timer check avoids dummy timer registration.
arch/arm/kernel/smp.c |2 +-
1 file changed, 1
(Forgot to CC Thomas)
On Wednesday 13 March 2013 02:36 PM, Santosh Shilimkar wrote:
With recent arm broadcast time clean-up from Mark Rutland, the dummy
broadcast device is always registered with timer subsystem. And since
the rating of the dummy clock event is very high, it is preferred
over
On Wednesday 13 March 2013 03:46 PM, Mark Rutland wrote:
Hi Santosh,
On Wed, Mar 13, 2013 at 09:28:22AM +, Santosh Shilimkar wrote:
(Forgot to CC Thomas)
On Wednesday 13 March 2013 02:36 PM, Santosh Shilimkar wrote:
With recent arm broadcast time clean-up from Mark Rutland, the dummy
On Wednesday 13 March 2013 07:49 PM, Thomas Gleixner wrote:
On Wed, 13 Mar 2013, Santosh Shilimkar wrote:
On Wednesday 13 March 2013 02:36 PM, Santosh Shilimkar wrote:
With recent arm broadcast time clean-up from Mark Rutland, the dummy
broadcast device is always registered with timer
On Wednesday 13 March 2013 05:55 PM, Mark Rutland wrote:
On Wed, Mar 13, 2013 at 11:24:01AM +, Santosh Shilimkar wrote:
On Wednesday 13 March 2013 03:46 PM, Mark Rutland wrote:
Hi Santosh,
[..]
Is the problem that the dummy timer is being registered as the broadcast
source
to link up using device tree, instead
of platform device, provide compatibility string match:
compatible = cpufreq,cpu0;
Cc: Rafael J. Wysocki r...@sisk.pl
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Shawn Guo shawn@linaro.org
Cc: linux-ker...@vger.kernel.org
Cc: cpuf
On Tuesday 12 March 2013 07:58 PM, Benoit Cousson wrote:
On 03/12/2013 06:07 AM, Santosh Shilimkar wrote:
On Tuesday 12 March 2013 04:35 AM, Nishanth Menon wrote:
commit 5553f9e (cpufreq: instantiate cpufreq-cpu0 as a platform_driver)
now forces platform device to be registered for allowing
Kevin,
On Wednesday 13 February 2013 02:25 PM, Santosh Shilimkar wrote:
Current CPU PM code code make use of common cpu_suspend() path for all the
CPU power states which is not optimal. In fact cpu_suspend() path is needed
only when we put CPU power domain to off state where the CPU context
for clk names to be provided as string so as to be used when needed.
Example (for OMAP3630):
cpus {
cpu@0 {
clock-name = cpufreq_ck;
};
};
Cc: Rafael J. Wysocki r...@sisk.pl
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Shawn Guo shawn@linaro.org
Cc: linux-ker
On Monday 04 March 2013 11:59 PM, Nishanth Menon wrote:
On 11:17-20130302, Santosh Shilimkar wrote:
On Saturday 02 March 2013 01:07 AM, Nishanth Menon wrote:
On 17:40-20130301, Santosh Shilimkar wrote:
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register
as well as add a
comment about the calculation in the code.
Otherwise, patch looks fine to me.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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in at init time.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Ambresh K ambr...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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lokeshvu...@ti.com
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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).
Make sense.
Reported-by: Richard Woodruff r-woodru...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Thanks for the fix.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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();
+ } else {
+ WARN(1, FIXME: NO pm_power_off!!! trying restart\n);
+ kernel_restart(SDRAM Over-temp Emergency restart);
+ }
return IRQ_HANDLED;
}
Otherwise,
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
, size);
pd-timings = temp;
} else {
dev_warn(dev, %s:%d: allocation error\n, __func__,
Patch as such looks good to me.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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-by: Santosh Shilimkar santosh.shilim...@ti.com
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endian format.
Correcting the same here.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Looks fine.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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More
and OMAP5432 Panda
devices with suspend and CPUIdle. On OMAP5 DT build though, there is an
issue with UART wakeup from suspend as discussed already on lists.
Nishanth Menon (1):
ARM: OMAP5: PM: handle device instance for for coldreset
Santosh Shilimkar (14):
ARM: OMAP4+: PM: Consolidate MPU subsystem PM
OMAP5 and future OMAP based SOCs has backward compatible MPUSS
IP block with OMAP4. It's programming model is mostly similar.
Hence consolidate the OMAP MPUSS code so that it can be re-used
on OMAP5 and future SOCs.
No functional change.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
clock-domain to avoid issues.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/pm_omap4plus.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm_omap4plus.c
b/arch/arm/mach-omap2
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git
.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap-secure.h|2 ++
arch/arm/mach-omap2/omap-wakeupgen.c | 14 ++
arch/arm/mach-omap2/omap-wakeupgen.h |1 +
3 files changed, 17 insertions(+)
diff --git a/arch/arm/mach-omap2/omap-secure.h
b
In addition to the standard power-management technique, the OMAP5
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU.
Signed-off-by: Santosh
devices first.
So update the code accordingly.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/cpuidle44xx.c |1 +
arch/arm/mach-omap2/omap-smp.c| 12 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2
In MPUSS OSWR(Open Switch Retention), entire CPU cluster is powered down
except L2 cache memory. For MPUSS OSWR state, both CPU's needs to be in
power off state.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c |2 ++
arch/arm/mach-omap2
/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -1,7 +1,7 @@
/*
- * OMAP4 CPU idle Routines
+ * OMAP4PLUS CPU idle Routines
*
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011-2013 Texas Instruments, Inc.
* Santosh Shilimkar santosh.shilim...@ti.com
* Rajendra Nayak
With consolidated code, now we can add the .init_late hook for
OMAP5 to enable power management and mux initialization.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/board-generic.c |1 +
arch/arm/mach-omap2/common.h|3 ++-
arch/arm/mach-omap2
Add power management code to handle the CPU off mode. Separate
suspend finisher is used for OMAP5(Cortex-A15) because it doesn't
use SCU power status register and external PL310 L2 cache which makes
code flow bit different.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm
When the entire MPUSS cluster is powered down in device off state, L2 cache
memory looses it's content and hence while targetting such a state,
l2 cache needs to be flushed to main memory.
Add the necessary low power code support for the same.
Signed-off-by: Santosh Shilimkar santosh.shilim
- CPU0 ON(WFI) + CPU1 ON(WFI) + MPUSS ON
C2 - CPU0 CSWR + CPU1 CSWR + MPUSS CSWR
C3 - CPU0 OFF + CPU1 Force OFF + MPUSS OSWR
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Kconfig|1 +
arch/arm/mach-omap2/Makefile
will be replicated without much benefit.
Signed-off-by: Nishanth Menon n...@ti.com
santosh.shilim...@ti.com: Refreshed patch against 3.8
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/prminst44xx.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git
with platform code for idle driver movement.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/common.h |5 -
arch/arm/mach-omap2/cpuidle44xx.c |3 ++-
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 14 --
3 files changed, 2
power management code build
and initialise on OMAP5 devices.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Makefile |9 +-
arch/arm/mach-omap2/{pm44xx.c = pm_omap4plus.c} | 87 +---
.../mach-omap2/{sleep44xx.S
On Friday 01 March 2013 06:34 PM, Nishanth Menon wrote:
$subject - warm reset
ok
On 17:41-20130301, Santosh Shilimkar wrote:
From: Nishanth Menon n...@ti.com
OMAP5 and OMAP4 have different device instance offsets.
So to handle them properly, use a runtime detected instance offset
Other
On Friday 01 March 2013 06:43 PM, Nishanth Menon wrote:
On 18:39-20130301, Santosh Shilimkar wrote:
On Friday 01 March 2013 06:34 PM, Nishanth Menon wrote:
$subject - warm reset
ok
On 17:41-20130301, Santosh Shilimkar wrote:
From: Nishanth Menon n...@ti.com
OMAP5 and OMAP4 have different
-hun...@ti.com
---
Cool.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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will fail. To prevent such hangs, test for
this case and warn if this is detected.
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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On Friday 01 March 2013 11:13 PM, Nishanth Menon wrote:
On 17:40-20130301, Santosh Shilimkar wrote:
diff --git a/arch/arm/mach-omap2/pm44xx.c
b/arch/arm/mach-omap2/pm_omap4plus.c
similarity index 74%
rename from arch/arm/mach-omap2/pm44xx.c
rename to arch/arm/mach-omap2/pm_omap4plus.c
On Saturday 02 March 2013 01:07 AM, Nishanth Menon wrote:
On 17:40-20130301, Santosh Shilimkar wrote:
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: ES1 behavior, CPU cores would enter and exit OFF mode together. Broken
0x1: ES2 behavior, CPU cores
On Saturday 02 March 2013 01:12 AM, Nishanth Menon wrote:
On 17:40-20130301, Santosh Shilimkar wrote:
In addition to the standard power-management technique, the OMAP5
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
Mercury fast is employed here
On Saturday 02 March 2013 01:42 AM, Nishanth Menon wrote:
On 17:40-20130301, Santosh Shilimkar wrote:
With consolidated code, now we can add the .init_late hook for
OMAP5 to enable power management and mux initialization.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch
On Saturday 02 March 2013 03:06 AM, Nishanth Menon wrote:
On 17:40-20130301, Santosh Shilimkar wrote:
Add power management code to handle the CPU off mode. Separate
suspend finisher is used for OMAP5(Cortex-A15) because it doesn't
use SCU power status register and external PL310 L2 cache which
On Saturday 02 March 2013 03:23 AM, Nishanth Menon wrote:
On 17:40-20130301, Santosh Shilimkar wrote:
While waking up CPU from off state using clock domain force wakeup, restore
the CPU power state to ON state before putting CPU clock domain under
hardware control. Otherwise CPU wakeup might
On Saturday 02 March 2013 05:13 AM, Nishanth Menon wrote:
On 17:41-20130301, Santosh Shilimkar wrote:
When the entire MPUSS cluster is powered down in device off state, L2 cache
memory looses it's content and hence while targetting such a state,
l2 cache needs to be flushed to main memory
On Saturday 02 March 2013 05:26 AM, Nishanth Menon wrote:
On 17:41-20130301, Santosh Shilimkar wrote:
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
b/arch/arm/mach-omap2/cpuidle44xx.c
index 9de47a7..df81243 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2
On Saturday 02 March 2013 05:55 AM, Nishanth Menon wrote:
On 17:41-20130301, Santosh Shilimkar wrote:
The OMAP5 idle driver can re-use OMAP4 CPUidle driver implementation thanks
to compatible MPUSS design.
Though unlike OMAP4, on OMAP5 devices, MPUSS CSWR (Close Switch Retention)
power
On Monday 25 February 2013 04:26 PM, Benoit Cousson wrote:
Hi Santosh,
On 02/20/2013 04:38 PM, Santosh Shilimkar wrote:
Patch adds the OCP address space for all missing hwmod from existing
DT file. Note that the compatible isn't added by purpose to ensure that for
these hwmod, devices
-by: Sourav Poddar sourav.pod...@ti.com
Tested-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Posting this one seperatly but will add along with rest of
my fixes so that it doesn't get lost on the list.
arch/arm/mach-omap2/omap4-common.c | 32
On Monday 25 February 2013 08:32 PM, Jon Hunter wrote:
On 02/25/2013 06:09 AM, Santosh Shilimkar wrote:
OMAP4460 ROM code bug needs the GIC distributor and local timer
bases to be available for the bug work around. In current code, dt
case these bases are not initialized leading to failure
On Thursday 21 February 2013 06:22 PM, Sergei Shtylyov wrote:
Hello.
On 20-02-2013 19:27, Santosh Shilimkar wrote:
OMAP5 clockdata has different sys clock clock node name. Fix the timer
code
One clock too many. :-)
Indeed. Will fix that.
Regards
Santosh
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On Thursday 21 February 2013 06:25 PM, Sergei Shtylyov wrote:
Hello.
On 20-02-2013 19:18, Santosh Shilimkar wrote:
The smp_wmb() here is out of placed
s/placed/place/
and redundant. So remove it. It is
a left over of the pain_release
Sure it's not 'pen_release'?
cleanup mostly
OCP_SYSCONFIG.ENAWAKEUP enabled
ARM: OMAP2+: hwmod: Add a new flag to handle SIDLE in SWSUP only in
active
Santosh Shilimkar (4):
ARM: OMAP2+: hwmod-data: UART IP needs software control to manage
sidle modes
SERIAL: OMAP: Remove the slave idle handling from the driver
ARM: OMAP2+: serial: Remove
From: Rajendra Nayak rna...@ti.com
_HWMOD_WAKEUP_ENABLED is currently unused across the hwmod
framework. Just get rid of it, so we have one less flag to
worry about.
Tested-by: Vaibhav Bedia vaibhav.be...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar
Poddar sourav.pod...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 48 ++
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-omap2
/SMART_WKUP modes
of sidle/mstandby the framework anyway sets this always.
Tested-by: Vaibhav Bedia vaibhav.be...@ti.com
Tested-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2
sourav.pod...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |3 ++-
arch/arm/mach-omap2/omap_hwmod.h |4
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2
.
Subsequent patches removes the slave idle handling from driver code.
Tested-by: Vaibhav Bedia vaibhav.be...@ti.com
Tested-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2
UART IP slave idle handling now taken care by runtime pm backend(hwmod layer)
so remove the hackery from the driver.
Tested-by: Vaibhav Bedia vaibhav.be...@ti.com
Tested-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Rajendra nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar
-by: Rajendra nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/serial.c | 31 ---
1 file changed, 31 deletions(-)
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 04fdbc4..037e691 100644
-off-by: Rajendra nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 68 --
arch/arm/mach-omap2/omap_hwmod.h |3 --
2 files changed, 71 deletions(-)
diff --git a/arch/arm/mach-omap2
+ Felipe ( Sorry I missed you in CC list)
On Wednesday 20 February 2013 03:27 PM, Santosh Shilimkar wrote:
OMAP UART IP needs manual idle modes based on functional state of the
IP. Currently this is handled by the driver with function pointers
implemented in platform code.
This however breaks
On Wednesday 20 February 2013 03:44 PM, Russell King - ARM Linux wrote:
On Wed, Feb 20, 2013 at 03:27:44PM +0530, Santosh Shilimkar wrote:
OMAP UART IP needs manual idle modes based on functional state of the
IP. Currently this is handled by the driver with function pointers
implemented
On Wednesday 20 February 2013 05:21 PM, Russell King - ARM Linux wrote:
On Wed, Feb 20, 2013 at 03:53:22PM +0530, Santosh Shilimkar wrote:
Actually the clean-up will remove the serial driver dependency with
idle handling. Infact DMA support need not care about idle handling
anymore.
How
and OMAP3 devices for boot, suspend and
CPUIDLE. OMAP1 patch isn't tested but I don't expect it to cause any
breakage since it is just cleaning up the bogus fiq use.
Santosh Shilimkar (8):
ARM: OMAP1: PM: Remove bogus fiq_[enable/disable] tuple
ARM: OMAP2+: PM: Remove bogus fiq_[enable/disable
From: Tero Kristo t-kri...@ti.com
Simplifies code and also allows the re-use as is on OMAP5 devices.
Signed-off-by: Tero Kristo t-kri...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap4-sar-layout.h | 14 +++---
1 file changed, 7
On OMAP platform, FIQ is reserved for secure environment only. If at all
the FIQ needs to be disabled, it involves going through security
API call. Hence the local_fiq_[enable/disable]() in the OMAP code is bogus.
So just get rid of it.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
This was added with intial port where OMAP PM support wasn't existing
and only simple WFI based hooks were used.
This should have been cleaned up while adding the PM support but some
how fall through cracks.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap
The smp_wmb() here is out of placed and redundant. So remove it. It is
a left over of the pain_release cleanup mostly.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap-smp.c |2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/pm44xx.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 1fd9662..1d03110 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch
On OMAP platform, FIQ is reserved for secure environment only. If at all
the FIQ needs to be disabled, it involves going through security
API call. Hence the local_fiq_[enable/disable]() in the OMAP code is bogus.
So just get rid of it.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
perspective, it isn't an ideal workaround.
Cc: Jon Hunter jon-hun...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/pm44xx.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm
Move the secondary CPU wakeup prepare code under smp_prepare_cpus(). While at
it drop the un-necessary sev() and barrier which was under prepare code.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap-smp.c | 51
1
This was borrowed from ARM versatile code with pen_release mechanism but since
OMAP uses hardware register based synchronisation, pen_release stuff was
dropped. Unfortunately the cacheflush wasn't dropped along with it.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach
Here are few OMAP5 updates discovered during es2.0 silicon validation.
Tested on OMAP5430 and OMAP5432 devices after applying out of tree
datafiles for OMAP5.
Rajendra Nayak (1):
ARM: OMAP5: clock: No Freqsel on OMAP5 devices
Santosh Shilimkar (6):
ARM: OMAP5: Update SOC id detection code
Update OMAP5 ES2 idcode and make ES2 as default detection.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/id.c | 16 +---
arch/arm/mach-omap2/soc.h |2 ++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2
OMAP5 clockdata has different sys clock clock node name. Fix the timer code
to take care of it.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/timer.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch
From: Tero Kristo t-kri...@ti.com
Make use of 'prm_base' so that prm read_inst/write_inst can work on
OMAP5 devices.
Signed-off-by: Tero Kristo t-kri...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/prm44xx.c |4 ++--
1 file changed, 2 insertions
Update SAR RAM base address for OMAP5 based devices.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap4-common.c | 10 --
arch/arm/mach-omap2/omap54xx.h |1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2
On OMAP5 es2 WakeupGen SAR register layout offset have changed.
Update the layout accordingly.
Reported-by: Menon, Nishanth n...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap4-sar-layout.h | 14 +++---
1 file changed, 7 insertions(+), 7
Errata i688 is also applicable for OMAP5 based devices. Update the
code so that it can be enabled on OMAP5 devices.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Kconfig |2 +-
arch/arm/mach-omap2/io.c|9 +
2 files changed, 10 insertions
Allow prm init to success on OMAP5 SOCs.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/prm44xx.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index c05a343..1aae198 100644
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