On Monday 29 October 2012 01:35 PM, Felipe Balbi wrote:
On Mon, Oct 29, 2012 at 12:17:08PM +0530, Santosh Shilimkar wrote:
+ Jon,
On Friday 26 October 2012 06:49 PM, Tim Niemeyer wrote:
Adds support for configuring the omap-gpio driver use autosuspend for
runtime power management. This can
On Saturday 27 October 2012 04:31 AM, Paul Walmsley wrote:
Hi Felipe
just two quick comments
On Thu, 25 Oct 2012, Felipe Balbi wrote:
if we allow compiler reorder our writes, we could
fall into a situation where dev-buf_len is reset
for no apparent reason.
This bug was found with a simple
On Saturday 27 October 2012 03:09 AM, Jon Hunter wrote:
On 10/26/2012 03:01 PM, Felipe Balbi wrote:
Hi,
On Fri, Oct 26, 2012 at 03:19:13PM +0200, Tim Niemeyer wrote:
Adds support for configuring the omap-gpio driver use autosuspend for
runtime power management. This can reduce the latency in
On Saturday 27 October 2012 05:33 PM, Constantine Shulyupin wrote:
From: Constantine Shulyupin co...@makelinux.com
Tested SD (MMC) and Ethernet smsc95xx on linux-3.7-rc2
Signed-off-by: Constantine Shulyupin co...@makelinux.com
--
kernel size is 2.3 MiB
---
On Saturday 27 October 2012 09:29 PM, Paul Walmsley wrote:
On Sat, 27 Oct 2012, Santosh Shilimkar wrote:
Another alternative, which I will recommend to just make use of the
read*/wrire* instead __raw versions. The barriers are taken care
already and driver point of view, it is transparent
that we are aligned, so we can take this patch forward. Feel free
to add my ack in case you plan to refresh it.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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More
On Friday 26 October 2012 12:45 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [121024 23:34]:
On Thursday 25 October 2012 06:12 AM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [121024 17:36]:
* Santosh Shilimkar santosh.shilim...@ti.com [121017 06:35
On Friday 26 October 2012 01:18 PM, Bedia, Vaibhav wrote:
Hi,
Compiling the current linus/master (2ab3f29) using omap2plus_defconfig
throws up the following error
$make -j7 uImage
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
make[1]:
On Friday 26 October 2012 03:32 PM, Bedia, Vaibhav wrote:
On Fri, Oct 26, 2012 at 14:29:28, Shilimkar, Santosh wrote:
On Friday 26 October 2012 01:18 PM, Bedia, Vaibhav wrote:
Hi,
Compiling the current linus/master (2ab3f29) using omap2plus_defconfig
throws up the following error
$make -j7
On Thursday 25 October 2012 06:12 AM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [121024 17:36]:
* Santosh Shilimkar santosh.shilim...@ti.com [121017 06:35]:
(Looping Arnd and Olof)
On Wednesday 17 October 2012 06:58 PM, Lokesh Vutla wrote:
When building omap_l3_noc/smx drivers
On Thursday 25 October 2012 04:24 AM, Jon Hunter wrote:
On 10/24/2012 12:10 PM, Kevin Hilman wrote:
From: Kevin Hilman khil...@ti.com
When a GPIO bank is freed or shutdown, ensure that the banks
dbck_enable_mask is cleared also. Otherwise, context restore on
subsequent off-mode transition
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
just a cleanup patch trying to make exit path
more straightforward. No changes otherwise.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/i2c/busses/i2c-omap.c | 26 +-
1 file changed, 17 insertions(+), 9
On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
In case we loop on IRQ handler until stat is
finally zero, we would end up in a situation
where all I2C transfers would misteriously
timeout because we were not calling complete()
in that situation.
Fix the issue by moving
On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
on OMAP4+ we want to read IRQSTATUS_RAW register,
instead of IRQSTATUS. The reason being that IRQSTATUS
will only contain the bits which were enabled on
IRQENABLE_SET and that will break when we need to
poll for a certain bit which wasn't
On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
Later patches will come adding support for
reporting amount of bytes transferred so that
client drivers can count how many bytes are
left to transfer.
This is useful mostly in case of NACKs when
client driver wants to know exactly which
On Thursday 25 October 2012 06:22 PM, Felipe Balbi wrote:
Hi,
On Thu, Oct 25, 2012 at 06:23:57PM +0530, Santosh Shilimkar wrote:
On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
on OMAP4+ we want to read IRQSTATUS_RAW register,
instead of IRQSTATUS. The reason being that IRQSTATUS
On Thursday 25 October 2012 06:41 PM, Jon Hunter wrote:
On 10/25/2012 02:00 AM, Santosh Shilimkar wrote:
On Thursday 25 October 2012 04:24 AM, Jon Hunter wrote:
On 10/24/2012 12:10 PM, Kevin Hilman wrote:
From: Kevin Hilman khil...@ti.com
When a GPIO bank is freed or shutdown, ensure
bogus state to be restored, leaving
GPIO debounce enabled which then prevented the CORE powerdomain from
transitioning.
Reported-by: Paul Walmsley p...@pwsan.com
Cc: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Kevin Hilman khil...@ti.com
---
Acked-by: Santosh Shilimkar santosh.shilim
On Wednesday 24 October 2012 05:32 PM, Grazvydas Ignotas wrote:
On Tue, Oct 23, 2012 at 9:09 PM, Kevin Hilman
khil...@deeprootsystems.com wrote:
From: Kevin Hilman khil...@ti.com
When debounce clocks are disabled, ensure that the banks
dbck_enable_mask is cleared also. Otherwise, context
On Wednesday 24 October 2012 07:49 PM, Kevin Hilman wrote:
Grazvydas Ignotas nota...@gmail.com writes:
On Tue, Oct 23, 2012 at 9:09 PM, Kevin Hilman
khil...@deeprootsystems.com wrote:
From: Kevin Hilman khil...@ti.com
When debounce clocks are disabled, ensure that the banks
dbck_enable_mask
the
value of UART sysconfig before and after the offmode entry to
see if the smart-idle/smart-idle wakeup setting getting disturbed
for some reason.
Below is the OMAP4 commit am referring to.
commit 5ae256dcd91bf308826a4ac19598b27ebb86a536
Author: Santosh Shilimkar santosh.shilim...@ti.com
Date: Fri
Mark,
On Saturday 20 October 2012 03:23 AM, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
This series updates the crypto omap-sham driver and supporting
infrastructure.
Notes:
a) Based on current k.o. c9623de (Merge branch 'v4l_for_linus'
of
Tero, paul,
On Thursday 18 October 2012 02:07 PM, Tero Kristo wrote:
On Thu, 2012-10-18 at 06:48 +, Paul Walmsley wrote:
On Thu, 18 Oct 2012, Paul Walmsley wrote:
Here are some basic OMAP test results for Linux v3.7-rc1.
Logs and other details at
Paul !!
This series and part2 both looks good to me.
Sorry for not being able to help in some of these clean-ups
because of other work priorities as talked at LPC.
Feel free to add my ack for the whole series if you need one.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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To unsubscribe from
Lokesh. Looks fine to me.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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On Thursday 11 October 2012 01:41 PM, Benoit Cousson wrote:
Hi Lokesh,
On 10/11/2012 08:16 AM, Lokesh Vutla wrote:
+ devicetree-discuss
Hi Benoit,
On Wednesday 10 October 2012 08:31 PM, Benoit Cousson wrote:
On 10/10/2012 02:05 PM, Lokesh Vutla wrote:
Device tree data for the EMIF sdram
Tony,
On Friday 05 October 2012 03:34 AM, Tony Lindgren wrote:
Hi all,
Here are some more patches for early merging after -rc1 for v3.8
merge window to remove more plat includes for the ARM common
zImage support. These are based on top of current linux next +
kevin's cpufreq fixes.
Have
On Monday 08 October 2012 02:22 PM, Santosh Shilimkar wrote:
Tony,
On Friday 05 October 2012 03:34 AM, Tony Lindgren wrote:
Hi all,
Here are some more patches for early merging after -rc1 for v3.8
merge window to remove more plat includes for the ARM common
zImage support. These are based
...@github.com:SantoshShilimkar/linux.git for_3.7/omap5_arch_timer
for you to fetch changes up to 3c7c5dab44d6c8861bc86dab924353d8d40344f8:
ARM: OMAP5: Enable arch timer support (2012-09-19 13:00:37 +0530)
Santosh Shilimkar (2):
ARM: OMAP: Add
OMAP interconnect drivers are used for the interconnect error handling.
Since they are bus driver, lets move it to newly created drivers/bus.
Cc: Arnd Bergmann a...@arndb.de
Cc: Tony Lindgren t...@atomide.com
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Santosh Shilimkar
Benoit,
On Monday 13 August 2012 04:30 PM, Santosh Shilimkar wrote:
These are the few device tree related patches which has been posted and
reviewed on the list. They are intended for 3.7 merge window but I am
posting them early enough to get into linux-next and linux-omap for testing
...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
v5:
Updated the patch as per Greg's comment for moving
the lpddr2 dt timings generic
+0530)
Aneesh V (3):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI's EMIF sdram controller
ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
Santosh Shilimkar (2
Cousson b-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.6-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../bindings/memory
-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.6-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +
arch/arm/boot/dts/omap4-panda.dts | 13 ++
arch/arm/boot/dts/omap4
This provides PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |7 +++
arch/arm/mach-omap2/omap4-common.c |6 +-
2 files
Add cortex-a9 local timer support for all OMAP4 based
SOCs using DT.
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |6 ++
arch/arm/mach-omap2/timer.c |6 ++
2 files changed, 12 insertions(+)
diff
-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.6-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/lpddr2/lpddr2
Below are the couple of patches which enables the architected cpu local timer
support for OMAP5 devices.
Santosh Shilimkar (2):
ARM: OMAP: Add initialisation for the real-time counter.
ARM: OMAP5: Enable arch timer support
arch/arm/boot/dts/omap5.dtsi |6 +++
arch/arm/mach-omap2/Kconfig
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |6 ++
arch/arm/mach-omap2/Kconfig |1 +
arch/arm/mach-omap2
initialisation, hardware takes care of adjusting
the clock in different low power modes to keep counter rate constant.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Kconfig |4 ++
arch/arm/mach-omap2/timer.c | 89 ++-
2 files
used registers.
Reported-by: Grygorii Strashko grygorii.stras...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
v2: Added comment in the code.
arch/arm/mach-omap2/sleep44xx.S |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff
...@arm.linux.org.uk
Cc: Kevin Hilman khil...@ti.com
Reported-by: Tony Lindgren t...@atomide.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Applies against linux-omap master at commit cb07e339457.
arch/arm/mach-omap2/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach
Couple of patches which updates the device tree support for OMAP4.
- Pl310 L2 cache controller DT support
- ARM cortex-A9 local timer DT support
Tested on OMAP4430 SDP.
Santosh Shilimkar (2):
ARM: OMAP4: Add L2 Cache Controller in Device Tree
ARM: OMAP4: Add local timer support for Device
This provides PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |7 +++
arch/arm/mach-omap2/omap4-common.c |6 +-
2 files
Add cortex-a9 local timer support for all OMAP4 based
SOCs using DT.
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |6 ++
arch/arm/mach-omap2/timer.c | 11 ---
2 files changed, 14 insertions
from board file
ARM: OMAP5: board-generic: Add device tree support
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: Add the build support
Santosh Shilimkar (2):
ARM: OMAP5: Add the WakeupGen IP updates
ARM: OMAP5: Add SMP support
Tarun Kanti DebBarma (1):
ARM: Kconfig update to support
-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Makefile |1 +
arch/arm/mach-omap2/devices.c |2 +-
arch/arm/mach-omap2/omap_l3_noc.h | 22 ++
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b
From: R Sricharan r.sricha...@ti.com
Adding the minimal support for OMAP5 evm board
with device tree.
Reviewed-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/arm/omap
From: Tarun Kanti DebBarma tarun.ka...@ti.com
OMAP5 has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs, ARCH_NR_GPIO is set
to 512 instead of present 256.
Cc: Santosh Shilimkar santosh.shilim...@ti.com
From: R Sricharan r.sricha...@ti.com
Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
detection support.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/control.h |4
arch/arm/mach-omap2/id.c
the CR register offset accordingly.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/plat-omap/counter_32k.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/counter_32k.c b
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/common.h |1 +
arch/arm/mach-omap2/omap-headsmp.S
board's irq init
support with device tree.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 23 ++-
arch/arm/mach-omap2/common.h|6 --
arch/arm/mach-omap2/irq.c
Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/plat-omap/common.c |9 +
arch/arm/plat-omap/include/plat/omap-secure.h |5 -
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/plat-omap
the WakeupGen code accordingly.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |7 ++
arch/arm/mach-omap2/omap-hotplug.c| 24 -
arch/arm/mach-omap2/omap-smp.c
From: R Sricharan r.sricha...@ti.com
Adding the Initialisaton for clocksource and clockevent device
on OMAP5 Socs.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/common.h |1 +
arch/arm/mach-omap2/timer.c
From: R Sricharan r.sricha...@ti.com
GPMC module is the same as in OMAP4.
Just update the base address and irq number.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/gpmc.c |3 ++-
1 file changed, 2 insertions
support.
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: Add the build support
Santosh Shilimkar (2):
ARM: OMAP5: Add the WakeupGen IP updates
ARM: OMAP5: Add SMP support.
Tarun Kanti DebBarma (1):
ARM: Kconfig update to support additional GPIOs in OMAP5
.../devicetree/bindings/arm/omap
From: R Sricharan r.sricha...@ti.com
Adding the build support required for OMAP5 soc
in to omap2+ config.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/configs
introduced CONFIG_SOC_HAS_OMAP2_SDRC marco.
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/plat-omap/include/plat/sdrc.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h
b/arch/arm
Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/plat-omap/common.c |9 +
arch/arm/plat-omap/include/plat/omap-secure.h |5 -
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/plat-omap
-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Makefile |1 +
arch/arm/mach-omap2/devices.c |2 +-
arch/arm/mach-omap2/omap_l3_noc.h | 22 ++
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b
From: R Sricharan r.sricha...@ti.com
GPMC module is the same as in OMAP4.
Just update the base address and irq number.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/gpmc.c |3 ++-
1 file changed, 2 insertions
board's irq init
support with device tree.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/board-generic.c | 23 ++-
arch/arm/mach-omap2/common.h|6 --
arch/arm/mach-omap2/irq.c
From: R Sricharan r.sricha...@ti.com
Adding the build support required for OMAP5 soc
in to omap2+ config.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/configs
the CR register offset accordingly.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/plat-omap/counter_32k.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/counter_32k.c b
From: R Sricharan r.sricha...@ti.com
Adding the minimal support for OMAP5 evm board
with device tree.
Reviewed-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/arm/omap
From: Tarun Kanti DebBarma tarun.ka...@ti.com
OMAP5 has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs, ARCH_NR_GPIO is set
to 512 instead of present 256.
Cc: Santosh Shilimkar santosh.shilim...@ti.com
From: R Sricharan r.sricha...@ti.com
Adding the minimum device tree files required for
OMAP5 to boot.
Reviewed-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap5-evm.dts | 20
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/common.h |1 +
arch/arm/mach-omap2/omap-headsmp.S
handler support for omap5.
ARM: omap2+: board-generic: clean up the irq data from board file.
ARM: OMAP5: board-generic: Add device tree support.
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: Add the build support
Santosh Shilimkar (2):
ARM: OMAP5: Add the WakeupGen IP updates
ARM
From: R Sricharan r.sricha...@ti.com
Adding the minimum device tree files required for
OMAP5 to boot.
Reviewed-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap5-evm.dts | 20
From: R Sricharan r.sricha...@ti.com
Adding the Initialisaton for clocksource and clockevent device
on OMAP5 Socs.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/common.h |1 +
arch/arm/mach-omap2/timer.c
DDR3 and SATA.
Patch includes:
- The machine specific headers and sources updates.
- Platform header updates.
- Minimum initialisation support for serial.
- IO table init
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach
From: R Sricharan r.sricha...@ti.com
Adding the minimal support for OMAP5 evm board
with device tree.
Reviewed-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/arm/omap
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/kernel/arch_timer.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index dd58035..df44c8c 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch
Tony,
Here is the EMIF driver DT support which was kept on hold for the driver
to get merged. The series has been already reviewed on the list.
v4:
Fixed the DT config flag and rebased against 3.5-rc4
v3:
Rebased against the 3.5-rc2
This series adds device tree support for TI EMIF SDRAM
Cousson b-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../bindings/memory
-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/lpddr2/lpddr2
-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +
arch/arm/boot/dts/omap4-panda.dts | 13 ++
arch/arm/boot/dts/omap4
-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
drivers/memory/emif.c | 291 -
1 file changed, 290 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c
index 33a4396..101997b 100644
--- a/drivers
Tony,
Here is the EMIF driver DT support which was kept on hold for the driver
to get merged. The series has been already reviewed on the list.
This series adds device tree support for TI EMIF SDRAM controller
driver. For this, a binding has been added for representing AC timing
parameters and
-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../devicetree/bindings/lpddr2/lpddr2
-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +
arch/arm/boot/dts/omap4-panda.dts | 13 ++
arch/arm/boot/dts/omap4
Cousson b-cous...@ti.com
Reviewed-by: Grant Likely grant.lik...@secretlab.ca
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
[santosh.shilim...@ti.com: Rebased against 3.5-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
.../bindings/memory
-rc]
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/memory/emif.c | 285 -
1 file changed, 284 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/emif.c b/drivers/memory
Jean,
On Monday 21 May 2012 07:55 PM, Shilimkar, Santosh wrote:
Jean,
On Mon, May 21, 2012 at 7:23 PM, Jean Pihet jean.pi...@newoldbits.com wrote:
Hi Santosh,
On Thu, May 17, 2012 at 12:04 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
[...]
What do you think?
I like the idea
, and
set the irq to allow the clockevent core to determine the affinity of the
timer.
Signed-off-by: Colin Cross ccr...@android.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/timer.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git
synchronization for coupled idle states
Santosh Shilimkar (3):
ARM: OMAP: timer: allow gp timer clock-event to be used on both cpus
ARM: OMAP4: CPUidle: Use coupled cpuidle states to implement SMP
cpuidle.
ARM: OMAP4: CPUidle: Open broadcast clock-event device.
arch/arm/mach-omap2/Kconfig
mode was also broken. This change fixes both the periodic/oneshot broadcast
modes.
Discussion thread :
https://lkml.org/lkml/2012/4/9/13
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/cpuidle44xx.c | 13 +
1 files changed, 13 insertions(+), 0
the coupled
state enter method can return.
In addition, cpuidle_coupled_parallel_barrier() is used to ensure the
clearing of the 'done' flag is synchronized on all CPUs.
Signed-off-by: Kevin Hilman khil...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2
Cross on the suggestions/fixes
on the intermediate version of this patch.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Kconfig |1 +
arch/arm/mach-omap2/cpuidle44xx.c | 112 ++---
2 files changed, 67 insertions(+), 46
Jean,
On Tuesday 08 May 2012 02:10 PM, Jean Pihet wrote:
Paul,
On Mon, May 7, 2012 at 11:28 AM, Paul Walmsley p...@pwsan.com wrote:
Hi
On Wed, 18 Apr 2012, jean.pi...@newoldbits.com wrote:
From: Jean Pihet j-pi...@ti.com
Introduce functional (or logical) states for power domains and the
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
Santosh,
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
GIC distributor control register has changed between CortexA9 r1pX and
r2pX. The Control Register secure banked version is now composed
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh Shilimkar wrote:
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
Santosh,
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
GIC distributor control register has changed between CortexA9 r1pX
Tero,
On Monday 14 May 2012 03:33 PM, Tero Kristo wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
GIC distributor control register has changed between CortexA9 r1pX and
r2pX. The Control Register secure banked version is now composed of 2
bits:
bit 0 == Secure Enable
bit
+ Tarun for any comments
On Wednesday 16 May 2012 05:05 AM, Jon Hunter wrote:
From: Jon Hunter jon-hun...@ti.com
In order to migrate the dmtimer driver to support device-tree I found that it
was first necessary to clean-up the timer platform data. The goal of this
series is to simplify the
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