Sergei,
On Thu, Jan 26, 2012 at 12:26 PM, Sergei Shtylyov
sshtyl...@ru.mvista.com wrote:
Hello.
On 25-01-2012 19:16, Jean Pihet wrote:
...
Change-Id: Id0145adacfa63d7652a29859ad6c95cc2ac61cc8
Please remove this line.
Done!
...
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
Hello.
On 31-01-2012 14:06, Jean Pihet wrote:
...
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
+ u32 errconfig_offs, vpboundint_en;
+ u32 vpboundint_st;
+ struct omap_sr *sr = _sr_lookup(voltdm);
+
+ if (IS_ERR(sr)) {
+ pr_warning(%s: omap_sr
Sergei,
On Tue, Jan 31, 2012 at 12:37 PM, Sergei Shtylyov
sshtyl...@ru.mvista.com wrote:
Hello.
On 31-01-2012 14:06, Jean Pihet wrote:
...
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
+ u32 errconfig_offs, vpboundint_en;
+ u32 vpboundint_st;
+ struct
Hello.
On 25-01-2012 19:16, Jean Pihet wrote:
From: Nishanth Menonn...@ti.com
SmartReflex AVS Errorgen module supplies signals to Voltage
Processor. It is suggested that by disabling Errorgen module
before we disable VP, we might be able to ensure lesser
chances of race condition to occur
From: Nishanth Menon n...@ti.com
SmartReflex AVS Errorgen module supplies signals to Voltage
Processor. It is suggested that by disabling Errorgen module
before we disable VP, we might be able to ensure lesser
chances of race condition to occur in the system.
Change-Id:
