On 04/14/2015 08:29 PM, Lennart Sorensen wrote:
On Tue, Mar 17, 2015 at 06:41:51PM -0700, Tony Lindgren wrote:
Yeah agreed. I suggest discussing the binding and the generic
parsing code for it first :)
It seems with the generic binding the actual driver should be
just the hardware specific
On Wed, Apr 15, 2015 at 11:51:32AM -0500, Nishanth Menon wrote:
I am yet to post a new revision to this series - few other stuff got
in the way. IODelay driver in no way removes the constraint that the
SoC architecture has - most of the pins still need to be muxed in
bootloader - we cannot
On 04/15/2015 01:44 PM, Lennart Sorensen wrote:
On Wed, Apr 15, 2015 at 11:51:32AM -0500, Nishanth Menon wrote:
I am yet to post a new revision to this series - few other stuff got
in the way. IODelay driver in no way removes the constraint that the
SoC architecture has - most of the pins
On Tue, Mar 17, 2015 at 06:41:51PM -0700, Tony Lindgren wrote:
Yeah agreed. I suggest discussing the binding and the generic
parsing code for it first :)
It seems with the generic binding the actual driver should be
just the hardware specific code hopefully.
Did this thread go anywhere in
* Linus Walleij linus.wall...@linaro.org [150317 18:31]:
On Tue, Mar 10, 2015 at 7:33 PM, Nishanth Menon n...@ti.com wrote:
On 03/10/2015 12:31 PM, Tony Lindgren wrote:
Yes except I'd make use of some kind of #pinctrl-cells here just like
interrupt controller has #interrupt-cells. Then
On Tue, Mar 10, 2015 at 7:33 PM, Nishanth Menon n...@ti.com wrote:
On 03/10/2015 12:31 PM, Tony Lindgren wrote:
Yes except I'd make use of some kind of #pinctrl-cells here just like
interrupt controller has #interrupt-cells. Then you can have the values
seprate and the controller knows what
* Linus Walleij linus.wall...@linaro.org [150310 03:39]:
On Wed, Mar 4, 2015 at 1:00 AM, Nishanth Menon n...@ti.com wrote:
+Configuration definition follows similar model as the pinctrl-single:
+The groups of pin configuration are defined under pinctrl-single,pins
+
+dra7_iodelay_core {
On Wed, Mar 4, 2015 at 1:00 AM, Nishanth Menon n...@ti.com wrote:
+Configuration definition follows similar model as the pinctrl-single:
+The groups of pin configuration are defined under pinctrl-single,pins
+
+dra7_iodelay_core {
+ mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf {
+
On 03/10/2015 10:33 AM, Tony Lindgren wrote:
* Linus Walleij linus.wall...@linaro.org [150310 03:39]:
On Wed, Mar 4, 2015 at 1:00 AM, Nishanth Menon n...@ti.com wrote:
+Configuration definition follows similar model as the pinctrl-single:
+The groups of pin configuration are defined under
* Nishanth Menon n...@ti.com [150310 10:25]:
On 03/10/2015 10:33 AM, Tony Lindgren wrote:
* Linus Walleij linus.wall...@linaro.org [150310 03:39]:
On Wed, Mar 4, 2015 at 1:00 AM, Nishanth Menon n...@ti.com wrote:
+Configuration definition follows similar model as the pinctrl-single:
On 03/10/2015 05:39 AM, Linus Walleij wrote:
On Wed, Mar 4, 2015 at 1:00 AM, Nishanth Menon n...@ti.com wrote:
+Configuration definition follows similar model as the pinctrl-single:
+The groups of pin configuration are defined under pinctrl-single,pins
+
+dra7_iodelay_core {
+
On 03/10/2015 12:31 PM, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [150310 10:25]:
On 03/10/2015 10:33 AM, Tony Lindgren wrote:
* Linus Walleij linus.wall...@linaro.org [150310 03:39]:
On Wed, Mar 4, 2015 at 1:00 AM, Nishanth Menon n...@ti.com wrote:
+Configuration definition follows
On 03/10/2015 01:33 PM, Nishanth Menon wrote:
On 03/10/2015 12:31 PM, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [150310 10:25]:
On 03/10/2015 10:33 AM, Tony Lindgren wrote:
* Linus Walleij linus.wall...@linaro.org [150310 03:39]:
On Wed, Mar 4, 2015 at 1:00 AM, Nishanth Menon
SoCs such as DRA7 family from Texas Instruments also include a highly
configurable hardware block called the IOdelay block. This block
allows very specific custom fine tuning for electrical characteristics
of IO pins.
In addition to the regular pin muxing modes supported by the
pinctrl-single,
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