Hi Pekon,
On 05/12/2014 12:05 PM, Gupta, Pekon wrote:
From: Javier Martinez Canillas [mailto:jav...@dowhile0.org]
[...]
Newer platforms have upgraded version of GPMC engine which supports
BCH16 ECC scheme in hardware. Thus the GPMC address space was
expanded to include some extra registers
Hi Roger,
For now, I'll use GPMC address-space size = 0x380 as it matches with
actual hardware and is working.
How did you get 0x380?
From DRA7 TRM, GPMC address range is 0x5000 : 0x5000 02D0
So the address-space size should be 0x2D4 (as last register@2D0 is 32-bits
wide)
I think that
On 05/14/2014 11:25 AM, Roger Quadros wrote:
Hi Pekon,
On 05/12/2014 12:05 PM, Gupta, Pekon wrote:
From: Javier Martinez Canillas [mailto:jav...@dowhile0.org]
[...]
Newer platforms have upgraded version of GPMC engine which supports
BCH16 ECC scheme in hardware. Thus the GPMC address
From: Quadros, Roger
[...]
For now, I'll use GPMC address-space size = 0x380 as it matches with
actual hardware and is working.
How did you get 0x380?
From DRA7 TRM, GPMC address range is 0x5000 : 0x5000 02D0
So the address-space size should be 0x2D4 (as last register@2D0 is 32-bits
On 05/14/2014 12:09 PM, Gupta, Pekon wrote:
From: Quadros, Roger
[...]
For now, I'll use GPMC address-space size = 0x380 as it matches with
actual hardware and is working.
How did you get 0x380?
From DRA7 TRM, GPMC address range is 0x5000 : 0x5000 02D0
So the address-space size
On Wed, May 14, 2014 at 11:17 AM, Roger Quadros rog...@ti.com wrote:
On 05/14/2014 12:09 PM, Gupta, Pekon wrote:
From: Quadros, Roger
[...]
For now, I'll use GPMC address-space size = 0x380 as it matches with
actual hardware and is working.
How did you get 0x380?
From DRA7 TRM, GPMC
Hello,
From: Javier Martinez Canillas [mailto:jav...@dowhile0.org]
On Fri, May 9, 2014 at 10:46 PM, Pekon Gupta pe...@ti.com wrote:
From: Minal Shah minalks...@gmail.com
[...]
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges
Hello Pekon,
On Mon, May 12, 2014 at 9:03 AM, Gupta, Pekon pe...@ti.com wrote:
Hello,
From: Javier Martinez Canillas [mailto:jav...@dowhile0.org]
On Fri, May 9, 2014 at 10:46 PM, Pekon Gupta pe...@ti.com wrote:
From: Minal Shah minalks...@gmail.com
[...]
+gpmc {
+ status = okay;
+
From: Javier Martinez Canillas [mailto:jav...@dowhile0.org]
[...]
Newer platforms have upgraded version of GPMC engine which supports
BCH16 ECC scheme in hardware. Thus the GPMC address space was
expanded to include some extra registers required for BCH16 ECC [2].
I see and did the GPMC
On Mon, May 12, 2014 at 11:05 AM, Gupta, Pekon pe...@ti.com wrote:
From: Javier Martinez Canillas [mailto:jav...@dowhile0.org]
[...]
Newer platforms have upgraded version of GPMC engine which supports
BCH16 ECC scheme in hardware. Thus the GPMC address space was
expanded to include some extra
Hello Pekon,
On Fri, May 9, 2014 at 10:46 PM, Pekon Gupta pe...@ti.com wrote:
From: Minal Shah minalks...@gmail.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for
From: Minal Shah minalks...@gmail.com
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP)
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