Hi Paul,
On 11/29/2011 7:11 PM, Paul Walmsley wrote:
On Tue, 29 Nov 2011, Cousson, Benoit wrote:
On 11/27/2011 3:07 AM, Paul Walmsley wrote:
So just out of curiosity, do those SYSCONFIG registers in the STM address
space apply to the entire DEBUGSS, or just the STM IP block?
The STM IP is
Hi Paul,
On 11/27/2011 3:07 AM, Paul Walmsley wrote:
On Sat, 26 Nov 2011, Paul Walmsley wrote:
Hi Benoît,
a question about this patch.
...
+ .name = mipi_stm,
+ .pa_start = 0x54161000,
+ .pa_end = 0x54161fff,
+
On Tue, 29 Nov 2011, Cousson, Benoit wrote:
On 11/27/2011 3:07 AM, Paul Walmsley wrote:
So just out of curiosity, do those SYSCONFIG registers in the STM address
space apply to the entire DEBUGSS, or just the STM IP block?
The STM IP is the only one to have the TI generic wrapper to be
Hi Benoît,
a question about this patch.
On Fri, 18 Nov 2011, Cousson, Benoit wrote:
From: Benoit Cousson b-cous...@ti.com
Date: Fri, 18 Nov 2011 11:42:12 +0100
Subject: [PATCH] ARM: OMAP4: hwmod data: Add support for the debug modules
The OMAP4 DEBUG subsystem contains all the IPs used
On Sat, 26 Nov 2011, Paul Walmsley wrote:
Hi Benoît,
a question about this patch.
...
+ .name = mipi_stm,
+ .pa_start = 0x54161000,
+ .pa_end = 0x54161fff,
+ .flags = ADDR_TYPE_RT
... none of the address
On Sun, Nov 20, 2011 at 03:27:19AM +, Paul Walmsley wrote:
The OMAP-specific parts should be queued up in my/Benoît's/Tony's trees,
rather than placed directly into -next. Otherwise they are likely to
generate merge conflicts with other OMAP changes that we may generate.
So I'd
Hi,
On Mon, Nov 21, 2011 at 9:58 PM, Will Deacon will.dea...@arm.com wrote:
On Sun, Nov 20, 2011 at 03:27:19AM +, Paul Walmsley wrote:
The OMAP-specific parts should be queued up in my/Benoît's/Tony's trees,
rather than placed directly into -next. Otherwise they are likely to
generate
On Mon, Nov 21, 2011 at 02:53:54PM +, Ming Lei wrote:
On Mon, Nov 21, 2011 at 9:58 PM, Will Deacon will.dea...@arm.com wrote:
On Sun, Nov 20, 2011 at 03:27:19AM +, Paul Walmsley wrote:
The OMAP-specific parts should be queued up in my/Benoît's/Tony's trees,
rather than placed
On Mon, Nov 21, 2011 at 11:16 PM, Will Deacon will.dea...@arm.com wrote:
On Mon, Nov 21, 2011 at 02:53:54PM +, Ming Lei wrote:
On Mon, Nov 21, 2011 at 9:58 PM, Will Deacon will.dea...@arm.com wrote:
On Sun, Nov 20, 2011 at 03:27:19AM +, Paul Walmsley wrote:
The OMAP-specific parts
Hi Benoit,
On Fri, Nov 18, 2011 at 8:58 PM, Cousson, Benoit b-cous...@ti.com wrote:
Hi Ming Lei,
Sorry, for the delay, it took me some time to gather the exhaustive data for
that block.
The work is really great.
On 11/10/2011 10:02 AM, Paul Walmsley wrote:
Hello Ming Lei,
just a few
Hi Will,
On Fri, Nov 18, 2011 at 10:56 PM, Will Deacon will.dea...@arm.com wrote:
Hi Benoit,
On Fri, Nov 18, 2011 at 12:58:20PM +, Cousson, Benoit wrote:
Hi Ming Lei,
Sorry, for the delay, it took me some time to gather the exhaustive data for
that block.
Thanks for looking at this!
Hi
On Sat, 19 Nov 2011, Ming Lei wrote:
On Fri, Nov 18, 2011 at 10:56 PM, Will Deacon will.dea...@arm.com wrote:
Ming Lei - can you take this into your patch series please?
Yes, I have made omap4 pmu work already with Benoit's patch,
and if no one has objections on other patches(5/7,
Hi Ming Lei,
Sorry, for the delay, it took me some time to gather the exhaustive data for
that block.
On 11/10/2011 10:02 AM, Paul Walmsley wrote:
Hello Ming Lei,
just a few quick comments for now -
On Wed, 9 Nov 2011, Ming Lei wrote:
On Tue, Nov 8, 2011 at 11:26 PM, Paul
Hi Benoit,
On Fri, Nov 18, 2011 at 12:58:20PM +, Cousson, Benoit wrote:
Hi Ming Lei,
Sorry, for the delay, it took me some time to gather the exhaustive data for
that block.
Thanks for looking at this! I don't think we'd have managed to get all of
the magic numbers in the right place
[Adding Benoit to CC].
On Thu, Nov 10, 2011 at 09:02:14AM +, Paul Walmsley wrote:
On Wed, 9 Nov 2011, Ming Lei wrote:
Also, current arm perf code don't handle three IRQs(one pl310 irq and
two CTI irq) inside one device correctly.
To fix this, that ARM perf code should either be using
On Fri, Nov 11, 2011 at 11:41:47AM +, Will Deacon wrote:
[Adding Benoit to CC].
On Thu, Nov 10, 2011 at 09:02:14AM +, Paul Walmsley wrote:
On Wed, 9 Nov 2011, Ming Lei wrote:
Also, current arm perf code don't handle three IRQs(one pl310 irq and
two CTI irq) inside one device
On Fri, Nov 11, 2011 at 11:47:35AM +, Jamie Iles wrote:
On Fri, Nov 11, 2011 at 11:41:47AM +, Will Deacon wrote:
The issue stems from the fact that we have to route the PMU interrupts to
the correct CPU manually (I think only MSM routes them as PPIs, which is
clearly the correct
On 11/11/2011 12:47 PM, Jamie Iles wrote:
On Fri, Nov 11, 2011 at 11:41:47AM +, Will Deacon wrote:
[Adding Benoit to CC].
On Thu, Nov 10, 2011 at 09:02:14AM +, Paul Walmsley wrote:
On Wed, 9 Nov 2011, Ming Lei wrote:
Also, current arm perf code don't handle three IRQs(one pl310 irq
Hi Benoit,
On Fri, Nov 11, 2011 at 02:56:05PM +, Cousson, Benoit wrote:
It will come soon... along with the updated patch for reg-names support.
Actually, I was hoping you could help Ming Lei with the hwmod stuff :)
Will
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Hi Will,
On 11/11/2011 3:58 PM, Will Deacon wrote:
Hi Benoit,
On Fri, Nov 11, 2011 at 02:56:05PM +, Cousson, Benoit wrote:
It will come soon... along with the updated patch for reg-names support.
Actually, I was hoping you could help Ming Lei with the hwmod stuff :)
And I'll do :-)
On Fri, Nov 11, 2011 at 03:12:49PM +, Cousson, Benoit wrote:
Hi Will,
Hello,
On 11/11/2011 3:58 PM, Will Deacon wrote:
Actually, I was hoping you could help Ming Lei with the hwmod stuff :)
And I'll do :-)
Cheers!
We already started looking at that with Paul a couple of days ago,
Hello Ming Lei,
just a few quick comments for now -
On Wed, 9 Nov 2011, Ming Lei wrote:
On Tue, Nov 8, 2011 at 11:26 PM, Paul Walmsley p...@pwsan.com wrote:
+static struct omap_hwmod_irq_info omap44xx_emu_irqs[] = {
+ { .name = cti0, .irq = 1 + OMAP44XX_IRQ_GIC_START },
+ {
Hi,
Thanks for your comments.
On Tue, Nov 8, 2011 at 11:26 PM, Paul Walmsley p...@pwsan.com wrote:
+static struct omap_hwmod_irq_info omap44xx_emu_irqs[] = {
+ { .name = cti0, .irq = 1 + OMAP44XX_IRQ_GIC_START },
+ { .name = cti1, .irq = 2 + OMAP44XX_IRQ_GIC_START },
+ { .irq =
Hi,
On Tue, Nov 8, 2011 at 11:42 PM, Paul Walmsley p...@pwsan.com wrote:
Hi
I just read
http://comments.gmane.org/gmane.comp.embedded.pandaboard/168
Looks to me that the L3_EMU interconnect and the emulation IP blocks need
You mean the emu hwmod in the patch should be kept and a new
Hi
some comments
On Mon, 24 Oct 2011, ming@canonical.com wrote:
From: Ming Lei ming@canonical.com
So that access to cross trigger interface can be allowed, which
will be introduce in later patches.
Signed-off-by: Ming Lei ming@canonical.com
---
Hi
I just read
http://comments.gmane.org/gmane.comp.embedded.pandaboard/168
Looks to me that the L3_EMU interconnect and the emulation IP blocks need
to be added to the OMAP4 hwmod data, based on Section 2.2.1 L3_EMU Memory
Space Mapping in the OMAP4460 TRM Rev. I. If the clockdomain
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