On Thu, Oct 7, 2010 at 10:16 PM, Omar Ramirez Luna omar.rami...@ti.com wrote:
On 10/7/2010 1:22 PM, Felipe Contreras wrote:
...
Note that the shared memory described in the document you share has
nothing to do with the SHM pool. AFAIK that memory is used for other
things, like MMU PTEs, and
On Thu, Oct 7, 2010 at 10:16 PM, Omar Ramirez Luna omar.rami...@ti.com wrote:
On 10/7/2010 1:22 PM, Felipe Contreras wrote:
Anyway, we will not know for sure until we try... Right?
yes we can try, at least we now for sure arm side can be done.
The only thing that changes is the cacheability
On 10/8/2010 3:18 AM, Felipe Contreras wrote:
On Thu, Oct 7, 2010 at 10:16 PM, Omar Ramirez Lunaomar.rami...@ti.com wrote:
On 10/7/2010 1:22 PM, Felipe Contreras wrote:
...
Note that the shared memory described in the document you share has
nothing to do with the SHM pool. AFAIK that memory
On 10/8/2010 3:20 AM, Felipe Contreras wrote:
On Thu, Oct 7, 2010 at 10:16 PM, Omar Ramirez Lunaomar.rami...@ti.com wrote:
On 10/7/2010 1:22 PM, Felipe Contreras wrote:
Anyway, we will not know for sure until we try... Right?
yes we can try, at least we now for sure arm side can be done.
On Thu, Oct 07, 2010 at 09:40:12AM +0200, Laurent Pinchart wrote:
Hi Omar,
On Thursday 07 October 2010 07:45:36 Omar Ramirez Luna wrote:
tidspbridge driver uses a block of memory denominated SHared Memory
to store info communicate with DSP, this SHM needs to be physically
contiguous and
Hi Russell
On Thursday 07 October 2010 10:32:42 Russell King - ARM Linux wrote:
On Thu, Oct 07, 2010 at 09:40:12AM +0200, Laurent Pinchart wrote:
Hi Omar,
On Thursday 07 October 2010 07:45:36 Omar Ramirez Luna wrote:
tidspbridge driver uses a block of memory denominated SHared Memory
On 10/7/2010 2:40 AM, Laurent Pinchart wrote:
Hi Omar,
On Thursday 07 October 2010 07:45:36 Omar Ramirez Luna wrote:
tidspbridge driver uses a block of memory denominated SHared Memory
to store info communicate with DSP, this SHM needs to be physically
contiguous and non-cacheable,
There
On 10/7/2010 9:01 AM, Laurent Pinchart wrote:
On Thursday 07 October 2010 10:32:42 Russell King - ARM Linux wrote:
ARMv6 and above don't like having multiple mappings with different
memory type/shareability/cache attributes. It's architecturally
forbidden.
So if you want non-cacheable memory
On Thu, Oct 7, 2010 at 8:01 PM, Omar Ramirez Luna omar.rami...@ti.com wrote:
On 10/7/2010 2:40 AM, Laurent Pinchart wrote:
On Thursday 07 October 2010 07:45:36 Omar Ramirez Luna wrote:
tidspbridge driver uses a block of memory denominated SHared Memory
to store info communicate with DSP,
On Thu, Oct 07, 2010 at 04:01:02PM +0200, Laurent Pinchart wrote:
Do we have an infrastructure, or even an embryo thereof, to remove pages from
the kernel's direct-mapped memory mapping at runtime ? The use of super pages
probably complicates the matter.
No, and yes, using section
On 10/7/2010 1:22 PM, Felipe Contreras wrote:
...
Note that the shared memory described in the document you share has
nothing to do with the SHM pool. AFAIK that memory is used for other
things, like MMU PTEs, and storing the base image and socket-nodes,
thus it needs to be contiguous.
hmmm,
tidspbridge driver uses a block of memory denominated SHared Memory
to store info communicate with DSP, this SHM needs to be physically
contiguous and non-cacheable, to achieve the latter the driver ioremaps
the memory reserved to be SHM, this will trigger a warning if the
memory is under kernel
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