In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.
On Thu, Sep 13, 2012 at 11:20:49AM +0100, Lorenzo Pieralisi wrote:
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache
On Thu, Sep 13, 2012 at 6:23 PM, Dave Martin dave.mar...@linaro.org wrote:
On Thu, Sep 13, 2012 at 11:20:49AM +0100, Lorenzo Pieralisi wrote:
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore.
On Thu, Sep 13, 2012 at 06:31:35PM +0530, Shilimkar, Santosh wrote:
In the series, there is patch [PATCH 3/6] which adds an
API which let you operate on a specific level.
Which is introduced but as far as I can see, is never used in the patch
set. Therefore, it shouldn't be introduced.
We've
On Thu, Sep 13, 2012 at 6:38 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Sep 13, 2012 at 06:31:35PM +0530, Shilimkar, Santosh wrote:
In the series, there is patch [PATCH 3/6] which adds an
API which let you operate on a specific level.
Which is introduced but as far as
On Thu, Sep 13, 2012 at 01:53:48PM +0100, Dave Martin wrote:
On Thu, Sep 13, 2012 at 11:20:49AM +0100, Lorenzo Pieralisi wrote:
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For
On Thu, Sep 13, 2012 at 02:01:35PM +0100, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 6:23 PM, Dave Martin dave.mar...@linaro.org wrote:
[...]
LoUIS matches the power domain affected by turning a single CPU off
on most (all?) current v7 SoCs where this matters, but only by
