On Thursday 19 January 2012 07:58 PM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently,
we have added properties for only DDR3 and LPDDR2 memories.
However, the binding
Hi,
On Mon, Jan 16, 2012 at 11:15 AM, Turquette, Mike mturque...@ti.com wrote:
And delaying DVFS (at least for the parts affecting mem) until
userspace is loaded doesn't seem great to me either. We're basically
pushing back feature readiness (with respect to boot sequence) in the
name of
Hi Olof,
On Saturday 14 January 2012 01:06 AM, Aneesh V wrote:
Hi Olof,
snip
We wish to drop the DDR3 support because we have concluded that our
platforms with DDR3 memories will not scale DDR frequency due to
limitations in DDR3 protocol(operating frequency can vary only in a
small range).
On Fri, Jan 13, 2012 at 11:36 AM, Aneesh V ane...@ti.com wrote:
Hi Olof,
On Monday 09 January 2012 11:12 AM, Olof Johansson wrote:
Hi,
On Sun, Jan 8, 2012 at 9:23 AM, Aneesh Vane...@ti.com wrote:
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20
Hi Olof,
On Monday 09 January 2012 11:12 AM, Olof Johansson wrote:
Hi,
On Sun, Jan 8, 2012 at 9:23 AM, Aneesh Vane...@ti.com wrote:
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
snip
In
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
snip
In general, is it really feasible to parse the DTB before DDR is
initialized?
Changing timings is still needed for DVFS during runtime.
But
Hi,
On Sun, Jan 8, 2012 at 9:23 AM, Aneesh V ane...@ti.com wrote:
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
snip
In general, is it really feasible to parse the DTB before DDR is
On Tuesday 20 December 2011 04:31 AM, Rob Herring wrote:
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently,
we have added properties for only
On Tuesday 20 December 2011 05:05 AM, Tony Lindgren wrote:
* Rob Herringrobherri...@gmail.com [111219 14:29]:
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR
Hi Aneesh,
On 12/20/2011 11:44 AM, Aneesh V wrote:
On Tuesday 20 December 2011 05:05 AM, Tony Lindgren wrote:
* Rob Herringrobherri...@gmail.com [111219 14:29]:
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
snip
In general, is it really feasible to parse the DTB before DDR is
initialized?
Changing timings is still needed for DVFS during runtime.
But we can boot to userspace with bootloader set timings, so I'm
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently,
we have added properties for only DDR3 and LPDDR2 memories.
However, the binding can be
* Rob Herring robherri...@gmail.com [111219 14:29]:
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently,
we have added properties for
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