DSI supports interleaving of command mode packets during the HSA, HFP, HBP and
BLLP blanking intervals in a video mode stream. This is useful as a user may
want to read or change the configuration of a panel without stopping the video
stream.
On OMAP DSI, we can queue HS or LP command mode
On Sat, May 12, 2012 at 22:45:04, Tony Lindgren wrote:
* Hiremath, Vaibhav hvaib...@ti.com [120512 01:26]:
On Sat, May 12, 2012 at 01:26:20, Tony Lindgren wrote:
Hi,
* Cousson, Benoit b-cous...@ti.com [120511 05:51]:
Hi Tony,
Here are some remaining DT patches I was not
On 14/05/12 17:52, Mark Brown wrote:
On Mon, May 14, 2012 at 10:58:31AM +0900, Graeme Gregory wrote:
Looks good, quite a few of the things below are updates for very
recently introduced APIs.
+static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
+unsigned int
Hello Afzal,
On 05/14/12 12:33, Mohammed, Afzal wrote:
Hi All,
On Thu, May 03, 2012 at 14:12:11, Mohammed, Afzal wrote:
Some boards depend on bootloader to update chip select value for NAND.
It is felt that Kernel should not depend on bootloader to get CS, as
for a particular board CS is
Hi Thomas,
On Tue, May 15, 2012 at 12:00:32, Thomas Weber wrote:
I need a help.
Can someone familiar with boards - devkit8000, omap3touchbook, overo boards,
let me know GPMC CS on which NAND is connected.
On Devkit8000 the NAND is connected to CS0.
Thanks for the information
I
This is the MFD and regulator parts for the Palmas family of chips from
Texas Instruments.
It has been decided to use the Palmas name in the driver instead of
the various marketing names the family will be avilable with to avoid
confusion. The driver will in the future determine the exact product
Add the new palmas MFD to Kconfig and Makefile
Signed-off-by: Graeme Gregory g...@slimlogic.co.uk
---
drivers/mfd/Kconfig | 10 ++
drivers/mfd/Makefile |1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9846424..8565658 100644
---
Add the Kconfig/Makefile stuff for the palmas regulator driver
Signed-off-by: Graeme Gregory g...@slimlogic.co.uk
---
drivers/regulator/Kconfig | 12
drivers/regulator/Makefile |1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/regulator/Kconfig
Palmas has both Switched Mode (SMPS) and Linear (LDO) regulators in it.
This regulator driver allows software control of these regulators.
The regulators available on Palmas series chips vary depending on the muxing.
This is handled automatically in the driver by reading the mux info from OTP.
On Fri, May 11, 2012 at 09:02:14PM +0100, Tony Lindgren wrote:
* Afzal Mohammed af...@ti.com [120511 08:48]:
Provide helper function for updating NAND register details for
the necessary chip select. NAND drivers platform data can be
updated with this information so that NAND driver can
On Mon, 2012-05-14 at 15:48 -0700, Kevin Hilman wrote:
Tomi Valkeinen tomi.valkei...@ti.com writes:
On Mon, 2012-05-14 at 08:36 +0100, Joe Woodward wrote:
Any news on this?
This thread seems to have gone a little quiet...
Hi,
I've been doing testing to understand the problem,
On Tue, May 15, 2012 at 09:49:24AM +0530, Vinod Koul wrote:
On Mon, 2012-04-23 at 17:04 +0100, Russell King - ARM Linux wrote:
For the full text, please see
http://lists.arm.linux.org.uk/lurker/message/20120418.100954.7fa7acf8.en.html
This version contains updates for some of the
Hi Mark,
On Mon, Apr 30, 2012 at 11:26 PM, Mark A. Greer mgr...@animalcreek.com wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs only support the PWRSTS_ON
state so create a new set of powerdomain structures
that ensure that only the ON state is entered.
DISPC has two accumulator registers DISPC_VIDp_ACCU_0 and DISPC_VIDp_ACCU_1 each
with horizontal and vertical bit fields. The bit fields can take values in the
range of -1024 to 1023. Based on bit field values DISPC decides on which one out
of 8 phases the filtering starts. DISPC_VIDp_ACCU_0 is
On Tue, 2012-05-15 at 08:41 +0100, Russell King - ARM Linux wrote:
On Tue, May 15, 2012 at 09:49:24AM +0530, Vinod Koul wrote:
On Mon, 2012-04-23 at 17:04 +0100, Russell King - ARM Linux wrote:
For the full text, please see
On Tue, May 15, 2012 at 02:29:27PM +0530, Vinod Koul wrote:
On Tue, 2012-05-15 at 08:41 +0100, Russell King - ARM Linux wrote:
It's not ready for merging. While it allows some of the OMAP drivers
to be converted, there's others which need changes to omap-dma.c.
So, I'm _not_ planning to
Hi Tony,
Could you please take this patch.
Its absence raises some issues like Errata maintenance.
Thanks,
_vr
On Thu, Apr 19, 2012 at 10:23 AM, Roger Quadros rog...@ti.com wrote:
Hi,
On 04/18/2012 07:50 PM, Tony Lindgren wrote:
Hi,
* Roger Quadros rog...@ti.com [120403 02:50]:
Commit 68523f4233de5f233478dde0a63047b4efb710b8 (ARM: OMAP4:
Workaround the OCP synchronisation issue with 32K synctimer)
does not include GP Timers in ABE domain. Since synchronization
issue is applicable to all GPTIMER[1-12], we also need to set
static dependency of MPUSS with abe_clkdm and
Eric,
This looks interesting, but I'll add the linux-omap list to CC so
someone can verify if there isn't already a patch to export this.
On Tue, May 15, 2012 at 2:57 AM, eric van tassell evt...@gmail.com wrote:
- These changes make OMAP power state register fields available as
attributes per
Hi Kevin,
On 5/15/2012 4:58 AM, Kevin Hilman wrote:
+Sekhar,
Mark A. Greer mgr...@animalcreek.com writes:
From: Mark A. Greer mgr...@animalcreek.com
Paul, Kevin,
These patches convert the davinci emac support for the am35x SoC
to use hwmod and add enable_hlt()/disable_hlt() calls to
On 05/15/12 00:32, Kevin Hilman wrote:
Mark A. Greer mgr...@animalcreek.com writes:
On Mon, May 14, 2012 at 11:20:58AM +0300, Igor Grinberg wrote:
Hi Mark,
Hi Igor.
Thanks for the great work!
On 05/12/12 00:12, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x
On Tue, 2012-05-15 at 13:34 +0530, Chandrabhanu Mahapatra wrote:
DISPC has two accumulator registers DISPC_VIDp_ACCU_0 and DISPC_VIDp_ACCU_1
each
with horizontal and vertical bit fields. The bit fields can take values in the
range of -1024 to 1023. Based on bit field values DISPC decides on
On Sat, May 12, 2012 at 12:51:00AM +0100, Jon Hunter wrote:
On 05/11/2012 11:38 AM, Will Deacon wrote:
Excellent, that works for me. Once we've worked out the problem with my
.config you can have my tested-by.
Great! I have been looking at your .config, but I have not been able to
figure
+ Paul
Hi Tarun,
On 5/15/2012 1:42 PM, Tarun Kanti DebBarma wrote:
Commit 68523f4233de5f233478dde0a63047b4efb710b8 (ARM: OMAP4:
Workaround the OCP synchronisation issue with 32K synctimer)
does not include GP Timers in ABE domain. Since synchronization
issue is applicable to all
Hi Santosh, Benoit,
On 05/10/2012 01:54 AM, Santosh Shilimkar wrote:
On Thursday 10 May 2012 03:06 AM, Jon Hunter wrote:
From: Jon Hunter jon-hun...@ti.com
For OMAP3+ devices, the clock domains (CLKDMs) support one or more of the
following transition modes ...
NO_SLEEP (0x0) - A clock
Hi Ming,
On 05/14/2012 11:53 PM, Ming Lei wrote:
On Thu, May 10, 2012 at 5:35 AM, Jon Hunter jon-hun...@ti.com wrote:
From: Jon Hunter jon-hun...@ti.com
This patch is based upon Ming Lei's patch to add runtime PM support for OMAP4
[1]. In Ming's original patch the CTI interrupts were being
Hi Jon,
On 5/15/2012 4:33 PM, Jon Hunter wrote:
Hi Santosh, Benoit,
On 05/10/2012 01:54 AM, Santosh Shilimkar wrote:
On Thursday 10 May 2012 03:06 AM, Jon Hunter wrote:
From: Jon Hunterjon-hun...@ti.com
For OMAP3+ devices, the clock domains (CLKDMs) support one or more of the
following
On Tue, May 15, 2012 at 8:10 PM, Cousson, Benoit b-cous...@ti.com wrote:
Hi Jon,
On 5/15/2012 4:33 PM, Jon Hunter wrote:
Hi Santosh, Benoit,
On 05/10/2012 01:54 AM, Santosh Shilimkar wrote:
On Thursday 10 May 2012 03:06 AM, Jon Hunter wrote:
From: Jon Hunterjon-hun...@ti.com
For
Hi Tony, Artem,
This series creates a fictitious GPMC interrupt chip and provide the
clients with interrupts that could be handled using standard APIs.
This helps in removing the requirement of driver of peripheral
connected to GPMC having the knowledge about GPMC. The only user is
OMAP NAND
Modify interrupt handling such that interrupts can be handled by GPMC
client drivers using standard interrupt APIs rather than requiring
the drivers to have knowledge about GPMC interrupt handling. Currently
only NAND related interrupts has been considered (which is the case
even without this
Now GPMC provides its client with interrupts that can be handled
using the standard interrupt API. Modify GPMC NAND setup to work
with it.
Also disable write protect in GPMC code, so that NAND driver can
be ignorant of GPMC configuration.
This helps in smooth migration of GPMC to driver.
GPMC driver provides it's clients with interrupts that can be used
through struct resource. Make use of it for irq mode functionality.
Also now write protect disable is done by GPMC code, hence remove it.
Signed-off-by: Afzal Mohammed af...@ti.com
---
drivers/mtd/nand/omap2.c | 70
On Tue, May 15, 2012 at 8:02 PM, Cousson, Benoit b-cous...@ti.com wrote:
+ Paul
Hi Tarun,
On 5/15/2012 1:42 PM, Tarun Kanti DebBarma wrote:
Commit 68523f4233de5f233478dde0a63047b4efb710b8 (ARM: OMAP4:
Workaround the OCP synchronisation issue with 32K synctimer)
does not include GP Timers
Hi Tony,
On Tue, May 15, 2012 at 20:08:34, Mohammed, Afzal wrote:
Modify interrupt handling such that interrupts can be handled by GPMC
client drivers using standard interrupt APIs rather than requiring
the drivers to have knowledge about GPMC interrupt handling. Currently
only NAND related
On Tue, May 15, 2012 at 03:42:09PM +0300, Igor Grinberg wrote:
On 05/15/12 00:32, Kevin Hilman wrote:
Mark A. Greer mgr...@animalcreek.com writes:
On Mon, May 14, 2012 at 11:20:58AM +0300, Igor Grinberg wrote:
Hi Mark,
Hi Igor.
Thanks for the great work!
On 05/12/12 00:12,
On 5/15/2012 5:00 PM, Shilimkar, Santosh wrote:
On Tue, May 15, 2012 at 8:02 PM, Cousson, Benoitb-cous...@ti.com wrote:
+ Paul
Hi Tarun,
On 5/15/2012 1:42 PM, Tarun Kanti DebBarma wrote:
Commit 68523f4233de5f233478dde0a63047b4efb710b8 (ARM: OMAP4:
Workaround the OCP synchronisation issue
Tomi Valkeinen tomi.valkei...@ti.com writes:
On Mon, 2012-05-14 at 15:48 -0700, Kevin Hilman wrote:
Tomi Valkeinen tomi.valkei...@ti.com writes:
On Mon, 2012-05-14 at 08:36 +0100, Joe Woodward wrote:
Any news on this?
This thread seems to have gone a little quiet...
Hi,
I've
Hi Amit, Eric,
Amit Kucheria amit.kuche...@linaro.org writes:
Eric,
This looks interesting, but I'll add the linux-omap list to CC so
someone can verify if there isn't already a patch to export this.
We used to have similar PM debug code in the kernel, but as the one who
maintained it, I
Hello Tomi,
On Mon, 14 May 2012, Tomi Valkeinen wrote:
I've been doing testing to understand the problem, but so far I don't
have any idea why things go wrong. I haven't found out any logic in
which configuration works and which doesn't. Looks to me that for some
reason the PM prevents DSS
On Tue, May 15, 2012 at 03:12:45PM +0900, Graeme Gregory wrote:
On 14/05/12 17:52, Mark Brown wrote:
On Mon, May 14, 2012 at 10:58:31AM +0900, Graeme Gregory wrote:
+
+ palmas_ldo_write(pmic-palmas, palmas_regs_info[id].ctrl_addr, reg);
Could use the core regmap stuff for the LDOs too.
Tony Lindgren t...@atomide.com writes:
* Javier Martinez Canillas jav...@dowhile0.org [120427 02:33]:
On Wed, Apr 25, 2012 at 9:59 AM, Enric Balletbò i Serra
eballe...@gmail.com wrote:
Tony, as this is a fix ,may be included ?
Acked-by: Enric Balletbo i Serra eballe...@gmail.com
From: Mark A. Greer mgr...@animalcreek.com
These patches convert the davinci emac support for the am35x SoC
to use hwmod and add enable_hlt()/disable_hlt() calls to the
pm_runtime hooks for that driver.
I have converted the davinci_emac driver to use pm_runtime but I
can't formally submit it yet
On Tue, May 15, 2012 at 03:48:56PM +0900, Graeme Gregory wrote:
Palmas is a PMIC from Texas Instruments and this is the MFD part of the
driver for this chip. The PMIC has SMPS and LDO regulators, a general
purpose ADC, GPIO, USB OTG mode detection, watchdog and RTC features.
Reviwed-by: Mark
From: Mark A. Greer mgr...@animalcreek.com
Add hwmod support for the EMAC (and MDIO)
ethernet controller that's on the am35x
family of SoC's.
Signed-off-by: Mark A. Greer mgr...@animalcreek.com
---
arch/arm/mach-omap2/am35xx-emac.c | 92 ++--
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs has a Davinci EMAC ethernet
controller on-chip. Unfortunately, the EMAC is unable
to wake the PRCM when there is network activity which
leads to a hung or extremely slow system when the MPU
has executed a 'wfi' instruction
On Tue, May 15, 2012 at 03:48:58PM +0900, Graeme Gregory wrote:
Palmas has both Switched Mode (SMPS) and Linear (LDO) regulators in it.
This regulator driver allows software control of these regulators.
The regulators available on Palmas series chips vary depending on the muxing.
This is
On Tue, May 15, 2012 at 09:43:52AM +0200, Jean Pihet wrote:
Hi Mark,
Hi Jean.
On Mon, Apr 30, 2012 at 11:26 PM, Mark A. Greer mgr...@animalcreek.com
wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs only support the PWRSTS_ON
state so create a new set of
On Tue, May 15, 2012 at 11:35:27AM -0700, Mark A. Greer wrote:
On Tue, May 15, 2012 at 09:43:52AM +0200, Jean Pihet wrote:
Hi Mark,
Hi Jean.
On Mon, Apr 30, 2012 at 11:26 PM, Mark A. Greer mgr...@animalcreek.com
wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x
On Wed, May 9, 2012 at 4:40 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, May 09, 2012 at 03:44:08PM -0500, Buckley, Bryan wrote:
On Wed, May 9, 2012 at 10:48 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, May 09, 2012 at 06:00:10PM +0530,
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs only support the PWRSTS_ON
state so create a new set of powerdomain structures
that ensure that only the ON state is entered.
Signed-off-by: Mark A. Greer mgr...@animalcreek.com
---
This patch has been reworked as per Jean
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
Remove the FIXME's in the suspend sequence since
we now intend to support system level RET support.
minor: this should probably go at the end of the series, after retention
is supported. Otherwise, ending up with only
* Kevin Hilman khil...@ti.com [120515 11:17]:
Tony Lindgren t...@atomide.com writes:
* Javier Martinez Canillas jav...@dowhile0.org [120427 02:33]:
On Wed, Apr 25, 2012 at 9:59 AM, Enric Balletbò i Serra
eballe...@gmail.com wrote:
Tony, as this is a fix ,may be included ?
* Stephen Warren swar...@wwwdotorg.org [120514 11:42]:
On 05/12/2012 05:49 PM, Linus Walleij wrote:
On Thu, May 10, 2012 at 7:05 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
Also, were you intending pinctrl-simple to actually be the GPIO
controller itself? That'd be another case
Tony Lindgren t...@atomide.com writes:
[...]
That's already merged as 8259573b (ARM: OMAP2+: nand: Make
board_onenand_init()
visible to board code) so we need to apply it as a fix.
Can you do a fix with your Signed-off-by or at least reply with that
so I can apply it?
Here you go.
* Felipe Balbi ba...@ti.com [120514 12:41]:
On Mon, May 14, 2012 at 11:37:43AM -0700, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [120514 11:19]:
* Felipe Balbi ba...@ti.com [120514 11:04]:
That whole MMC card detection is also pretty screwed up. Balaji/Venkat,
can you
* Kevin Hilman khil...@ti.com [120515 13:17]:
Tony Lindgren t...@atomide.com writes:
[...]
That's already merged as 8259573b (ARM: OMAP2+: nand: Make
board_onenand_init()
visible to board code) so we need to apply it as a fix.
Can you do a fix with your Signed-off-by or at least
Use omap_disable_channel_irq() function instead of directly accessing CICR.
The omap_disable_chanel_irq() function clears pending interrupts
and disables interrupt on channel.
Functions omap2_enable_irq_lch()/omap2_disable_irq_lch() clear interrupt
status register.
Signed-off-by: Oleg Matcovschi
Cousson, Benoit b-cous...@ti.com writes:
On 4/24/2012 4:46 PM, Tero Kristo wrote:
On Mon, 2012-04-23 at 10:52 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:19 AM, Tero Kristo wrote:
From: Rajendra Nayakrna...@ti.com
On OMAP4 most modules/hwmods support module level context status. On
Tero Kristo t-kri...@ti.com writes:
On OMAP4, there is no support to read previous logic state
or previous memory state achieved when a power domain transitions
to RET. Instead there are module level context registers.
In order to support the powerdomain level logic/mem_off_counters
on
Tero Kristo t-kri...@ti.com writes:
PM debug now contains a file that can be used to control OSWR support
enable / disable on OMAP4. Also removed the off_mode_enable file for
the same platform as it is unsupported.
Signed-off-by: Tero Kristo t-kri...@ti.com
I'll gladly take a patch that
From: Jon Hunter jon-hun...@ti.com
In order to migrate the dmtimer driver to support device-tree I found that it
was first necessary to clean-up the timer platform data. The goal of this
series is to simplify the timer platform data structure from ...
struct dmtimer_platform_data {
int
From: Jon Hunter jon-hun...@ti.com
In the plat/dmtimer.h there is a structure named clk declared. This structure
is not used and appears to be left over from previous code. Hence, remove this
unused structure.
Verified that both omap1 and omap2plus kernel configurations build with this
change.
From: Jon Hunter jon-hun...@ti.com
The OMAP2+ timer code has a definition for the maximum number of timers that
OMAP2+ devices have. This defintion is not used anywhere in the code and
appears to be left over. Furthermore the definition is not accurate for OMAP4
devices that only have 11 timers
From: Jon Hunter jon-hun...@ti.com
During early boot, two timers are reserved by the kernel as system timers (for
clocksource and clockevents). These timers are marked as reserved and the
dmtimer driver is notified which timers have been reserved via the platform
data information.
For OMAP2+
From: Jon Hunter jon-hun...@ti.com
Although the OMAP timers share a common hardware design, there are some
differences between the timer instances in a given device. For example, a timer
maybe in a power domain that can be powered-of, so can lose its logic state and
need restoring where as
From: Jon Hunter jon-hun...@ti.com
Fix the following issues with the timer device attributes for OMAP2+ devices:
1. For OMAP24xx devices, timers 2-8 have the ALWAYS-ON attribute indicating
that these timers are in an ALWAYS-ON power domain. This is not the case
only timer1 is in an
From: Jon Hunter jon-hun...@ti.com
The platform data variable loses_context is used to determine if the timer may
lose its logic state during power transitions and so needs to be restored. This
information is also provided in the HWMOD device attributes for OMAP2+ devices
via the OMAP_TIMER_ALWON
From: Jon Hunter jon-hun...@ti.com
For OMAP2+ devices, a function pointer that returns the number of times a timer
power domain has lost context is passed to the dmtimer driver. This function
pointer is only populated for OMAP2+ devices and it is pointing to a platform
function. Given that this
From: Jon Hunter jon-hun...@ti.com
For OMAP1 devices, it is necessary to perform a manual reset of the timer.
Currently, this is indicating by setting the needs_manual_reset variable in
the platform data. Instead of using an extra variable to indicate this add a new
timer capabilities flag to
From: Jon Hunter jon-hun...@ti.com
Currently, the dmtimer determines whether an timer can support an external
clock source (sys_altclk) for driving the timer by the IP version. Only
OMAP24xx devices can support an external clock source, but the IP version
between OMAP24xx and OMAP3xxx is common
Hi Jassi,
On 05/12/2012 08:40 AM, Jassi Brar wrote:
On 12 May 2012 05:21, Stephen Warren swar...@wwwdotorg.org wrote:
On 05/11/2012 03:06 PM, Jassi Brar wrote:
On 12 May 2012 00:58, Stephen Warren swar...@wwwdotorg.org wrote:
On 05/10/2012 01:59 PM, Jassi Brar wrote:
...
client0: i2s {
Hi Jassi,
On 05/04/2012 02:01 PM, Jassi Brar wrote:
On 4 May 2012 20:47, Jon Hunter jon-hun...@ti.com wrote:
Hi Jassi,
On 05/04/2012 01:56 AM, Jassi Brar wrote:
On 1 May 2012 02:47, Jon Hunter jon-hun...@ti.com wrote:
From: Jon Hunter jon-hun...@ti.com
This is based upon the work by
On 2 May 2012 21:11, Omar Ramirez Luna omar.l...@linaro.org wrote:
Recently a patch went in for tidspbridge code, to ioremap
SCM registers and solve a build break[1]. However it has
been pointed out before that this is a layer violation
given that control module should handle its own
On Wednesday 16 May 2012 03:52 AM, Kevin Hilman wrote:
Cousson, Benoitb-cous...@ti.com writes:
On 4/24/2012 4:46 PM, Tero Kristo wrote:
On Mon, 2012-04-23 at 10:52 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:19 AM, Tero Kristo wrote:
From: Rajendra Nayakrna...@ti.com
On OMAP4 most
On Wednesday 16 May 2012 10:54 AM, Rajendra Nayak wrote:
On Wednesday 16 May 2012 03:52 AM, Kevin Hilman wrote:
Cousson, Benoitb-cous...@ti.com writes:
On 4/24/2012 4:46 PM, Tero Kristo wrote:
On Mon, 2012-04-23 at 10:52 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:19 AM, Tero Kristo
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