Re: [PATCH v5 00/11] ARM: OMAP2+: AM43x PRCM basic support
On Tuesday 01 October 2013 12:34 PM, Afzal Mohammed wrote: Hi Paul, Benoit, Tony, This series adds PRCM support (except clock tree) for AM43x SoC's. Please consider this for inclusion in the coming merge window. Patch 02/11 ARM: OMAP2+: hwmod: AM335x/AM43x: move common data may not reach mailing lists due to bigger size, this series is also present @git://gitorious.org/x0148406-public/linux-kernel.git tags/am43x-prcm-v5 Compared to v4, only change is in fixing the powerdomain data. Major changes compared to rfc v3: 1. All register offsets properly taken care for AM43x (with rfc v3, a couple of issues was detected while testing on pre-silicon) 2. There were two patches for common hwmod data movement (one for interconnect and other for ip block data), both were combined to have a cleaner series that is bisectable. 3. Cleaner seperation of common data Major changes compared to v2 (v3 was only an rfc for current approach): 1. omap_hwmod_33xx_43xx_interconnect_data.c has the common interconnect ocp's structs shared between AM335x and AM43x 2. omap_hwmod_33xx_43xx_ipblock_data.c has the common hwmod structs shared between AM335x and AM43x This split and reuse looks much better and readable now. For the complete series, Acked-by: Rajendra Nayak rna...@ti.com 3. Instances where clock domain or clock topology has changed in the few cases, have separate structures for AM335x and AM43x 4. To handle scenarios where register offsets are different, they are dynamically init-ed in omap_hwmod_33xx_43xx_ipblock_data.c 5. Register offsets for hwmod's that are present either in AM335x or AM43x are updated statically in omap_hwmod_33xx_data.c or omap_hwmod_43xx_data.c as that was cleaner. 6. Remove the change that re-introduces SW_SLEEP for OMAP4, this will be taken care separately. This series has been boot tested on pre-silicon platform with the help of Tero's DT clock tree conversion series. This series has been tested on AM335x-EVM too. Additional details: AM43x reuses most of the IP's from AM335x, as that is the case, much of the AM335x hwmod data is reused. As AM43x PRCM register layout differs from AM335x and is similar to OMAP4, power domain, clock domain hwmod operations are reused from OMAP4. Currently there is no public TRM available for AM43x. Changes based on: v3.12-rc2 Regards Afzal Afzal Mohammed (7): ARM: OMAP2+: hwmod: AM335x/AM43x: move common data ARM: OMAP2+: hwmod: AM335x: runtime register update ARM: OMAP2+: hwmod: AM335x: remove static register offs ARM: OMAP2+: PRCM: AM43x definitions ARM: OMAP2+: hwmod: AM43x support ARM: OMAP2+: hwmod: AM43x operations ARM: OMAP2+: AM43x: PRCM kbuild Ambresh K (3): ARM: OMAP2+: PM: AM43x powerdomain data ARM: OMAP2+: CM: AM43x clockdomain data ARM: OMAP2+: AM43x PRCM init Ankur Kishore (1): ARM: OMAP2+: CM: cm_inst offset s16-u16 arch/arm/mach-omap2/Makefile |9 +- arch/arm/mach-omap2/clockdomain.h |4 +- arch/arm/mach-omap2/clockdomains43xx_data.c| 196 ++ arch/arm/mach-omap2/cm33xx.c | 16 +- arch/arm/mach-omap2/cm33xx.h | 12 +- arch/arm/mach-omap2/cminst44xx.c | 29 +- arch/arm/mach-omap2/cminst44xx.h | 26 +- arch/arm/mach-omap2/io.c |6 + arch/arm/mach-omap2/omap_hwmod.c |8 + arch/arm/mach-omap2/omap_hwmod.h |1 + .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 163 ++ .../omap_hwmod_33xx_43xx_interconnect_data.c | 643 +++ .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 1456 +++ arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1966 +--- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 622 +++ arch/arm/mach-omap2/powerdomain.h |1 + arch/arm/mach-omap2/powerdomains43xx_data.c| 136 ++ arch/arm/mach-omap2/prcm43xx.h | 141 ++ 18 files changed, 3432 insertions(+), 2003 deletions(-) create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c create mode 100644 arch/arm/mach-omap2/omap_hwmod_43xx_data.c create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c create mode 100644 arch/arm/mach-omap2/prcm43xx.h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3] Add support for Newflow NanoBone board
On 25/09/13 09:04, Mark Jackson wrote: NanoBone Specification: --- CPU: TI AM335x Memory: 256MB DDR3 128MB NOR flash 128KB FRAM Ethernet: 2 x 10/100 connected to SMSC LAN8710 PHY USB: 1 x USB2.0 Type A I2C: 2Kbit EEPROM (Microchip 24AA02) RTC (Maxim DS1338) GPIO Expander (Microchip MCP23017) Expansion connector: 6 x UART 1 x MMC/SD 1 x USB2.0 Signed-off-by: Mark Jackson m...@newflow.co.uk Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk snip Any chance someone could accept / comment on this patch ? Cheers Mark J. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3] Add support for Newflow NanoBone board
NanoBone Specification:
---
CPU:
TI AM335x
Memory:
256MB DDR3
128MB NOR flash
128KB FRAM
Ethernet:
2 x 10/100 connected to SMSC LAN8710 PHY
USB:
1 x USB2.0 Type A
I2C:
2Kbit EEPROM (Microchip 24AA02)
RTC (Maxim DS1338)
GPIO Expander (Microchip MCP23017)
Expansion connector:
6 x UART
1 x MMC/SD
1 x USB2.0
Signed-off-by: Mark Jackson m...@newflow.co.uk
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes in v3:
- Added MMC support
- Fixed regulator limits
Changes in v2:
- Reworked to use existing device nodes as suggested by Javier
MAINTAINERS |6 +
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/am335x-nano.dts | 431 +
3 files changed, 438 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-nano.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index e61c2e8..8a4c9d9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6062,6 +6062,12 @@ L: linux-omap@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-omap.c
+OMAP/NEWFLOW NANOBONE MACHINE SUPPORT
+M: Mark Jackson m...@newflow.co.uk
+L: linux-omap@vger.kernel.org
+S: Maintained
+F: arch/arm/boot/dts/am335x-nano.dts
+
OMFS FILESYSTEM
M: Bob Copeland m...@bobcopeland.com
L: linux-karma-de...@lists.sourceforge.net
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e95af3f..543e837 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -184,6 +184,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
am335x-evmsk.dtb \
am335x-bone.dtb \
am335x-boneblack.dtb \
+ am335x-nano.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
am43x-epos-evm.dtb
diff --git a/arch/arm/boot/dts/am335x-nano.dts
b/arch/arm/boot/dts/am335x-nano.dts
new file mode 100644
index 000..9907b49
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -0,0 +1,431 @@
+/*
+ * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include am33xx.dtsi
+
+/ {
+ model = Newflow AM335x NanoBone;
+ compatible = ti,am33xx;
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = dcdc2_reg;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x8000 0x1000; /* 256 MB */
+ };
+
+ leds {
+ compatible = gpio-leds;
+
+ led@0 {
+ label = nanobone:green:usr1;
+ gpios = gpio1 5 0;
+ default-state = off;
+ };
+ };
+};
+
+am33xx_pinmux {
+ pinctrl-names = default;
+ pinctrl-0 = misc_pins;
+
+ misc_pins: misc_pins {
+ pinctrl-single,pins =
+ 0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
+ ;
+ };
+
+ gpmc_pins: gpmc_pins {
+ pinctrl-single,pins =
+ 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad7.gpmc_ad7 */
+ 0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad8.gpmc_ad8 */
+ 0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad9.gpmc_ad9 */
+ 0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad10.gpmc_ad10 */
+ 0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad11.gpmc_ad11 */
+ 0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad12.gpmc_ad12 */
+ 0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad13.gpmc_ad13 */
+ 0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad14.gpmc_ad14 */
+ 0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_ad15.gpmc_ad15 */
+
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x80 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn1.gpmc_csn1 */
+ 0x84 (PIN_OUTPUT | MUX_MODE0)
Re: [PATCH] ARM: DTS: DRA7: Add TPS659038 PMIC nodes
Hi Benoit,
Thanks a lot for fixing it.
On Thursday 03 October 2013 07:09 PM, Benoit Cousson wrote:
Hi Keerthy,
On 11/09/2013 07:30, Keerthy wrote:
On Tuesday 10 September 2013 12:51 AM, Nishanth Menon wrote:
On 08/26/2013 12:36 AM, Keerthy wrote:
The Patch adds nodes for TPS659038 PMIC for DRA7 boards.
It is based on top of:
http://comments.gmane.org/gmane.linux.ports.arm.omap/102459.
Documentation:Documentation/devicetree/bindings/mfd/palmas.txt
Documentation/devicetree/bindings/regulator/palmas-pmic.txt
Boot Tested on DRA7 d1 Board.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 118
1 file changed, 118 insertions(+)
Index: linux/arch/arm/boot/dts/dra7-evm.dts
===
--- linux.orig/arch/arm/boot/dts/dra7-evm.dts2013-08-26
09:57:52.496173554 +0530
+++ linux/arch/arm/boot/dts/dra7-evm.dts2013-08-26
10:38:44.995414695 +0530
@@ -93,6 +93,119 @@
pinctrl-names = default;
pinctrl-0 = i2c1_pins;
clock-frequency = 40;
+
+tps659038: tps659038@58 {
+compatible = ti,tps659038;
+reg = 0x58;
+
+tps659038_pmic {
+compatible = ti,tps659038-pmic;
+
+regulators {
+smps123_reg: smps123 {
+/* VDD_MPU */
+regulator-name = smps123;
+regulator-min-microvolt = 85;
+regulator-max-microvolt = 125;
+regulator-always-on;
+regulator-boot-on;
+};
+
+smps45_reg: smps45 {
+/* VDD_DSPEVE */
+regulator-name = smps45;
+regulator-min-microvolt = 85;
+regulator-max-microvolt = 115;
+regulator-boot-on;
+};
+
+smps6_reg: smps6 {
+/* VDD_GPU - over VDD_SMPS6 */
+regulator-name = smps6;
+regulator-min-microvolt = 85;
+regulator-max-microvolt = 1250;
+regulator-boot-on;
+};
+
+smps7_reg: smps7 {
+/* CORE_VDD */
+regulator-name = smps7;
+regulator-min-microvolt = 85;
+regulator-max-microvolt = 103;
+regulator-always-on;
+regulator-boot-on;
+};
+
+smps8_reg: smps8 {
+/* VDD_IVAHD */
+regulator-name = smps8;
+regulator-min-microvolt = 85;
+regulator-max-microvolt = 125;
+regulator-boot-on;
+};
+
+smps9_reg: smps9 {
+/* VDDS1V8 */
+regulator-name = smps9;
+regulator-min-microvolt = 180;
+regulator-max-microvolt = 180;
+regulator-always-on;
+regulator-boot-on;
+};
+
+ldo1_reg: ldo1 {
+/* LDO1_OUT -- SDIO */
+regulator-name = ldo1;
+regulator-min-microvolt = 180;
+regulator-max-microvolt = 330;
+regulator-boot-on;
+};
+
+ldo2_reg: ldo2 {
+/* VDD_RTCIO */
+/* LDO2 - VDDSHV5, LDO2 also goes to
CAN_PHY_3V3 */
+regulator-name = ldo2;
+regulator-min-microvolt = 330;
+regulator-max-microvolt = 330;
+regulator-boot-on;
+};
+
+ldo3_reg: ldo3 {
+/* VDDA_1V8_PHY */
+regulator-name = ldo3;
+regulator-min-microvolt = 180;
+regulator-max-microvolt = 180;
+regulator-boot-on;
+};
+
+ldo9_reg: ldo9 {
+/* VDD_RTC */
+regulator-name = ldo9;
+regulator-min-microvolt = 105;
+regulator-max-microvolt = 105;
+regulator-boot-on;
+};
+
+ldoln_reg: ldoln {
+/* VDDA_1V8_PLL */
+regulator-name = ldoln;
+regulator-min-microvolt = 180;
+regulator-max-microvolt = 180;
+regulator-always-on;
+
Re: [PATCH v7 09/10] usb: dwc3: omap: manage usb_otg_ss_refclk960m clock
Greg, On 10/03/2013 06:41 PM, Greg KH wrote: On Thu, Oct 03, 2013 at 05:54:14PM +0300, Roger Quadros wrote: On 10/03/2013 03:29 PM, Felipe Balbi wrote: Hi, On Wed, Oct 02, 2013 at 04:41:53PM +0300, Roger Quadros wrote: On 10/02/2013 04:11 PM, Felipe Balbi wrote: On Mon, Sep 23, 2013 at 04:11:30PM +0300, Roger Quadros wrote: Hi Felipe, On 09/18/2013 03:49 PM, Roger Quadros wrote: usb_otg_ss_refclk960m is an optional functional clock to the UBS_OTG_SS module. So manage it in the driver. Just realized that usb_otg_ss_refclk960m is in fact functional clock to the PHY and not USB_OTG_SS module. The name is misleading. So please ignore patch 9 and 10. ignored. All others are fine, right ? Yes. But I might have to rebase this on top of Phy framework stuff. alright, Greg already took the PHY framework, so maybe we need to just give him my Acked-by and he takes the patches directly as I don't have PYH framework. OK. I'll resend this series to Greg in a while. It looks like you did, but forgot Felipe's ack :( I was under the impression that Felipe will explicitly give his Ack there. Should I resend with his Acked-bys? cheers, -roger -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 0/2] ARM: dts: Add initial support for IGEP AQUILA
Hi Enric, On 03/10/2013 20:17, Tony Lindgren wrote: * Javier Martinez Canillas martinez.jav...@gmail.com [130925 06:18]: On Tue, Sep 10, 2013 at 4:55 PM, Enric Balletbo i Serra eballe...@gmail.com wrote: From: Enric Balletbo i Serra eballe...@iseebcn.com Hi all, These two patches introduces initial support for the IGEP AM335x-based platforms. The first patch add support for IGEP COM AQUILA products, and the second patch add support for the development board. These patches apply on top of bcousson/for_3.12/dts repository. Changes since v2: * Make it compatible with isee,am335x-base0033, isee,am335x-igep0033, ti,am33xx since these boards are manufactured by ISEE not TI. (Javier) Changes since v1: * Use node to reference the nodes already defined in dtsi files. (Javier) Best regards, Enric Balletbo i Serra (2): ARM: dts: AM33XX: Add support for IGEP COM AQUILA ARM: dts: AM33XX: Add support for IGEP AQUILA EXPANSION board. arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-base0033.dts | 16 ++ arch/arm/boot/dts/am335x-igep0033.dtsi | 265 + 3 files changed, 282 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-base0033.dts create mode 100644 arch/arm/boot/dts/am335x-igep0033.dtsi -- 1.8.1.2 Hi Benoit and Tony, Any comments on this series? I had already reviewed previous versions of the DT and it looks good to me now. It would be great if this can make it for 3.13. Looks good to me, I would assume Benoit will be looking at this shortly. I did :-) It looks good to me too, I've just fixed a conflict with my current branch in the Makefile and fix a typo in the header: +++ b/arch/arm/boot/dts/am335x-base0033.dts @@ -0,0 +1,16 @@ +/* + * am335x-base0033.dtsi - Device Tree file for IGEP AQUILA EXPANSION Should be am335x-base0033.dts. I fixed it for you. Please check if the fix is ok in the branch. Pushed on my for_3.13/dts branch. Thanks, Benoit -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: dts: am335x-bone-common: correct mux mode for cmd line
Hi Balaji,
On 27/09/2013 13:35, Balaji T K wrote:
pinmux_emmc_pins: mux mode for cmd line should be MODE2
to detect eMMC on beagle bone black and beagle bone white + eMMC cape.
Signed-off-by: Balaji T K balaj...@ti.com
Tested-by: Felipe Balbi ba...@ti.com
---
based on
git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
for_3.13/dts
arch/arm/boot/dts/am335x-bone-common.dtsi |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi
b/arch/arm/boot/dts/am335x-bone-common.dtsi
index ff5c3ca..51f6a99 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -153,7 +153,7 @@
emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins =
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /*
gpmc_csn1.mmc1_clk */
- 0x84 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_csn2.mmc1_cmd */
+ 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /*
gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_ad2.mmc1_dat2 */
Thanks, I'll apply it for 3.13.
Regards,
Benoit
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Re: [PATCH 2/2] ARM: dts: am335x-evm, am335x-evmsdk: switch mmc1 to 4-bit mode
Hi Balaji,
On 27/09/2013 13:35, Balaji T K wrote:
set bus-width to make SD card operate in 4 bit mode.
Signed-off-by: Balaji T K balaj...@ti.com
---
based on
git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
for_3.13/dts
arch/arm/boot/dts/am335x-evm.dts |1 +
arch/arm/boot/dts/am335x-evmsk.dts |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 23b0a3e..028ca09 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -521,4 +521,5 @@
mmc1 {
status = okay;
vmmc-supply = vmmc_reg;
+ bus-width = 4;
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index bc93895..563a2b1 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -423,4 +423,5 @@
mmc1 {
status = okay;
vmmc-supply = vmmc_reg;
+ bus-width = 4;
};
Thanks, I'll apply it for 3.13.
Regards,
Benoit
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Re: [PATCH v7 09/10] usb: dwc3: omap: manage usb_otg_ss_refclk960m clock
On Fri, Oct 04, 2013 at 01:46:08PM +0300, Roger Quadros wrote: Greg, On 10/03/2013 06:41 PM, Greg KH wrote: On Thu, Oct 03, 2013 at 05:54:14PM +0300, Roger Quadros wrote: On 10/03/2013 03:29 PM, Felipe Balbi wrote: Hi, On Wed, Oct 02, 2013 at 04:41:53PM +0300, Roger Quadros wrote: On 10/02/2013 04:11 PM, Felipe Balbi wrote: On Mon, Sep 23, 2013 at 04:11:30PM +0300, Roger Quadros wrote: Hi Felipe, On 09/18/2013 03:49 PM, Roger Quadros wrote: usb_otg_ss_refclk960m is an optional functional clock to the UBS_OTG_SS module. So manage it in the driver. Just realized that usb_otg_ss_refclk960m is in fact functional clock to the PHY and not USB_OTG_SS module. The name is misleading. So please ignore patch 9 and 10. ignored. All others are fine, right ? Yes. But I might have to rebase this on top of Phy framework stuff. alright, Greg already took the PHY framework, so maybe we need to just give him my Acked-by and he takes the patches directly as I don't have PYH framework. OK. I'll resend this series to Greg in a while. It looks like you did, but forgot Felipe's ack :( I was under the impression that Felipe will explicitly give his Ack there. Should I resend with his Acked-bys? No need, I took the patches yesterday, you should have seen the automated emails, right? greg k-h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/9] ARM: dts: DT data for OMAP platforms for v3.13
On 04/10/2013 04:00, Joel Fernandes wrote: On 10/03/2013 08:25 AM, Benoit Cousson wrote: + DT list and DT maintainers. Hi Joel, Thanks for the update. It looks good to me. For the new bindings added below; .../devicetree/bindings/crypto/omap-aes.txt| 34 ++ .../devicetree/bindings/crypto/omap-sham.txt | 31 + I will need the acked-by from one of the DT maintainers. Sure. To help with giving Ack for this, I'd like to also mention these patches were due for long time and reposted. The supporting code is already in the kernel. Also bindings were reviewed by Mark Rutland comments in the following thread were addressed: http://www.spinics.net/lists/arm-kernel/msg269006.html OK, that's good news, at least it was already reviewed by Mark. I'm fixing and pulling the series, and will add Mark's Acked-by as soon as he will send it. Meanwhile some nits, I'm fixing myself this time :-) None of your subjects is following the same guideline and the repertory guideline... omap4: dts: Add node for AES omap4: dts: Add node for DES3DES module am33xx: dts: Fix AES interrupt number ARM: am437x: dts: Add AES node for am437x ARM: am437x: dts: Add DES node for am437x It should be ARM: dts: OMAPXXX or AMXXX... Regards, Benoit -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/9] ARM: dts: Add SHAM data and documentation for AM33XX
On Mon, Sep 30, 2013 at 04:13:00PM +0100, Joel Fernandes wrote:
From: Mark A. Greer mgr...@animalcreek.com
Add the generic AM33XX SHAM module's device tree data and
enable it for the am335x-evm, am335x-evmsk, and am335x-bone
platforms. Also add Documentation file describing the data
for the SHAM module.
[jo...@ti.com: Dropped interrupt-parrent property]
CC: Paul Walmsley p...@pwsan.com
Signed-off-by: Mark A. Greer mgr...@animalcreek.com
---
.../devicetree/bindings/crypto/omap-sham.txt | 31
++
arch/arm/boot/dts/am335x-bone.dts | 4 +++
arch/arm/boot/dts/am335x-evm.dts | 4 +++
arch/arm/boot/dts/am335x-evmsk.dts | 4 +++
arch/arm/boot/dts/am33xx.dtsi | 9 +++
5 files changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/omap-sham.txt
diff --git a/Documentation/devicetree/bindings/crypto/omap-sham.txt
b/Documentation/devicetree/bindings/crypto/omap-sham.txt
new file mode 100644
index 000..b97710f
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/omap-sham.txt
@@ -0,0 +1,31 @@
+OMAP SoC SHA crypto Module
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SHAM versions:
+ - ti,omap2-sham for OMAP2 OMAP3.
+ - ti,omap4-sham for OMAP4 and AM33XX.
+ Note that these two versions are incompatible.
+- ti,hwmods: Name of the hwmod associated with the SHAM module
+- reg : Offset and length of the register set for the module
+- interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this module.
I don't think this is strictly speaking necessary -- it's mostly going
to be implicit (it is in the dtsi below). As this is a standard
property, you don't need to document it here.
+- interrupts : the interrupt number for the SHAM module.
Sorry, I missed this last time, but this should be interrupt-specifier
rather than interrupt number.
Otherwise, this looks good to me. With the fixups above:
Acked-by: Mark Rutland mark.rutl...@arm.com
+
+Optional properties:
+- dmas: DMA specifier for the rx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request name. Should be rx if a dma is present.
+
+Example:
+ /* AM335x */
+ sham: sham@5310 {
+ compatible = ti,omap4-sham;
+ ti,hwmods = sham;
+ reg = 0x5310 0x200;
+ interrupt-parent = intc;
+ interrupts = 109;
+ dmas = edma 36;
+ dma-names = rx;
+ };
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 0d63348..8a9802e 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -19,3 +19,7 @@
mmc1 {
vmmc-supply = ldo3_reg;
};
+
+sham {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts
b/arch/arm/boot/dts/am335x-evm.dts
index 23b0a3e..d59e51c 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -522,3 +522,7 @@
status = okay;
vmmc-supply = vmmc_reg;
};
+
+sham {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index bc93895..d45a330 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -424,3 +424,7 @@
status = okay;
vmmc-supply = vmmc_reg;
};
+
+sham {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 553adc6..299710b 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -710,5 +710,14 @@
#size-cells = 1;
status = disabled;
};
+
+ sham: sham@5310 {
+ compatible = ti,omap4-sham;
+ ti,hwmods = sham;
+ reg = 0x5310 0x200;
+ interrupts = 109;
+ dmas = edma 36;
+ dma-names = rx;
+ };
};
};
--
1.8.1.2
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Re: [PATCH v2 5/9] am33xx: dts: Fix AES interrupt number
On 30/09/2013 17:13, Joel Fernandes wrote: Signed-off-by: Joel Fernandes jo...@ti.com Even if this is obvious, a small changelog is always recommended. Thanks, Benoit --- arch/arm/boot/dts/am33xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 0daa1b2..d7be90a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -724,7 +724,7 @@ compatible = ti,omap4-aes; ti,hwmods = aes; reg = 0x5350 0xa0; - interrupts = 102; + interrupts = 103; dmas = edma 6 edma 5; dma-names = tx, rx; -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 1/3] usb: dwc3: msm: Add device tree binding information
On Wed, Aug 21, 2013 at 04:29:44PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys (SNPS) and HS, SS PHY's control and configuration registers. It could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com these patches were sent *ages* and nobody from DT mailing list has reviewed. Unless someone steps up now, I'll be queueing these patches next week. -- balbi signature.asc Description: Digital signature
Re: [PATCH v2 4/9] ARM: dts: Add AES data and documentation for AM33XX
On Mon, Sep 30, 2013 at 04:13:01PM +0100, Joel Fernandes wrote:
From: Mark A. Greer mgr...@animalcreek.com
Add the generic AM33XX AES module's device tree data and
enable it for the am335x-evm, am335x-evmsk, and am335x-bone
platforms. Also add Documentation file describing the data
for the AES module.
[jo...@ti.com: Dropped interrupt-parent propert]
CC: Paul Walmsley p...@pwsan.com
Signed-off-by: Mark A. Greer mgr...@animalcreek.com
---
.../devicetree/bindings/crypto/omap-aes.txt| 34
++
arch/arm/boot/dts/am335x-bone.dts | 4 +++
arch/arm/boot/dts/am335x-evm.dts | 4 +++
arch/arm/boot/dts/am335x-evmsk.dts | 4 +++
arch/arm/boot/dts/am33xx.dtsi | 10 +++
5 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/omap-aes.txt
diff --git a/Documentation/devicetree/bindings/crypto/omap-aes.txt
b/Documentation/devicetree/bindings/crypto/omap-aes.txt
new file mode 100644
index 000..4bb1e27
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/omap-aes.txt
@@ -0,0 +1,34 @@
+OMAP SoC AES crypto Module
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ AES versions:
+ - ti,omap2-aes for OMAP2.
+ - ti,omap3-aes for OMAP3.
+ - ti,omap4-aes for OMAP4 and AM33XX.
+ Note that the OMAP2 and 3 versions are compatible (OMAP3 supports
+ more algorithms) but they are incompatible with OMAP4.
+- ti,hwmods: Name of the hwmod associated with the AES odule
+- reg : Offset and length of the register set for the module
+- interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this module.
+- interrupts : the interrupt number for the AES odule.
Similar comments to the SHAM module here:
* s/interrupt number/interrupt-specifier/
* Drop interrupt-parent.
* s/AES odule/AES module/
+
+Optional properties:
+- dmas: DMA specifier for tx and rx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
s/DMA specifier/DMA specifiers/
+- dma-names: DMA request names. Should be 'tx, rx' if dma is present.
Nit: I'd prefer 'Should include tx and rx if present' -- I hope the
driver's requesting these by name rather than relying on a specific
ordering (it makes future expansion and optional components far easier
to handle sanely).
+
+Example:
+ /* AM335x */
+ aes: aes@5350 {
+ compatible = ti,omap4-aes;
+ ti,hwmods = aes;
+ reg = 0x5350 0xa0;
+ interrupt-parent = intc;
+ interrupts = 102;
+ dmas = edma 6
+ edma 5;
+ dma-names = tx, rx;
+ };
Minor nit, but for consistency could you bracket the DMAs individually:
dmas = edma 6,
edma 5;
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 8a9802e..94ee427 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -23,3 +23,7 @@
sham {
status = okay;
};
+
+aes {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts
b/arch/arm/boot/dts/am335x-evm.dts
index d59e51c..86463fa 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -526,3 +526,7 @@
sham {
status = okay;
};
+
+aes {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index d45a330..f577e65 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -428,3 +428,7 @@
sham {
status = okay;
};
+
+aes {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 299710b..0daa1b2 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -719,5 +719,15 @@
dmas = edma 36;
dma-names = rx;
};
+
+ aes: aes@5350 {
+ compatible = ti,omap4-aes;
+ ti,hwmods = aes;
+ reg = 0x5350 0xa0;
+ interrupts = 102;
+ dmas = edma 6
+ edma 5;
Bracketing here too, please.
Cheers,
Mark.
+ dma-names = tx, rx;
+ };
};
};
--
1.8.1.2
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Re: [PATCH v2 0/9] ARM: dts: DT data for OMAP platforms for v3.13
On 10/04/2013 09:10 AM, Benoit Cousson wrote: On 04/10/2013 04:00, Joel Fernandes wrote: On 10/03/2013 08:25 AM, Benoit Cousson wrote: + DT list and DT maintainers. Hi Joel, Thanks for the update. It looks good to me. For the new bindings added below; .../devicetree/bindings/crypto/omap-aes.txt| 34 ++ .../devicetree/bindings/crypto/omap-sham.txt | 31 + I will need the acked-by from one of the DT maintainers. Sure. To help with giving Ack for this, I'd like to also mention these patches were due for long time and reposted. The supporting code is already in the kernel. Also bindings were reviewed by Mark Rutland comments in the following thread were addressed: http://www.spinics.net/lists/arm-kernel/msg269006.html OK, that's good news, at least it was already reviewed by Mark. I'm fixing and pulling the series, and will add Mark's Acked-by as soon as he will send it. Meanwhile some nits, I'm fixing myself this time :-) None of your subjects is following the same guideline and the repertory guideline... omap4: dts: Add node for AES omap4: dts: Add node for DES3DES module am33xx: dts: Fix AES interrupt number ARM: am437x: dts: Add AES node for am437x ARM: am437x: dts: Add DES node for am437x It should be ARM: dts: OMAPXXX or AMXXX... Regards, Benoit On 10/04/2013 09:10 AM, Benoit Cousson wrote: On 04/10/2013 04:00, Joel Fernandes wrote: On 10/03/2013 08:25 AM, Benoit Cousson wrote: + DT list and DT maintainers. Hi Joel, Thanks for the update. It looks good to me. For the new bindings added below; .../devicetree/bindings/crypto/omap-aes.txt| 34 ++ .../devicetree/bindings/crypto/omap-sham.txt | 31 + I will need the acked-by from one of the DT maintainers. Sure. To help with giving Ack for this, I'd like to also mention these patches were due for long time and reposted. The supporting code is already in the kernel. Also bindings were reviewed by Mark Rutland comments in the following thread were addressed: http://www.spinics.net/lists/arm-kernel/msg269006.html OK, that's good news, at least it was already reviewed by Mark. I'm fixing and pulling the series, and will add Mark's Acked-by as soon as he will send it. Meanwhile some nits, I'm fixing myself this time :-) None of your subjects is following the same guideline and the repertory guideline... omap4: dts: Add node for AES omap4: dts: Add node for DES3DES module am33xx: dts: Fix AES interrupt number ARM: am437x: dts: Add AES node for am437x ARM: am437x: dts: Add DES node for am437x It should be ARM: dts: OMAPXXX or AMXXX... Thanks sorry about that. I think Mark came back with some more comments on 2 of those patches. I will work on those and repost. -Joel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv7 00/36] ARM: OMAP: clock data conversion to DT
Hi, Just a gentle reminder, anybody have any comments on this series or should we start queuing stuff? -Tero On 09/25/2013 11:48 AM, Tero Kristo wrote: Hi all, Version 7 contains following high level changes: - Dropped support for basic bindings from Mike Turquette, instead using vendor specific bindings for all clocks - Mux clock + divider clock vendor specific bindings get rid of use of the bit-masks, instead these are generated runtime based on parent clock / divider min/max info, see individual patches for details - Added support for dummy_ck nodes, was missing from previous version - Fixed support for omap3630 - Added support for new clock node type: ti,mux-gate-clock (using composite clock type) - OMAP4 / OMAP5 only build fixes (compiler flag checks added to some files) - most of the of_omap_* calls renamed to of_ti_* - Rebased on top of v3.12-rc2 Some detailed comments about patch level changes (if no mention, no major changes): - Patch #1: * removed use of reg-names property, instead registers mapped using compatible string * removed ti,modes property, instead uses DPLL mode flags now * separated AM33XX DPLLs under their own compatible strings - Patch #4 #5: new patches - Patch #6: merged basic gate support from Mike to this patch as vendor specific gate clock support - Patch #9 #10: new patches - Patch #11: dummy clocks added, USB / ABE DPLL setup ordering changed - Patch #14: dummy clocks added - Patch #20: dropped usage of reg-names property - Patch #21: dummy clocks added - Patch #22 #23: new patches - Patch #30: AM35XX clock data added to this patch - Patch #31: * dummy clocks added * added missing 3630 clocks Test branch available here: https://github.com/t-kristo/linux-pm.git branch: mainline-3.12-rc2-ti-dt-clks-v7 Testing done: - am335x-bone : boot only - omap5-sevm : boot only - dra7-evm : boot only - omap3-beagle : boot + suspend/resume (ret + off) - omap4-panda-es : boot + suspend/resume Nishanth has also been doing some tests with omap3-beagle-xm with some WIP versions of this branch, but not with this latest one. Nishanth, maybe you can provide test results to this one also? -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 0/6] mtd:nand:omap2: clean-up of supported ECC schemes
*Changes v6 - v7* [PATCH 1/6] NEW split from [PATCH v6 2/4] as per feedbacks of Brain Norris [PATCH 2/6] incorporated feedbacks from DT maintainers [PATCH 3/6] patch cleaning and incorporated feedbacks from Brain Norris [PATCH 4/6] rebasing changes and cleanup [PATCH 5/6] updated omap3430-sdp.dts [PATCH 6/6] NEW updated for devm_xx *Changes v5 - v6* [PATCH 1/4]: - updated DT binding for gpmc-nand based on 'Olof Johansson's feedbacks http://lists.infradead.org/pipermail/linux-mtd/2013-August/048394.html - detection of ELM device via ti,elm-id DT node, moved to gpmc.c driver [PATCH 2/4] - removed: support for following obselete ECC schemes OMAP_ECC_HAMMING_CODE_DEFAULT (S/W based 1-bit Hamming ECC) OMAP_ECC_HAMMING_CODE_HW_ROMCODE (H/W based 1-bit Hamming ECC scheme) - updated: using omap_oobinfo as chip-ecc.layout for all ecc-schemes - clean: error messages [PATCH 3/4] cleaned to include changes for OMAP_ECC_BCH8_CODE_HW only [PATCH 4/4] updated to include DT property changes *Changes v4 - v5* - Rebased to linux-next IMPORTANT: Need to revert commit fb1585b, [PATCH 2/4] part of previous version http://lists.infradead.org/pipermail/linux-mtd/2013-July/047441.html - Swapped PATCH-1 PATCH-2 to maintain bisectibility compilation dependency http://lists.infradead.org/pipermail/linux-mtd/2013-July/047461.html - PATCH-2: re-ordered call to is_elm_present() for later updates ELM driver - dropped changes in include/linux/platform_data/elm.h (not needed) - PATCH-3: re-ordered call to is_elm_present() for later updates ELM driver - Re-formated patch description (replaced tabs with white-spaces) *Changes v3 - v4* (Resent with CC: devicetree-disc...@lists.ozlabs.org) - [Patch 1/3] removed MTD_NAND_OMAP_BCH8 MTD_NAND_OMAP_BCH4 from nand/Kconfig ECC scheme selectable via nand DT (nand-ecc-opt). - [*] rebased for l2-mtd.git *Changes v2 - v3* (Resent with Author Name fixed) - PATCH-1: re-arranged code to remove redundancy, added NAND_BUSWIDTH_AUTO - PATCH-2: updated nand-ecc-opt DT mapping and Documentation - PATCH-3: code-cleaning + changes to match PATCH-1 - PATCH-4 DROPPED update DT attribute for ti,nand-ecc-opt - received feedback to keep DT mapping independent of linuxism - PATCH-4:NEW : ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt - independent patch for AM335x-evm.dts update based on PATCH-2 *Changes v1 - v2* added [PATCH 3/4] and [PATCH 4/4] After this patch series, omap2-nand driver will supports following ECC schemes: +---+---+---+ | ECC scheme|ECC calculation|Error detection| +---+---+---+ |OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W| +---+---+---+ |OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.h)| |OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) | +---+---+---+ |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.h)| |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) | +---+---+---+ To optimize footprint of omap2-nand driver, selection of some ECC schemes also require enabling following Kconfigs, in addition to setting appropriate DT bindings - Kconfig:CONFIG_MTD_NAND_ECC_BCHerror detection done in software - Kconfig:CONFIG_MTD_NAND_OMAP_BCH error detection done by h/w engine Pekon Gupta (6): mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes ARM: OMAP2+: cleaned-up DT support of various ECC schemes mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe mtd:nand:omap2: updated support for BCH4 ECC scheme ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt mtd: nand: omap: updated devm_xx for all resource allocation and free calls .../devicetree/bindings/mtd/gpmc-nand.txt | 16 +- arch/arm/boot/dts/am335x-evm.dts | 3 +- arch/arm/boot/dts/omap3430-sdp.dts | 2 +- arch/arm/mach-omap2/board-flash.c | 2 +- arch/arm/mach-omap2/gpmc.c | 49 +- drivers/mtd/nand/Kconfig | 30 +- drivers/mtd/nand/omap2.c | 569 ++--- include/linux/platform_data/mtd-nand-omap2.h | 18 +- 8 files changed, 335 insertions(+), 354 deletions(-) -- 1.8.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 1/6] mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
1-bit hamming ecc code using software library
- OMAP_ECC_HAMMING_CODE_HW
1-bit hamming ecc-code using GPMC h/w engine
- OMAP_ECC_HAMMING_CODE_HW_ROMCODE
1-bit hamming ecc-code using GPMC h/w engin with ecc-layout compatible
to ROM code.
This patch combines above multiple ecc-schemes into single implementation:
- OMAP_ECC_HAM1_CODE_HW
1-bit hamming ecc-code using GPMC h/w engine with ROM-code compatible
ecc-layout.
Signed-off-by: Pekon Gupta pe...@ti.com
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 8
arch/arm/mach-omap2/board-flash.c | 2 +-
arch/arm/mach-omap2/gpmc.c | 4 +---
drivers/mtd/nand/omap2.c| 9 +++--
include/linux/platform_data/mtd-nand-omap2.h| 6 +-
5 files changed, 10 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index df338cb..25ee232 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -22,10 +22,10 @@ Optional properties:
width of 8 is assumed.
- ti,nand-ecc-opt:A string setting the ECC layout to use. One of:
-
- swSoftware method (default)
- hwHardware method
- hw-romcodegpmc hamming mode method romcode layout
+ swdeprecated use ham1 instead
+ hwdeprecated use ham1 instead
+ hw-romcodedeprecated use ham1 instead
+ ham1 1-bit Hamming ecc code
bch4 4-bit BCH ecc code
bch8 8-bit BCH ecc code
diff --git a/arch/arm/mach-omap2/board-flash.c
b/arch/arm/mach-omap2/board-flash.c
index fc20a61..ac82512 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8
nr_parts, u8 cs,
board_nand_data.nr_parts= nr_parts;
board_nand_data.devsize = nand_type;
- board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
+ board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW;
gpmc_nand_init(board_nand_data, gpmc_t);
}
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9f4795a..1c45b72 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1342,9 +1342,7 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
#ifdef CONFIG_MTD_NAND
static const char * const nand_ecc_opts[] = {
- [OMAP_ECC_HAMMING_CODE_DEFAULT] = sw,
- [OMAP_ECC_HAMMING_CODE_HW] = hw,
- [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = hw-romcode,
+ [OMAP_ECC_HAM1_CODE_HW] = ham1,
[OMAP_ECC_BCH4_CODE_HW] = bch4,
[OMAP_ECC_BCH8_CODE_HW] = bch8,
};
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 4ecf0e5..8d521aa 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1993,10 +1993,7 @@ static int omap_nand_probe(struct platform_device *pdev)
}
/* select the ecc type */
- if (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
- info-nand.ecc.mode = NAND_ECC_SOFT;
- else if ((pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
- (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
+ if (pdata-ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
info-nand.ecc.bytes= 3;
info-nand.ecc.size = 512;
info-nand.ecc.strength = 1;
@@ -2025,7 +2022,7 @@ static int omap_nand_probe(struct platform_device *pdev)
}
/* rom code layout */
- if (pdata-ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
+ if (pdata-ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
if (info-nand.options NAND_BUSWIDTH_16)
offset = 2;
@@ -2033,7 +2030,7 @@ static int omap_nand_probe(struct platform_device *pdev)
offset = 1;
info-nand.badblock_pattern = bb_descrip_flashbased;
}
- omap_oobinfo.eccbytes = 3 * (info-mtd.oobsize/16);
+ omap_oobinfo.eccbytes = 3 * (info-mtd.writesize / 512);
for (i = 0; i omap_oobinfo.eccbytes; i++)
omap_oobinfo.eccpos[i] = i+offset;
diff --git a/include/linux/platform_data/mtd-nand-omap2.h
b/include/linux/platform_data/mtd-nand-omap2.h
index 6bf9ef4..cb5a54a 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
[PATCH v7 2/6] ARM: OMAP2+: cleaned-up DT support of various ECC schemes
OMAP NAND driver support multiple ECC scheme, which can used in following
different flavours, depending on in-build Hardware engines supported by SoC.
+---+---+---+
| ECC scheme|ECC calculation|Error detection|
+---+---+---+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W|
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W|
|(requires CONFIG_MTD_NAND_ECC_BCH) | | |
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
|(requires CONFIG_MTD_NAND_OMAP_BCH | | |
| ti,elm-id in DT) | | |
+---+---+---+
To optimize footprint of omap2-nand driver, selection of some ECC schemes
also require enabling following Kconfigs, in addition to setting appropriate
DT bindings
- Kconfig:CONFIG_MTD_NAND_ECC_BCHerror detection done in software
- Kconfig:CONFIG_MTD_NAND_OMAP_BCH error detection done by h/w engine
DT binding updates in this patch are:
- ti,elm-id: replaces elm_id
- ti,nand-ecc-opts: supported values ham1, bch4, and bch8
selection of h/w or s/w implementation depends on ti,elm-id
Signed-off-by: Pekon Gupta pe...@ti.com
---
.../devicetree/bindings/mtd/gpmc-nand.txt | 8 +++-
arch/arm/mach-omap2/gpmc.c | 47 --
include/linux/platform_data/mtd-nand-omap2.h | 14 +--
3 files changed, 52 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index 25ee232..7785666 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -36,8 +36,12 @@ Optional properties:
prefetch-dma Prefetch enabled sDMA mode
prefetch-irq Prefetch enabled irq mode
- - elm_id: Specifies elm device node. This is required to support BCH
- error correction using ELM module.
+ - elm_id: deprecated use ti,elm-id instead
+ - ti,elm-id: Specifies pHandle of the ELM devicetree node.
+ ELM is an on-chip hardware engine on TI SoC which is used for
+ locating ECC errors for BCHx algorithms. SoC devices which have
+ ELM hardware engines should specify this device node in .dtsi
+ Using ELM for ECC error correction frees some CPU cycles.
For inline partiton table parsing (optional):
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1c45b72..5a607fa 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1341,12 +1341,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct
device_node *np,
#ifdef CONFIG_MTD_NAND
-static const char * const nand_ecc_opts[] = {
- [OMAP_ECC_HAM1_CODE_HW] = ham1,
- [OMAP_ECC_BCH4_CODE_HW] = bch4,
- [OMAP_ECC_BCH8_CODE_HW] = bch8,
-};
-
static const char * const nand_xfer_types[] = {
[NAND_OMAP_PREFETCH_POLLED] = prefetch-polled,
[NAND_OMAP_POLLED] = polled,
@@ -1361,6 +1355,8 @@ static int gpmc_probe_nand_child(struct platform_device
*pdev,
const char *s;
struct gpmc_timings gpmc_t;
struct omap_nand_platform_data *gpmc_nand_data;
+ const __be32 *phandle;
+ int lenp;
if (of_property_read_u32(child, reg, val) 0) {
dev_err(pdev-dev, %s has no 'reg' property\n,
@@ -1376,12 +1372,39 @@ static int gpmc_probe_nand_child(struct platform_device
*pdev,
gpmc_nand_data-cs = val;
gpmc_nand_data-of_node = child;
- if (!of_property_read_string(child, ti,nand-ecc-opt, s))
- for (val = 0; val ARRAY_SIZE(nand_ecc_opts); val++)
- if (!strcasecmp(s, nand_ecc_opts[val])) {
- gpmc_nand_data-ecc_opt = val;
- break;
- }
+ /* Detect availability of ELM module */
+ phandle = of_get_property(child, ti,elm-id, lenp);
+ if ((phandle == NULL) || (lenp != sizeof(void *))) {
+ pr_warn(%s: ti,elm-id property not found\n, __func__);
+ gpmc_nand_data-elm_of_node = NULL;
+ } else {
+ gpmc_nand_data-elm_of_node =
+ of_find_node_by_phandle(be32_to_cpup(phandle));
+ }
+ /* select NAND ecc-opt */
+ if (of_property_read_string(child, ti,nand-ecc-opt, s)) {
+ pr_err(%s:
[PATCH v7 5/6] ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt
DT property values for OMAP based gpmc-nand have been updated
to match changes in commit:
6faf096 ARM: OMAP2+: cleaned-up DT support of various ECC schemes
Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 3 +--
arch/arm/boot/dts/omap3430-sdp.dts | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index e8ec875..1aee6ac 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -269,7 +269,6 @@
reg = 0 0 0; /* CS0, offset 0 */
nand-bus-width = 8;
ti,nand-ecc-opt = bch8;
- gpmc,device-nand = true;
gpmc,device-width = 1;
gpmc,sync-clk-ps = 0;
gpmc,cs-on-ns = 0;
@@ -296,7 +295,7 @@
#address-cells = 1;
#size-cells = 1;
- elm_id = elm;
+ ti,elm-id = elm;
/* MTD partition table */
partition@0 {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts
b/arch/arm/boot/dts/omap3430-sdp.dts
index e2249bc..501f863 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -105,7 +105,7 @@
reg = 1 0 0x0800;
nand-bus-width = 8;
- ti,nand-ecc-opt = sw;
+ ti,nand-ecc-opt = ham1;
gpmc,cs-on-ns = 0;
gpmc,cs-rd-off-ns = 36;
gpmc,cs-wr-off-ns = 36;
--
1.8.1
--
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[PATCH v7 4/6] mtd:nand:omap2: updated support for BCH4 ECC scheme
This patch adds following two flavours of BCH4 ECC scheme in omap2-nand driver
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
- uses GPMC H/W engine for calculating ECC.
- uses software library (lib/bch.h nand_bch.h) for error correction.
- OMAP_ECC_BCH4_CODE_HW
- uses GPMC H/W engine for calculating ECC.
- uses ELM H/W engine for error correction.
With this patch omap2-nand driver supports following ECC schemes:
+---+---+---+
| ECC scheme|ECC calculation|Error detection|
+---+---+---+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W|
+---+---+---+
|OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.h)|
|OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) |
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.h)|
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
+---+---+---+
Important:
- Selection of OMAP_ECC_BCHx_CODE_HW_DETECTION_SW requires,
Kconfig: CONFIG_MTD_NAND_ECC_BCH: enables S/W based BCH ECC algorithm.
- Selection of OMAP_ECC_BCHx_CODE_HW requires,
Kconfig: CONFIG_MTD_NAND_OMAP_BCH: enables ELM H/W module.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/Kconfig | 30 ++-
drivers/mtd/nand/omap2.c | 134 +--
2 files changed, 63 insertions(+), 101 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index d885298..5836039 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -96,35 +96,13 @@ config MTD_NAND_OMAP2
config MTD_NAND_OMAP_BCH
depends on MTD_NAND MTD_NAND_OMAP2 ARCH_OMAP3
- tristate Enable support for hardware BCH error correction
+ tristate Support hardware based BCH error correction
default n
select BCH
- select BCH_CONST_PARAMS
help
-Support for hardware BCH error correction.
-
-choice
- prompt BCH error correction capability
- depends on MTD_NAND_OMAP_BCH
-
-config MTD_NAND_OMAP_BCH8
- bool 8 bits / 512 bytes (recommended)
- help
-Support correcting up to 8 bitflips per 512-byte block.
-This will use 13 bytes of spare area per 512 bytes of page data.
-This is the recommended mode, as 4-bit mode does not work
-on some OMAP3 revisions, due to a hardware bug.
-
-config MTD_NAND_OMAP_BCH4
- bool 4 bits / 512 bytes
- help
-Support correcting up to 4 bitflips per 512-byte block.
-This will use 7 bytes of spare area per 512 bytes of page data.
-Note that this mode does not work on some OMAP3 revisions, due to a
-hardware bug. Please check your OMAP datasheet before selecting this
-mode.
-
-endchoice
+ Some devices have built-in ELM hardware engine, which can be used to
+ locate and correct errors when using BCH ECC scheme. This enables the
+ driver support for same.
if MTD_NAND_OMAP_BCH
config BCH_CONST_M
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index fb96251..a783dae 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -27,6 +27,7 @@
#ifdef CONFIG_MTD_NAND_ECC_BCH
#include linux/bch.h
+#include linux/mtd/nand_bch.h
#endif
#ifdef CONFIG_MTD_NAND_OMAP_BCH
#include linux/platform_data/elm.h
@@ -144,7 +145,6 @@
#define BCH_ECC_SIZE1 0x20/* ecc_size1 = 32 */
#define BADBLOCK_MARKER_LENGTH 2
-#define OMAP_ECC_BCH8_POLYNOMIAL 0x201b
#ifdef CONFIG_MTD_NAND_OMAP_BCH
static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
@@ -188,7 +188,6 @@ struct omap_nand_info {
int buf_len;
struct gpmc_nand_regs reg;
/* fields specific for BCHx_HW ECC scheme */
- struct bch_control *bch;
boolis_elm_used;
struct device *elm_dev;
struct device_node *of_node;
@@ -1522,43 +1521,7 @@ static int omap_elm_correct_data(struct mtd_info *mtd,
u_char *data,
return stat;
}
-#endif /* CONFIG_MTD_NAND_OMAP_BCH */
-#ifdef CONFIG_MTD_NAND_ECC_BCH
-/**
- * omap3_correct_data_bch - Decode received data and correct errors
- * @mtd: MTD device structure
- * @data: page data
- * @read_ecc: ecc read from nand flash
- * @calc_ecc: ecc read from HW ECC registers
- */
-static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
- u_char *read_ecc, u_char *calc_ecc)
-{
- int i, count;
- /* cannot correct more
[PATCH v7 3/6] mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe
OMAP NAND driver support multiple ECC scheme, which can used in following
different flavours, depending on in-build Hardware engines supported by SoC.
+---+---+---+
| ECC scheme|ECC calculation|Error detection|
+---+---+---+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W|
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W|
|(requires CONFIG_MTD_NAND_ECC_BCH) | | |
+---+---+---+
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
|(requires CONFIG_MTD_NAND_OMAP_BCH | | |
| ti,elm-id in DT) | | |
+---+---+---+
To optimize footprint of omap2-nand driver, selection of some ECC schemes
also require enabling following Kconfigs, in addition to setting appropriate
DT bindings
- Kconfig:CONFIG_MTD_NAND_ECC_BCHenables S/W based BCH ECC algorithm
- Kconfig:CONFIG_MTD_NAND_OMAP_BCH enables H/W based BCH ECC algorithm
This patch
- removes OMAP_ECC_HAMMING_CODE_DEFAULT and OMAP_ECC_HAMMING_CODE_HW_ROMCODE
- separates the configurations for other ECC schemes
- fixes dependency issues based on Kconfig options
- updates ELM device detection in is_elm_present()
- cleans redundant code
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 450 +++
1 file changed, 220 insertions(+), 230 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 8d521aa..fb96251 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -25,8 +25,10 @@
#include linux/of.h
#include linux/of_device.h
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
+#ifdef CONFIG_MTD_NAND_ECC_BCH
#include linux/bch.h
+#endif
+#ifdef CONFIG_MTD_NAND_OMAP_BCH
#include linux/platform_data/elm.h
#endif
@@ -141,6 +143,9 @@
#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
#define BCH_ECC_SIZE1 0x20/* ecc_size1 = 32 */
+#define BADBLOCK_MARKER_LENGTH 2
+#define OMAP_ECC_BCH8_POLYNOMIAL 0x201b
+
#ifdef CONFIG_MTD_NAND_OMAP_BCH
static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
0xac, 0x6b, 0xff, 0x99, 0x7b};
@@ -182,14 +187,11 @@ struct omap_nand_info {
u_char *buf;
int buf_len;
struct gpmc_nand_regs reg;
-
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
- struct bch_control *bch;
- struct nand_ecclayout ecclayout;
+ /* fields specific for BCHx_HW ECC scheme */
+ struct bch_control *bch;
boolis_elm_used;
struct device *elm_dev;
struct device_node *of_node;
-#endif
};
/**
@@ -1058,8 +1060,7 @@ static int omap_dev_ready(struct mtd_info *mtd)
}
}
-#ifdef CONFIG_MTD_NAND_OMAP_BCH
-
+#if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
/**
* omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
* @mtd: MTD device structure
@@ -1140,7 +1141,9 @@ static void omap3_enable_hwecc_bch(struct mtd_info *mtd,
int mode)
/* Clear ecc and enable bits */
writel(ECCCLEAR | ECC1, info-reg.gpmc_ecc_control);
}
+#endif
+#ifdef CONFIG_MTD_NAND_ECC_BCH
/**
* omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
* @mtd: MTD device structure
@@ -1225,7 +1228,9 @@ static int omap3_calculate_ecc_bch8(struct mtd_info *mtd,
const u_char *dat,
return 0;
}
+#endif /* CONFIG_MTD_NAND_ECC_BCH */
+#ifdef CONFIG_MTD_NAND_OMAP_BCH
/**
* omap3_calculate_ecc_bch - Generate bytes of ECC bytes
* @mtd: MTD device structure
@@ -1517,7 +1522,9 @@ static int omap_elm_correct_data(struct mtd_info *mtd,
u_char *data,
return stat;
}
+#endif /* CONFIG_MTD_NAND_OMAP_BCH */
+#ifdef CONFIG_MTD_NAND_ECC_BCH
/**
* omap3_correct_data_bch - Decode received data and correct errors
* @mtd: MTD device structure
@@ -1549,7 +1556,9 @@ static int omap3_correct_data_bch(struct mtd_info *mtd,
u_char *data,
}
return count;
}
+#endif /* CONFIG_MTD_NAND_ECC_BCH */
+#ifdef CONFIG_MTD_NAND_OMAP_BCH
/**
* omap_write_page_bch - BCH ecc based write page function for entire page
* @mtd: mtd info structure
@@ -1637,197 +1646,68 @@ static int omap_read_page_bch(struct mtd_info *mtd,
struct nand_chip *chip,
}
/**
- * omap3_free_bch - Release BCH ecc resources
- * @mtd: MTD device structure
+ * is_elm_present - checks for presence of
[PATCH v7 6/6] mtd: nand: omap: updated devm_xx for all resource allocation and free calls
Managed Device Resource or devm_xx calls takes care of automatic freeing
of the resource in case of:
- failure during driver probe
- failure during resource allocation
- detaching or unloading of driver module (rmmod)
Reference: Documentation/driver-model/devres.txt
Though OMAP NAND driver handles freeing of resource allocation in most of
the cases, but using devm_xx provides more clean and effortless approach
to handle all such cases.
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 38 +-
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index a783dae..0f2b0d1 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1658,7 +1658,8 @@ static int omap_nand_probe(struct platform_device *pdev)
return -ENODEV;
}
- info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
+ info = devm_kzalloc(pdev-dev, sizeof(struct omap_nand_info),
+ GFP_KERNEL);
if (!info)
return -ENOMEM;
@@ -1690,13 +1691,14 @@ static int omap_nand_probe(struct platform_device *pdev)
info-phys_base = res-start;
info-mem_size = resource_size(res);
- if (!request_mem_region(info-phys_base, info-mem_size,
- pdev-dev.driver-name)) {
+ if (!devm_request_mem_region(pdev-dev, info-phys_base,
+ info-mem_size, pdev-dev.driver-name)) {
err = -EBUSY;
goto out_free_info;
}
- info-nand.IO_ADDR_R = ioremap(info-phys_base, info-mem_size);
+ info-nand.IO_ADDR_R = devm_ioremap(pdev-dev, info-phys_base,
+ info-mem_size);
if (!info-nand.IO_ADDR_R) {
err = -ENOMEM;
goto out_release_mem_region;
@@ -1799,8 +1801,9 @@ static int omap_nand_probe(struct platform_device *pdev)
err = -ENODEV;
goto out_release_mem_region;
}
- err = request_irq(info-gpmc_irq_fifo, omap_nand_irq,
- IRQF_SHARED, gpmc-nand-fifo, info);
+ err = devm_request_irq(pdev-dev, info-gpmc_irq_fifo,
+ omap_nand_irq, IRQF_SHARED,
+ gpmc-nand-fifo, info);
if (err) {
dev_err(pdev-dev, requesting irq(%d) error:%d,
info-gpmc_irq_fifo, err);
@@ -1814,8 +1817,9 @@ static int omap_nand_probe(struct platform_device *pdev)
err = -ENODEV;
goto out_release_mem_region;
}
- err = request_irq(info-gpmc_irq_count, omap_nand_irq,
- IRQF_SHARED, gpmc-nand-count, info);
+ err = devm_request_irq(pdev-dev, info-gpmc_irq_count,
+ omap_nand_irq, IRQF_SHARED,
+ gpmc-nand-count, info);
if (err) {
dev_err(pdev-dev, requesting irq(%d) error:%d,
info-gpmc_irq_count, err);
@@ -2031,10 +2035,10 @@ out_release_mem_region:
if (info-dma)
dma_release_channel(info-dma);
if (info-gpmc_irq_count 0)
- free_irq(info-gpmc_irq_count, info);
+ devm_free_irq(pdev-dev, info-gpmc_irq_count, info);
if (info-gpmc_irq_fifo 0)
- free_irq(info-gpmc_irq_fifo, info);
- release_mem_region(info-phys_base, info-mem_size);
+ devm_free_irq(pdev-dev, info-gpmc_irq_fifo, info);
+ devm_release_mem_region(pdev-dev, info-phys_base, info-mem_size);
out_free_info:
#ifdef CONFIG_MTD_NAND_ECC_BCH
if (info-nand.ecc.priv) {
@@ -2042,7 +2046,7 @@ out_free_info:
info-nand.ecc.priv = NULL;
}
#endif
- kfree(info);
+ devm_kfree(pdev-dev, info);
return err;
}
@@ -2062,15 +2066,15 @@ static int omap_nand_remove(struct platform_device
*pdev)
dma_release_channel(info-dma);
if (info-gpmc_irq_count 0)
- free_irq(info-gpmc_irq_count, info);
+ devm_free_irq(pdev-dev, info-gpmc_irq_count, info);
if (info-gpmc_irq_fifo 0)
- free_irq(info-gpmc_irq_fifo, info);
+ devm_free_irq(pdev-dev, info-gpmc_irq_fifo, info);
/* Release NAND device, its internal structures and partitions */
nand_release(info-mtd);
- iounmap(info-nand.IO_ADDR_R);
- release_mem_region(info-phys_base, info-mem_size);
- kfree(info);
+ devm_iounmap(pdev-dev, info-nand.IO_ADDR_R);
+ devm_release_mem_region(pdev-dev, info-phys_base, info-mem_size);
+ devm_kfree(pdev-dev,
[RFC PATCH v2] ARM: OMAP4/highbank: Flush L2 cache before disabling
Kexec disables outer cache before jumping to reboot code, but it doesn't
flush it explicitly. Flush is done implicitly inside of l2x0_disable().
But some SoC's override default .disable handler and don't flush cache.
This may lead to a corrupted memory during Kexec reboot on these platforms.
This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable()
handlers to make it consistent with default l2x0_disable().
Also it removes redundant outer_flush_all() call just before outer_disable().
Signed-off-by: Taras Kondratiuk taras.kondrat...@linaro.org
---
v2: Make the fix specific to platforms that don't use l2x0_disable().
v1: https://patchwork.kernel.org/patch/2974431/
---
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Rob Herring rob.herr...@calxeda.com
Cc: linaro-ker...@lists.linaro.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-omap@vger.kernel.org
---
arch/arm/mach-highbank/highbank.c |1 +
arch/arm/mach-highbank/pm.c|1 -
arch/arm/mach-omap2/omap4-common.c |1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-highbank/highbank.c
b/arch/arm/mach-highbank/highbank.c
index 8e63ccd..22e6f34 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -63,6 +63,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
static void highbank_l2x0_disable(void)
{
+ outer_flush_all();
/* Disable PL310 L2 Cache controller */
highbank_smc1(0x102, 0x0);
}
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c
index 04eddb4..9a5b8a7 100644
--- a/arch/arm/mach-highbank/pm.c
+++ b/arch/arm/mach-highbank/pm.c
@@ -28,7 +28,6 @@
static int highbank_suspend_finish(unsigned long val)
{
- outer_flush_all();
outer_disable();
highbank_set_pwr_suspend();
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index 5791143..3f44b16 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -163,6 +163,7 @@ void __iomem *omap4_get_l2cache_base(void)
static void omap4_l2x0_disable(void)
{
+ outer_flush_all();
/* Disable PL310 L2 Cache controller */
omap_smc1(0x102, 0x0);
}
--
1.7.9.5
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Re: [RFC PATCH v2] ARM: OMAP4/highbank: Flush L2 cache before disabling
On 10/04/2013 03:57 PM, Taras Kondratiuk wrote:
Kexec disables outer cache before jumping to reboot code, but it doesn't
flush it explicitly. Flush is done implicitly inside of l2x0_disable().
But some SoC's override default .disable handler and don't flush cache.
This may lead to a corrupted memory during Kexec reboot on these platforms.
This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable()
handlers to make it consistent with default l2x0_disable().
Also it removes redundant outer_flush_all() call just before outer_disable().
Signed-off-by: Taras Kondratiuk taras.kondrat...@linaro.org
Acked-by: Rob Herring rob.herr...@calxeda.com
---
v2: Make the fix specific to platforms that don't use l2x0_disable().
v1: https://patchwork.kernel.org/patch/2974431/
---
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Rob Herring rob.herr...@calxeda.com
Cc: linaro-ker...@lists.linaro.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-omap@vger.kernel.org
---
arch/arm/mach-highbank/highbank.c |1 +
arch/arm/mach-highbank/pm.c|1 -
arch/arm/mach-omap2/omap4-common.c |1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-highbank/highbank.c
b/arch/arm/mach-highbank/highbank.c
index 8e63ccd..22e6f34 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -63,6 +63,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
static void highbank_l2x0_disable(void)
{
+ outer_flush_all();
/* Disable PL310 L2 Cache controller */
highbank_smc1(0x102, 0x0);
}
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c
index 04eddb4..9a5b8a7 100644
--- a/arch/arm/mach-highbank/pm.c
+++ b/arch/arm/mach-highbank/pm.c
@@ -28,7 +28,6 @@
static int highbank_suspend_finish(unsigned long val)
{
- outer_flush_all();
outer_disable();
highbank_set_pwr_suspend();
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index 5791143..3f44b16 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -163,6 +163,7 @@ void __iomem *omap4_get_l2cache_base(void)
static void omap4_l2x0_disable(void)
{
+ outer_flush_all();
/* Disable PL310 L2 Cache controller */
omap_smc1(0x102, 0x0);
}
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Re: [RFC PATCH v2] ARM: OMAP4/highbank: Flush L2 cache before disabling
On Friday 04 October 2013 04:57 PM, Taras Kondratiuk wrote: Kexec disables outer cache before jumping to reboot code, but it doesn't flush it explicitly. Flush is done implicitly inside of l2x0_disable(). But some SoC's override default .disable handler and don't flush cache. This may lead to a corrupted memory during Kexec reboot on these platforms. This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable() handlers to make it consistent with default l2x0_disable(). Also it removes redundant outer_flush_all() call just before outer_disable(). Signed-off-by: Taras Kondratiuk taras.kondrat...@linaro.org --- v2: Make the fix specific to platforms that don't use l2x0_disable(). v1: https://patchwork.kernel.org/patch/2974431/ --- Acked-by: Santosh Shilimkar santosh.shilim...@ti.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 0/2] ARM: dts: Add initial support for IGEP AQUILA
Hi Benoit, 2013/10/4 Benoit Cousson bcous...@baylibre.com: Hi Enric, On 03/10/2013 20:17, Tony Lindgren wrote: * Javier Martinez Canillas martinez.jav...@gmail.com [130925 06:18]: On Tue, Sep 10, 2013 at 4:55 PM, Enric Balletbo i Serra eballe...@gmail.com wrote: From: Enric Balletbo i Serra eballe...@iseebcn.com Hi all, These two patches introduces initial support for the IGEP AM335x-based platforms. The first patch add support for IGEP COM AQUILA products, and the second patch add support for the development board. These patches apply on top of bcousson/for_3.12/dts repository. Changes since v2: * Make it compatible with isee,am335x-base0033, isee,am335x-igep0033, ti,am33xx since these boards are manufactured by ISEE not TI. (Javier) Changes since v1: * Use node to reference the nodes already defined in dtsi files. (Javier) Best regards, Enric Balletbo i Serra (2): ARM: dts: AM33XX: Add support for IGEP COM AQUILA ARM: dts: AM33XX: Add support for IGEP AQUILA EXPANSION board. arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-base0033.dts | 16 ++ arch/arm/boot/dts/am335x-igep0033.dtsi | 265 + 3 files changed, 282 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-base0033.dts create mode 100644 arch/arm/boot/dts/am335x-igep0033.dtsi -- 1.8.1.2 Hi Benoit and Tony, Any comments on this series? I had already reviewed previous versions of the DT and it looks good to me now. It would be great if this can make it for 3.13. Looks good to me, I would assume Benoit will be looking at this shortly. I did :-) It looks good to me too, I've just fixed a conflict with my current branch in the Makefile and fix a typo in the header: +++ b/arch/arm/boot/dts/am335x-base0033.dts @@ -0,0 +1,16 @@ +/* + * am335x-base0033.dtsi - Device Tree file for IGEP AQUILA EXPANSION Should be am335x-base0033.dts. I fixed it for you. Please check if the fix is ok in the branch. Checked. Pushed on my for_3.13/dts branch. Thanks, Benoit Thanks, Enric -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] ARM: dts: omap3-igep0020: Add HS USB Host support
Add device nodes for the HS USB Host port 1, USB PHY and its
required regulator and also pin mux setup for HS USB1 pins.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/boot/dts/omap3-igep.dtsi| 22 ++
arch/arm/boot/dts/omap3-igep0020.dts | 25 +
2 files changed, 47 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi
b/arch/arm/boot/dts/omap3-igep.dtsi
index 0f92224..ec2ecd2 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -27,6 +27,11 @@
};
omap3_pmx_core {
+ pinctrl-names = default;
+ pinctrl-0 =
+ hsusbb1_pins
+ ;
+
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins =
0x152 (PIN_INPUT | MUX_MODE0) /*
uart1_rx.uart1_rx */
@@ -78,6 +83,23 @@
;
};
+ hsusbb1_pins: pinmux_hsusbb1_pins {
+ pinctrl-single,pins =
+ 0x5aa (PIN_OUTPUT | MUX_MODE3) /*
etk_ctl.hsusb1_clk */
+ 0x5a8 (PIN_OUTPUT | MUX_MODE3) /*
etk_clk.hsusb1_stp */
+ 0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d8.hsusb1_dir */
+ 0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d9.hsusb1_nxt */
+ 0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d0.hsusb1_data0 */
+ 0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d1.hsusb1_data1 */
+ 0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d2.hsusb1_data2 */
+ 0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d3.hsusb1_data7 */
+ 0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d4.hsusb1_data4 */
+ 0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d5.hsusb1_data5 */
+ 0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d6.hsusb1_data6 */
+ 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
etk_d7.hsusb1_data3 */
+ ;
+ };
+
leds_pins: pinmux_leds_pins { };
};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts
b/arch/arm/boot/dts/omap3-igep0020.dts
index 903e944..180b186 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -55,6 +55,23 @@
regulator-name = vdd33a;
regulator-always-on;
};
+
+ /* HS USB Port 1 Power */
+ hsusb1_power: hsusb1_power_reg {
+ compatible = regulator-fixed;
+ regulator-name = hsusb1_vbus;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ gpio = twl_gpio 18 GPIO_ACTIVE_LOW; /* GPIO LEDA */
+ startup-delay-us = 7;
+ };
+
+ /* HS USB Host PHY on PORT 1 */
+ hsusb1_phy: hsusb1_phy {
+ compatible = usb-nop-xceiv;
+ reset-gpios = gpio1 24 GPIO_ACTIVE_LOW; /* gpio_24 */
+ vcc-supply = hsusb1_power;
+ };
};
leds_pins {
@@ -173,3 +190,11 @@
mode = 3;
power = 50;
};
+
+usbhshost {
+ port1-mode = ehci-phy;
+};
+
+usbhsehci {
+ phys = hsusb1_phy;
+};
--
1.8.4.rc3
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[PATCH 1/3] ARM: dts: omap3-igep0020: Add USB OTG support
Commit ad871c10b (ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards)
added USB OTG support for most OMAP boards but some OMAP3 boards
such as the IGEPv2 were not updated. This patch adds an USB OTG
device node to this board.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/boot/dts/omap3-igep0020.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts
b/arch/arm/boot/dts/omap3-igep0020.dts
index eedf0d8..903e944 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -166,3 +166,10 @@
smsc,save-mac-address;
};
};
+
+usb_otg_hs {
+ interface-type = 0;
+ usb-phy = usb2_phy;
+ mode = 3;
+ power = 50;
+};
--
1.8.4.rc3
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[PATCH 3/3] ARM: dts: omap3-igep0020: use standard constant for IRQ flags
Commit 840ef8b7 (ARM: dt: add header to define IRQ flags) added constants for IRQ edge/level triggered types so use it instead of a magic number to enhance the DT readability. Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk --- arch/arm/boot/dts/omap3-igep0020.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index 180b186..64884fa 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -175,7 +175,7 @@ gpmc,cycle2cycle-diffcsen; interrupt-parent = gpio6; - interrupts = 16 8; + interrupts = 16 IRQ_TYPE_LEVEL_LOW; vmmc-supply = vddvario; vmmc_aux-supply = vdd33a; reg-io-width = 4; -- 1.8.4.rc3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] ARM: dts: omap3-igep0020: improvements for v3.13
Hi Benoit, This series are some enhancements and cleanups for IGEP boards that it would be great if can make it for v3.13. The patch-set is composed of the following patches: [PATCH 1/3] ARM: dts: omap3-igep0020: Add USB OTG support [PATCH 2/3] ARM: dts: omap3-igep0020: Add HS USB Host support [PATCH 3/3] ARM: dts: omap3-igep0020: use standard constant for IRQ flags Patch 1 and 2 adds USB OTG and Host support respectively and patch 3 is a small cleanup to get rid of a magic number and use the proper constant for IRQ edge/level type flags. Thanks a lot and best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] ARM: OMAP2+: pdata-quirks: add legacy display init for IGEPv2 board
IGEPv2 board has both an DVI and TFP410 video interfaces but
DSS support for DeviceTree has not yet landed in mainline so
is necessary to init the displays using legacy platform code.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/mach-omap2/dss-common.c | 37 +
arch/arm/mach-omap2/dss-common.h | 1 +
arch/arm/mach-omap2/pdata-quirks.c | 7 +++
3 files changed, 45 insertions(+)
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index bf89eff..0c1cf2e 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -39,6 +39,7 @@
#define HDMI_GPIO_HPD 63 /* Hotplug detect */
#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0
+#define IGEP2_DVI_TFP410_POWER_DOWN_GPIO 170
/* DVI Connector */
static struct connector_dvi_platform_data omap4_panda_dvi_connector_pdata = {
@@ -53,6 +54,18 @@ static struct platform_device
omap4_panda_dvi_connector_device = {
.dev.platform_data = omap4_panda_dvi_connector_pdata,
};
+static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
+ .name = dvi,
+ .source = tfp410.0,
+ .i2c_bus_num= 3,
+};
+
+static struct platform_device omap3_igep2_dvi_connector_device = {
+ .name = connector-dvi,
+ .id = 0,
+ .dev.platform_data = omap3_igep2_dvi_connector_pdata,
+};
+
/* TFP410 DPI-to-DVI chip */
static struct encoder_tfp410_platform_data omap4_panda_tfp410_pdata = {
.name = tfp410.0,
@@ -67,6 +80,19 @@ static struct platform_device omap4_panda_tfp410_device = {
.dev.platform_data = omap4_panda_tfp410_pdata,
};
+static struct encoder_tfp410_platform_data omap3_igep2_tfp410_pdata = {
+ .name = tfp410.0,
+ .source = dpi.0,
+ .data_lines = 24,
+ .power_down_gpio= IGEP2_DVI_TFP410_POWER_DOWN_GPIO,
+};
+
+static struct platform_device omap3_igep2_tfp410_device = {
+ .name = tfp410,
+ .id = 0,
+ .dev.platform_data = omap3_igep2_tfp410_pdata,
+};
+
/* HDMI Connector */
static struct connector_hdmi_platform_data omap4_panda_hdmi_connector_pdata = {
.name = hdmi,
@@ -99,6 +125,10 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
.default_display_name = dvi,
};
+static struct omap_dss_board_info igep2_dss_data = {
+ .default_display_name = dvi,
+};
+
void __init omap4_panda_display_init_of(void)
{
omap_display_init(omap4_panda_dss_data);
@@ -110,6 +140,13 @@ void __init omap4_panda_display_init_of(void)
platform_device_register(omap4_panda_hdmi_connector_device);
}
+void __init omap3_igep2_display_init_of(void)
+{
+ omap_display_init(igep2_dss_data);
+
+ platform_device_register(omap3_igep2_tfp410_device);
+ platform_device_register(omap3_igep2_dvi_connector_device);
+}
/* OMAP4 Blaze display data */
diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h
index c28fe3c..a9becf0 100644
--- a/arch/arm/mach-omap2/dss-common.h
+++ b/arch/arm/mach-omap2/dss-common.h
@@ -8,5 +8,6 @@
void __init omap4_panda_display_init_of(void);
void __init omap_4430sdp_display_init_of(void);
+void __init omap3_igep2_display_init_of(void);
#endif
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index 3d472db..830a4d2 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -74,6 +74,11 @@ static void __init hsmmc2_internal_input_clk(void)
reg |= OMAP2_MMCSDIO2ADPCLKISEL;
omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
}
+
+static void __init omap3_igep0020_legacy_init(void)
+{
+ omap3_igep2_display_init_of();
+}
#endif /* CONFIG_ARCH_OMAP3 */
#ifdef CONFIG_ARCH_OMAP4
@@ -103,6 +108,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
#ifdef CONFIG_ARCH_OMAP3
{ nokia,omap3-n9, hsmmc2_internal_input_clk, },
{ nokia,omap3-n950, hsmmc2_internal_input_clk, },
+ { nokia,omap3-n950, hsmmc2_internal_input_clk, },
+ { isee,omap3-igep0020, omap3_igep0020_legacy_init, },
#endif
#ifdef CONFIG_ARCH_OMAP4
{ ti,omap4-sdp, omap4_sdp_legacy_init, },
--
1.8.4.rc3
--
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[PATCH v2 1/1] ARM: OMAP2+: pdata-quirks: add legacy display init for IGEPv2 board
IGEPv2 board has both an DVI and TFP410 video interfaces but
DSS support for DeviceTree has not yet landed in mainline so
is necessary to init the displays using legacy platform code.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1:
- Remove duplicate entry in pdata_quirks[] due silly copy paste error.
Sorry for the noise.
arch/arm/mach-omap2/dss-common.c | 37 +
arch/arm/mach-omap2/dss-common.h | 1 +
arch/arm/mach-omap2/pdata-quirks.c | 6 ++
3 files changed, 44 insertions(+)
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index bf89eff..0c1cf2e 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -39,6 +39,7 @@
#define HDMI_GPIO_HPD 63 /* Hotplug detect */
#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0
+#define IGEP2_DVI_TFP410_POWER_DOWN_GPIO 170
/* DVI Connector */
static struct connector_dvi_platform_data omap4_panda_dvi_connector_pdata = {
@@ -53,6 +54,18 @@ static struct platform_device
omap4_panda_dvi_connector_device = {
.dev.platform_data = omap4_panda_dvi_connector_pdata,
};
+static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
+ .name = dvi,
+ .source = tfp410.0,
+ .i2c_bus_num= 3,
+};
+
+static struct platform_device omap3_igep2_dvi_connector_device = {
+ .name = connector-dvi,
+ .id = 0,
+ .dev.platform_data = omap3_igep2_dvi_connector_pdata,
+};
+
/* TFP410 DPI-to-DVI chip */
static struct encoder_tfp410_platform_data omap4_panda_tfp410_pdata = {
.name = tfp410.0,
@@ -67,6 +80,19 @@ static struct platform_device omap4_panda_tfp410_device = {
.dev.platform_data = omap4_panda_tfp410_pdata,
};
+static struct encoder_tfp410_platform_data omap3_igep2_tfp410_pdata = {
+ .name = tfp410.0,
+ .source = dpi.0,
+ .data_lines = 24,
+ .power_down_gpio= IGEP2_DVI_TFP410_POWER_DOWN_GPIO,
+};
+
+static struct platform_device omap3_igep2_tfp410_device = {
+ .name = tfp410,
+ .id = 0,
+ .dev.platform_data = omap3_igep2_tfp410_pdata,
+};
+
/* HDMI Connector */
static struct connector_hdmi_platform_data omap4_panda_hdmi_connector_pdata = {
.name = hdmi,
@@ -99,6 +125,10 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
.default_display_name = dvi,
};
+static struct omap_dss_board_info igep2_dss_data = {
+ .default_display_name = dvi,
+};
+
void __init omap4_panda_display_init_of(void)
{
omap_display_init(omap4_panda_dss_data);
@@ -110,6 +140,13 @@ void __init omap4_panda_display_init_of(void)
platform_device_register(omap4_panda_hdmi_connector_device);
}
+void __init omap3_igep2_display_init_of(void)
+{
+ omap_display_init(igep2_dss_data);
+
+ platform_device_register(omap3_igep2_tfp410_device);
+ platform_device_register(omap3_igep2_dvi_connector_device);
+}
/* OMAP4 Blaze display data */
diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h
index c28fe3c..a9becf0 100644
--- a/arch/arm/mach-omap2/dss-common.h
+++ b/arch/arm/mach-omap2/dss-common.h
@@ -8,5 +8,6 @@
void __init omap4_panda_display_init_of(void);
void __init omap_4430sdp_display_init_of(void);
+void __init omap3_igep2_display_init_of(void);
#endif
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index 3d472db..9113e70 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -74,6 +74,11 @@ static void __init hsmmc2_internal_input_clk(void)
reg |= OMAP2_MMCSDIO2ADPCLKISEL;
omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
}
+
+static void __init omap3_igep0020_legacy_init(void)
+{
+ omap3_igep2_display_init_of();
+}
#endif /* CONFIG_ARCH_OMAP3 */
#ifdef CONFIG_ARCH_OMAP4
@@ -103,6 +108,7 @@ static struct pdata_init pdata_quirks[] __initdata = {
#ifdef CONFIG_ARCH_OMAP3
{ nokia,omap3-n9, hsmmc2_internal_input_clk, },
{ nokia,omap3-n950, hsmmc2_internal_input_clk, },
+ { isee,omap3-igep0020, omap3_igep0020_legacy_init, },
#endif
#ifdef CONFIG_ARCH_OMAP4
{ ti,omap4-sdp, omap4_sdp_legacy_init, },
--
1.8.4.rc3
--
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