Re: [RFC] CPSW: dual standalone emac mode / bonding
On Wednesday 05 March 2014 11:03 PM, Christian Engelmayer wrote: Has anybody successfuly setup ethernet bonding on a TI AM335x based system using the CPSW in dual standalone emac mode? I am running an active-backup test setup - momentarily still running Linux 3.2 - and experience repeated loss of ethernet connectivity. That happens eg. after the board is idle and receives an own ARP request on the backup slave interface. It seems that the corresponding reply does not reach the CPU and I can see via SysFs that the host's address entry got associated with the external backup port. index 2, raw: 1018 31e00669, type: addr(1), addr: 00:18:31:e0:06:69, uctype: persistant(0), port: 0 -- uctype: persistant(0), port: 2 As expected, triggering a unicast from the board or bypassing the ALE recovers It seems that some other system in the network is using the same mac in your EVM or there is a loop detected in your network which leads that ALE is learning that there is system with your MAC and updating the ALE table that the mac is there and which leads your own packet will be forwarded to that port and not to host port. When ever you start a transmission the ALE learns the host port MAC is x and updates ALE table with that port number and so there in your network is working. Regards Mugunthan V N -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] ARM: dts: AM4372: Add USB nodes
Hi George,
On 03/03/2014 03:53 PM, George Cherian wrote:
Add nodes for 2 instances each of
- ocp2scp
- USB PHY control module
- USB PHY
- dwc3_omap
- USB
for AM43xx.
Signed-off-by: George Cherian george.cher...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 99
+++
1 file changed, 99 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 5a7cc38..90408b3 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -698,6 +698,105 @@
edma 11;
dma-names = tx, rx;
};
+
+ am43xx_control_usb2phy1: control-phy@44e10620 {
+ compatible = ti,control-phy-am437usb2;
Since this is the first usage of this compatible ID, we still have room to
change it to be better. Tony's suggestion was to use ti,control-phy-am437-usb2
Please see
http://article.gmane.org/gmane.linux.drivers.devicetree/64833
+ reg = 0x44e10620 0x4;
+ reg-names = power;
+ status = disabled;
Why disable something that is within the SoC and does not affect board
configurations?
Question applies for all the nodes in this patch except the ones that come out
on the
SoC pins. e.g. PHY.
+ };
+
+ am43xx_control_usb2phy2: control-phy@0x44e10628 {
+ compatible = ti,control-phy-am437usb2;
+ reg = 0x44e10628 0x4;
+ reg-names = power;
+ status = disabled;
+ };
+
+ ocp2scp0: ocp2scp@483a8000 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ ti,hwmods = ocp2scp0;
+ status = disabled;
+
+ usb2_phy1: usb2phy1@483a8000 {
should be
usb2_phy1: phy@483a8000 {
+ compatible = ti,am437x-usb2;
+ reg = 0x483a8000 0x8000;
+ ctrl-module = am43xx_control_usb2phy1;
+ clocks = clk_32768_ck,
+ usb_otg_ss0_refclk960m;
+ clock-names = usb_phy_cm_clk32k,
+ usb_otg_ss_refclk960m;
clock-names should be platform independent. Better option would be to
modify the usb2 driver to use names like wkupclk and refclk
+ #phy-cells = 0;
+ status = disabled;
+ };
+ };
+
+ ocp2scp1: ocp2scp@483e8000 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ ti,hwmods = ocp2scp1;
+ status = disabled;
+
+ usb2_phy2: usb2phy2@483e8000 {
+ compatible = ti,am437x-usb2;
+ reg = 0x483e8000 0x8000;
+ ctrl-module = am43xx_control_usb2phy2;
+ clocks = clk_32768_ck,
+ usb_otg_ss1_refclk960m;
+ clock-names = usb_phy_cm_clk32k,
+ usb_otg_ss_refclk960m;
+ #phy-cells = 0;
+ status = disabled;
+ };
+ };
+
+ dwc3_1: omap_dwc3_1@4838 {
+ compatible = ti,am437x-dwc3;
+ ti,hwmods = usb_otg_ss0;
+ reg = 0x4838 0x1;
+ interrupts = GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH;
+ #address-cells = 1;
+ #size-cells = 1;
+ utmi-mode = 1;
+ ranges;
+ status = disabled;
+
+ usb1: usb@4839 {
+ compatible = synopsys,dwc3;
+ reg = 0x4839 0x17000;
+ interrupts = GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH;
+ usb-phy = usb2_phy1;
shouldn't this be phys = usb2_phy1;?
+ phy-names = usb2-phy;
what about
maximum-speed = high-speed;
and
dr_mode = otg; ?
+ status = disabled;
+ };
+ };
+
+ dwc3_2: omap_dwc3_2@483c {
+ compatible = ti,am437x-dwc3;
+ ti,hwmods = usb_otg_ss1;
+ reg = 0x483c 0x1;
+
Re: [PATCH 5/5] doc: Add ti,am437x-dwc3 comaptible for dwc3 glue
On 03/03/2014 03:53 PM, George Cherian wrote: Add the compatible ti,am437x-dwc3 for dwc3 glue driver. Signed-off-by: George Cherian george.cher...@ti.com --- Documentation/devicetree/bindings/usb/omap-usb.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) The patch order could be the rearranged so that this appears before the am437x bindings are used. cheers, -roger diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt index c495135..1d38569 100644 --- a/Documentation/devicetree/bindings/usb/omap-usb.txt +++ b/Documentation/devicetree/bindings/usb/omap-usb.txt @@ -44,7 +44,9 @@ Board specific device node entry }; OMAP DWC3 GLUE - - compatible : Should be ti,dwc3 + - compatible : Should be + * ti,dwc3 for OMAP5 and DRA7 + * ti,am437x-dwc3 for AM437x - ti,hwmods : Should be usb_otg_ss - reg : Address and length of the register set for the device. - interrupts : The irq number of this device that is used to interrupt the -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Help needed USB hub disconnected at resume
On 03/06/2014 01:29 AM, Marc Murphy wrote:
-Original Message-
From: Felipe Balbi [mailto:ba...@ti.com]
Sent: 04 March 2014 23:43
To: Marc Murphy
Cc: 'ba...@ti.com'; 'Igor Grinberg'; Roger Quadros; linux-
o...@vger.kernel.org
Subject: Re: Help needed USB hub disconnected at resume
On Tue, Mar 04, 2014 at 11:05:58PM +, Marc Murphy wrote:
-Original Message-
From: Felipe Balbi [mailto:ba...@ti.com]
Sent: 04 March 2014 22:44
To: Marc Murphy
Cc: 'Igor Grinberg'; Roger Quadros; linux-omap@vger.kernel.org
Subject: Re: Help needed USB hub disconnected at resume
Hi,
On Tue, Mar 04, 2014 at 10:34:56PM +, Marc Murphy wrote:
static __init void tam3517_ehci_init(void) {
/* Configure GPIO for EHCI port */
omap_mux_init_gpio(TAM3517_EHCI_RESET, OMAP_PIN_OUTPUT);
gpio_request(TAM3517_EHCI_RESET, USB_RESET);
gpio_direction_output(TAM3517_EHCI_RESET, 1);
gpio_export(TAM3517_EHCI_RESET, 0);
why are you exporting this gpio ?
It makes no difference whether I configure the GPIO or not.
gpio_export() is only to expose the gpio to sysfs. Check if that pin is
active
high or active low. Then what you need, most likely, is something like below:
gpio_direction_output(RESET, HIGH);
usleep_range(5, 200);
gpio_set_value(RESET, LOW);
(assuming active high here)
Thanks, the export was for sysfs so that I could toggle the state myself to
debug. The reference has now been removed and the toggling left to the
driver (ehci)
Igor, I have been looking at the ehci driver and the reset pin of the 3320 is
toggled at initialisation but there is no resetting when resuming from sleep.
I have created a resume function;
There should be no need to reset the PHY during suspend/resume.
Can you please try your board on v3.13? A lot of cleanup has been done since
3.4.
cheers,
-roger
static void ehci_hcd_omap_resume(struct platform_device *pdev)
{
struct device *dev = pdev-dev;
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct ehci_hcd_omap_platform_data *pdata = dev-platform_data;
if (pdata-phy_reset) {
if (gpio_is_valid(pdata-reset_gpio_port[0]))
gpio_set_value(pdata-reset_gpio_port[0], 0);
if (gpio_is_valid(pdata-reset_gpio_port[1]))
gpio_set_value(pdata-reset_gpio_port[1], 0);
/* Hold the PHY in RESET for enough time till DIR is high */
udelay(100);
}
if (pdata-phy_reset) {
/* Hold the PHY in RESET for enough time till
* PHY is settled and ready
*/
udelay(10);
if (gpio_is_valid(pdata-reset_gpio_port[0]))
gpio_set_value(pdata-reset_gpio_port[0], 1);
if (gpio_is_valid(pdata-reset_gpio_port[1]))
gpio_set_value(pdata-reset_gpio_port[1], 1);
}
}
And linked in the static struct platform_driver ehci_hcd_omap_driver = {
.resume = ehci_hcd_omap_resume,
It calls the function at resume and I can see the line toggle on the scope
but still the same response from the driver of disconnecting the hub.
I have even stepped through ehci_bus_resume (struct usb_hcd *hcd) and it all
seems to be OK with the bringup.
Is there any way to enable more debug so that I can see the path through the
pm and hci code ?
I have enabled dynamic debug in the kernel but when I pass the dyndbg modules
on the command line I don't seem to get any additional output... e.g.
rootfstype=nfs ip=dhcp nohlt no_console_suspend=1 dyndbg= module ehci_hcd +p
; module uhci_hcd +p ; module ohci_hcd +p rw
Marc
--
balbi
--
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VIGTIGE MEDDELELSER
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VIGTIGE MEDDELELSER
Et forsøg er gjort for at logge på fra en ny computer. For sikkerheden i din konto, er vi klar til at åbne en forespørgsel. Venligt Klik på linket nedenfor eller kopiere og indsætte på din webbrowser for god sikkerhed praksis: https://www.formstack.com/forms/?1697374-WXAkNc0aBZ Må ikke ignorere denne besked for at undgå opsigelse af din webmail-konto. Webmail Administration. 192.168.0.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 3/6] drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY Framework
On Monday 03 March 2014 05:08 PM, Kishon Vijay Abraham I wrote:
Adapted omap-usb3 PHY driver to Generic PHY Framework and moved phy-omap-usb3
driver in drivers/usb/phy to drivers/phy and also renamed the file to
phy-ti-pipe3 since this same driver will be used for SATA PHY and
PCIE PHY.
merged 3rd, 4th and 5th patch of this series to linux-phy next.
Thanks
Kishon
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile |1 +
.../phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} | 240
drivers/usb/phy/Kconfig| 11 -
drivers/usb/phy/Makefile |1 -
5 files changed, 158 insertions(+), 106 deletions(-)
rename drivers/{usb/phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} (54%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c7a551c..e3ec7d1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -40,6 +40,17 @@ config OMAP_USB2
The USB OTG controller communicates with the comparator using this
driver.
+config TI_PIPE3
+ tristate TI PIPE3 PHY Driver
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ select GENERIC_PHY
+ select OMAP_CONTROL_USB
+ help
+ Enable this to support the PIPE3 PHY that is part of TI SOCs. This
+ driver takes care of all the PHY functionality apart from comparator.
+ This driver interacts with the OMAP Control PHY Driver to power
+ on/off the PHY.
+
config TWL4030_USB
tristate TWL4030 USB Transceiver Driver
depends on TWL4030_CORE REGULATOR_TWL4030 USB_MUSB_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..32e3f94 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
+obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/phy/phy-ti-pipe3.c
similarity index 54%
rename from drivers/usb/phy/phy-omap-usb3.c
rename to drivers/phy/phy-ti-pipe3.c
index 0c6ba29..67b189d 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -1,5 +1,5 @@
/*
- * omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
+ * phy-ti-pipe3 - PIPE3 PHY driver.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -19,10 +19,11 @@
#include linux/module.h
#include linux/platform_device.h
#include linux/slab.h
-#include linux/usb/omap_usb.h
+#include linux/phy/phy.h
#include linux/of.h
#include linux/clk.h
#include linux/err.h
+#include linux/io.h
#include linux/pm_runtime.h
#include linux/delay.h
#include linux/usb/omap_control_usb.h
@@ -52,17 +53,34 @@
/*
* This is an Empirical value that works, need to confirm the actual
- * value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
- * to be correctly reflected in the USB3PHY_PLL_STATUS register.
+ * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
+ * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
*/
# define PLL_IDLE_TIME 100;
-struct usb_dpll_map {
+struct pipe3_dpll_params {
+ u16 m;
+ u8 n;
+ u8 freq:3;
+ u8 sd;
+ u32 mf;
+};
+
+struct ti_pipe3 {
+ void __iomem*pll_ctrl_base;
+ struct device *dev;
+ struct device *control_dev;
+ struct clk *wkupclk;
+ struct clk *sys_clk;
+ struct clk *optclk;
+};
+
+struct pipe3_dpll_map {
unsigned long rate;
- struct usb_dpll_params params;
+ struct pipe3_dpll_params params;
};
-static struct usb_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
@@ -71,7 +89,18 @@ static struct usb_dpll_map dpll_map[] = {
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
};
-static struct usb_dpll_params *omap_usb3_get_dpll_params(unsigned long rate)
+static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+ return __raw_readl(addr + offset);
+}
+
+static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
+ u32 data)
+{
+ __raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
{
int i;
@@
Re: [PATCH v4 0/8] wilink: add device tree support
On Fri, Feb 28, 2014 at 10:22 AM, Alexandre Belloni alexandre.bell...@free-electrons.com wrote: On 28/02/2014 at 08:26:46 +0100, Yegor Yefremov wrote : What is the state of the series? Who is now responsible for the patches? What issues were still not handled? We probably want to end that discussion before taking those bindings in: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-February/232185.html I've hit the issue, precisely using those bindings. The discussion seems to flow down. The last message was about Mon Feb 17 18:25:11 EST 2014. Btw is TI going to assign a new maintainer for Wilink stuff? As Luca has left TI, the driver is marked as Orphan. Yegor -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] ARM: dts: AM4372: Add USB nodes
Hi Roger,
On 3/6/2014 2:19 PM, Roger Quadros wrote:
Hi George,
On 03/03/2014 03:53 PM, George Cherian wrote:
Add nodes for 2 instances each of
- ocp2scp
- USB PHY control module
- USB PHY
- dwc3_omap
- USB
for AM43xx.
Signed-off-by: George Cherian george.cher...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 99 +++
1 file changed, 99 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 5a7cc38..90408b3 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -698,6 +698,105 @@
edma 11;
dma-names = tx, rx;
};
+
+ am43xx_control_usb2phy1: control-phy@44e10620 {
+ compatible = ti,control-phy-am437usb2;
Since this is the first usage of this compatible ID, we still have room to
change it to be better. Tony's suggestion was to use ti,control-phy-am437-usb2
Please see
http://article.gmane.org/gmane.linux.drivers.devicetree/64833
Okay.
+ reg = 0x44e10620 0x4;
+ reg-names = power;
+ status = disabled;
Why disable something that is within the SoC and does not affect board
configurations?
Question applies for all the nodes in this patch except the ones that come out
on the
SoC pins. e.g. PHY.
Okay
+ };
+
+ am43xx_control_usb2phy2: control-phy@0x44e10628 {
+ compatible = ti,control-phy-am437usb2;
+ reg = 0x44e10628 0x4;
+ reg-names = power;
+ status = disabled;
+ };
+
+ ocp2scp0: ocp2scp@483a8000 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ ti,hwmods = ocp2scp0;
+ status = disabled;
+
+ usb2_phy1: usb2phy1@483a8000 {
should be
okay
usb2_phy1: phy@483a8000 {
+ compatible = ti,am437x-usb2;
+ reg = 0x483a8000 0x8000;
+ ctrl-module = am43xx_control_usb2phy1;
+ clocks = clk_32768_ck,
+usb_otg_ss0_refclk960m;
+ clock-names = usb_phy_cm_clk32k,
+ usb_otg_ss_refclk960m;
clock-names should be platform independent. Better option would be to
modify the usb2 driver to use names like wkupclk and refclk
The phy driver still does devm_get_clk using above clock names and not
wkupclk and refclk.
+ #phy-cells = 0;
+ status = disabled;
+ };
+ };
+
+ ocp2scp1: ocp2scp@483e8000 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ ti,hwmods = ocp2scp1;
+ status = disabled;
+
+ usb2_phy2: usb2phy2@483e8000 {
+ compatible = ti,am437x-usb2;
+ reg = 0x483e8000 0x8000;
+ ctrl-module = am43xx_control_usb2phy2;
+ clocks = clk_32768_ck,
+usb_otg_ss1_refclk960m;
+ clock-names = usb_phy_cm_clk32k,
+ usb_otg_ss_refclk960m;
+ #phy-cells = 0;
+ status = disabled;
+ };
+ };
+
+ dwc3_1: omap_dwc3_1@4838 {
+ compatible = ti,am437x-dwc3;
+ ti,hwmods = usb_otg_ss0;
+ reg = 0x4838 0x1;
+ interrupts = GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH;
+ #address-cells = 1;
+ #size-cells = 1;
+ utmi-mode = 1;
+ ranges;
+ status = disabled;
+
+ usb1: usb@4839 {
+ compatible = synopsys,dwc3;
+ reg = 0x4839 0x17000;
+ interrupts = GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH;
+ usb-phy = usb2_phy1;
shouldn't this be phys = usb2_phy1; ?
At the time of writing this patch phys property is still not in.
Also generic-phy conversion for dwc3 was recently posted by kishon.
+ phy-names = usb2-phy;
what about
maximum-speed =
Re: [PATCH 5/5] doc: Add ti,am437x-dwc3 comaptible for dwc3 glue
Hi Roger, On 3/6/2014 2:25 PM, Roger Quadros wrote: On 03/03/2014 03:53 PM, George Cherian wrote: Add the compatible ti,am437x-dwc3 for dwc3 glue driver. Signed-off-by: George Cherian george.cher...@ti.com --- Documentation/devicetree/bindings/usb/omap-usb.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) The patch order could be the rearranged so that this appears before the am437x bindings are used. cheers, -roger okay will do in v2 diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt index c495135..1d38569 100644 --- a/Documentation/devicetree/bindings/usb/omap-usb.txt +++ b/Documentation/devicetree/bindings/usb/omap-usb.txt @@ -44,7 +44,9 @@ Board specific device node entry }; OMAP DWC3 GLUE - - compatible : Should be ti,dwc3 + - compatible : Should be + * ti,dwc3 for OMAP5 and DRA7 + * ti,am437x-dwc3 for AM437x - ti,hwmods : Should be usb_otg_ss - reg : Address and length of the register set for the device. - interrupts : The irq number of this device that is used to interrupt the -- -George -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH 1/1] arm: dts: am33xx: correcting dt node unit address for usb
DT node's unit address should be its own register offset address to make it a
unique across the system. This patch corrects the incorrect USB entries with
correct register offset for unit address.
Cc: Sebastian Andrzej Siewior bige...@linutronix.de
Cc: Felipe Balbi ba...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
This patch was posted long back (Aug. 30, 2013), below is the archive of the
orginal patch.
https://patchwork.kernel.org/patch/2852163/
---
arch/arm/boot/dts/am33xx.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 7073429..9770e35 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -453,7 +453,7 @@
ti,hwmods = usb_otg_hs;
status = disabled;
- usb_ctrl_mod: control@44e1 {
+ usb_ctrl_mod: control@44e10620 {
compatible = ti,am335x-usb-ctrl-module;
reg = 0x44e10620 0x10
0x44e10648 0x4;
@@ -556,7 +556,7 @@
tx14, tx15;
};
- cppi41dma: dma-controller@07402000 {
+ cppi41dma: dma-controller@47402000 {
compatible = ti,am3359-cppi41;
reg = 0x4740 0x1000
0x47402000 0x1000
--
1.9.0
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Re: [RESEND PATCH 1/1] arm: dts: am33xx: correcting dt node unit address for usb
On 03/06/2014 01:31 PM, Mugunthan V N wrote: DT node's unit address should be its own register offset address to make it a unique across the system. This patch corrects the incorrect USB entries with correct register offset for unit address. Cc: Sebastian Andrzej Siewior bige...@linutronix.de Cc: Felipe Balbi ba...@ti.com Signed-off-by: Mugunthan V N mugunthan...@ti.com Acked-by: Sebastian Andrzej Siewior bige...@linutronix.de Sebastian -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] ARM: dts: AM4372: Add USB nodes
On 03/06/2014 02:27 PM, George Cherian wrote:
Hi Roger,
On 3/6/2014 2:19 PM, Roger Quadros wrote:
Hi George,
On 03/03/2014 03:53 PM, George Cherian wrote:
Add nodes for 2 instances each of
- ocp2scp
- USB PHY control module
- USB PHY
- dwc3_omap
- USB
for AM43xx.
Signed-off-by: George Cherian george.cher...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 99
+++
1 file changed, 99 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 5a7cc38..90408b3 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -698,6 +698,105 @@
edma 11;
dma-names = tx, rx;
};
+
+am43xx_control_usb2phy1: control-phy@44e10620 {
+compatible = ti,control-phy-am437usb2;
Since this is the first usage of this compatible ID, we still have room to
change it to be better. Tony's suggestion was to use
ti,control-phy-am437-usb2
Please see
http://article.gmane.org/gmane.linux.drivers.devicetree/64833
Okay.
+reg = 0x44e10620 0x4;
+reg-names = power;
+status = disabled;
Why disable something that is within the SoC and does not affect board
configurations?
Question applies for all the nodes in this patch except the ones that come
out on the
SoC pins. e.g. PHY.
Okay
+};
+
+am43xx_control_usb2phy2: control-phy@0x44e10628 {
+compatible = ti,control-phy-am437usb2;
+reg = 0x44e10628 0x4;
+reg-names = power;
+status = disabled;
+};
+
+ocp2scp0: ocp2scp@483a8000 {
+compatible = ti,omap-ocp2scp;
+#address-cells = 1;
+#size-cells = 1;
+ranges;
+ti,hwmods = ocp2scp0;
+status = disabled;
+
+usb2_phy1: usb2phy1@483a8000 {
should be
okay
usb2_phy1: phy@483a8000 {
+compatible = ti,am437x-usb2;
+reg = 0x483a8000 0x8000;
+ctrl-module = am43xx_control_usb2phy1;
+clocks = clk_32768_ck,
+ usb_otg_ss0_refclk960m;
+clock-names = usb_phy_cm_clk32k,
+ usb_otg_ss_refclk960m;
clock-names should be platform independent. Better option would be to
modify the usb2 driver to use names like wkupclk and refclk
The phy driver still does devm_get_clk using above clock names and not
wkupclk and refclk.
I'll post a patch soon that takes care of both clock names and the compatible
ids in
the phy-omap-usb2.c driver.
+#phy-cells = 0;
+status = disabled;
+};
+};
+
+ocp2scp1: ocp2scp@483e8000 {
+compatible = ti,omap-ocp2scp;
+#address-cells = 1;
+#size-cells = 1;
+ranges;
+ti,hwmods = ocp2scp1;
+status = disabled;
+
+usb2_phy2: usb2phy2@483e8000 {
+compatible = ti,am437x-usb2;
+reg = 0x483e8000 0x8000;
+ctrl-module = am43xx_control_usb2phy2;
+clocks = clk_32768_ck,
+ usb_otg_ss1_refclk960m;
+clock-names = usb_phy_cm_clk32k,
+ usb_otg_ss_refclk960m;
+#phy-cells = 0;
+status = disabled;
+};
+};
+
+dwc3_1: omap_dwc3_1@4838 {
+compatible = ti,am437x-dwc3;
+ti,hwmods = usb_otg_ss0;
+reg = 0x4838 0x1;
+interrupts = GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH;
+#address-cells = 1;
+#size-cells = 1;
+utmi-mode = 1;
+ranges;
+status = disabled;
+
+usb1: usb@4839 {
+compatible = synopsys,dwc3;
+reg = 0x4839 0x17000;
+interrupts = GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH;
+usb-phy = usb2_phy1;
shouldn't this bephys = usb2_phy1;?
At the time of writing this patch phys property is still not in.
Also generic-phy conversion for dwc3 was recently posted by kishon.
+phy-names = usb2-phy;
what about
maximum-speed = high-speed;
and
dr_mode = otg; ?
Done from board file. Actually maximum-speed I can set here.
dr_mode is a board property.
Is it a known standard that dr_mode must come from board dts?
I think dr_mode can be set here by default. Board can always override if it
needs non otg operation.
cheers,
-roger
+status = disabled;
+};
+};
+
+dwc3_2: omap_dwc3_2@483c {
+compatible = ti,am437x-dwc3;
+ti,hwmods = usb_otg_ss1;
+reg = 0x483c 0x1;
+interrupts = GIC_SPI 178
Re: [PATCHv2 13/14] ARM: OMAP24xx: clock: remove legacy clock data
On 03/05/2014 08:10 PM, Tony Lindgren wrote: * Tony Lindgren t...@atomide.com [140305 09:12]: * Tero Kristo t-kri...@ti.com [140305 00:17]: On 03/04/2014 11:28 PM, Tony Lindgren wrote: * Tero Kristo t-kri...@ti.com [140304 10:58]: On 03/04/2014 07:32 PM, Tony Lindgren wrote: * Tero Kristo t-kri...@ti.com [140304 01:22]: This is no longer needed as clock data is provided through DT. Looks like there's a new error even before applying this patch in the series as I'm now getting the following oops on n8x0. So cannot test this patch yet. Is this with OMAP2 only boot? Yeah that's with omap2 only. That explains it, as previous series was never boot tested in omap2 only config (due to build issues.) I just force pushed the branch with the below additional patch, can you check if it works now? Yes seems to work with that thanks. And with the omap2 legacy clock data removed too, it boots fine on n8x0 and 2430sdp. I suggest you drop the omap3 legacy data patch from this branch as it's not omap2 related and cannot be done yet. Then try to get acks from Paul. And if there are no issues, it seems Mike could take the whole branch as it seems to merge just fine with what I have queued. So for all the patches except for the omap3 legacy data removal, feel free to add: Acked-by: Tony Lindgren t...@atomide.com Found one randconfig error with this series when CONFIG_ARCH_OMAP2 is not set: /drivers/clk/ti/dpll.c:273: undefined reference to `omap2xxx_clkt_dpllcore_init' drivers/clk/ti/dpll.c:311: undefined reference to `clkhwops_omap2xxx_dpll' Yeah, this is in this series. Force pushed a minor update to patch #4 to fix this. I can repost the series if Mike or Paul or someone requests this. -Tero It's also possible the error is the PRM clean up series, but probably in this series based drivers/clk/ti/dpll.c path. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 04/13] phy: ti-pipe3: cleanup clock handling
As this driver is no longer USB specific, use generic clock names.
- Use 'wkupclk', 'sysclk' and 'refclk' clock-names. Update DT binding info.
- Fix PLL_SD_SHIFT from 9 to 10
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Update omap5 usb3_phy device tree node.
CC: Benoît Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 12 ++
arch/arm/boot/dts/omap5.dtsi | 7 ++-
drivers/phy/phy-ti-pipe3.c | 55
3 files changed, 46 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 28e674b..8d13349 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -59,6 +59,12 @@ Required properties:
filled in reg.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+ clock-names.
+ - clock-names: should include:
+ * wkupclk - wakup clock.
+ * sysclk - system clock.
+ * refclk - reference clock.
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
@@ -74,4 +80,10 @@ usb3phy@4a084400 {
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_usb;
#phy-cells = 0;
+ clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+ clock-names = wkupclk,
+ sysclk,
+ refclk;
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 859a800..e47601a 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -778,7 +778,12 @@
0x4a084800 0x64,
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_usb3phy;
+ clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+ clock-names = wkupclk,
+ sysclk,
+ refclk;
#phy-cells = 0;
};
};
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index fd029b1..211703c 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -45,7 +45,7 @@
#definePLL_SELFREQDCO_MASK 0x000E
#definePLL_SELFREQDCO_SHIFT0x1
#definePLL_SD_MASK 0x0003FC00
-#definePLL_SD_SHIFT0x9
+#definePLL_SD_SHIFT10
#defineSET_PLL_GO 0x1
#definePLL_TICOPWDN0x1
#definePLL_LOCK0x2
@@ -72,7 +72,7 @@ struct ti_pipe3 {
struct device *control_dev;
struct clk *wkupclk;
struct clk *sys_clk;
- struct clk *optclk;
+ struct clk *refclk;
};
struct pipe3_dpll_map {
@@ -270,23 +270,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+ dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
- clk_prepare(phy-wkupclk);
- phy-optclk = devm_clk_get(phy-dev, usb_otg_ss_refclk960m);
- if (IS_ERR(phy-optclk)) {
- dev_err(pdev-dev, unable to get usb_otg_ss_refclk960m\n);
- return PTR_ERR(phy-optclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
}
- clk_prepare(phy-optclk);
- phy-sys_clk = devm_clk_get(phy-dev, sys_clkin);
+ phy-sys_clk = devm_clk_get(phy-dev, sysclk);
if (IS_ERR(phy-sys_clk)) {
- pr_err(%s: unable to get sys_clkin\n, __func__);
+ dev_err(pdev-dev, unable to get sysclk\n);
return -EINVAL;
}
@@ -326,10 +324,6 @@ static int ti_pipe3_probe(struct platform_device *pdev)
static int ti_pipe3_remove(struct platform_device *pdev)
{
- struct ti_pipe3 *phy = platform_get_drvdata(pdev);
-
-
[PATCH v2 09/13] phy: omap: Depend on OMAP_OCP2SCP bus driver
The OMAP_USB2 and OMAP_PIPE3 PHY devices will not be detected if the OMAP_OCP2SCP bus driver is not present. Make them depend on it. Signed-off-by: Roger Quadros rog...@ti.com --- drivers/phy/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index fe8c009..2aead8b 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -47,6 +47,7 @@ config OMAP_USB2 depends on USB_PHY select GENERIC_PHY select OMAP_CONTROL_PHY + depends on OMAP_OCP2SCP help Enable this to support the transceiver that is part of SOC. This driver takes care of all the PHY functionality apart from comparator. @@ -58,6 +59,7 @@ config TI_PIPE3 depends on ARCH_OMAP2PLUS || COMPILE_TEST select GENERIC_PHY select OMAP_CONTROL_PHY + depends on OMAP_OCP2SCP help Enable this to support the PIPE3 PHY that is part of TI SOCs. This driver takes care of all the PHY functionality apart from comparator. -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 03/13] phy: omap-control: update dra7 and am437 usb2 bindings
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
drivers/phy/phy-omap-control.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 5c5b1b0..28e674b 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,9 +9,9 @@ Required properties:
e.g. USB2_PHY on OMAP5.
ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-dra7-usb2 - if it has power down register like USB2 PHY on
DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-am437-usb2 - if it has power down register like USB2 PHY on
AM437 platform.
- reg : Address and length of the register set for the device. It contains
the address of otghs_control for control-phy-otghs or power register
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-dra7-usb2,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-am437-usb2,
.data = am437usb2_data,
},
{},
--
1.8.3.2
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[PATCH v2 10/13] ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
From: Keshava Munegowda keshava_mgo...@ti.com
Create hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index e297d62..227a69f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -1726,6 +1726,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
},
};
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+/* ocp2scp3 */
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
+/* l4_cfg - ocp2scp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
+ .master = omap54xx_l4_cfg_hwmod,
+ .slave = omap54xx_ocp2scp3_hwmod,
+ .clk= l4_root_clk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
+ .name = ocp2scp3,
+ .class = omap54xx_ocp2scp_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs =
OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+ .context_offs =
OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'sata' class
+ * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
+ .sysc_offs = 0x,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
+ .name = sata,
+ .sysc = omap54xx_sata_sysc,
+};
+
+/* sata */
+static struct omap_hwmod omap54xx_sata_hwmod = {
+ .name = sata,
+ .class = omap54xx_sata_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = func_48m_fclk,
+ .mpu_rt_idx = 1,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_cfg - sata */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
+ .master = omap54xx_l4_cfg_hwmod,
+ .slave = omap54xx_sata_hwmod,
+ .clk= l3_iclk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
/*
* Interfaces
@@ -2399,6 +2470,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[]
__initdata = {
omap54xx_l4_cfg__usb_tll_hs,
omap54xx_l4_cfg__usb_otg_ss,
omap54xx_l4_wkup__wd_timer2,
+ omap54xx_l4_cfg__ocp2scp3,
+ omap54xx_l4_cfg__sata,
NULL,
};
--
1.8.3.2
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[PATCH v2 12/13] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods
From: Nikhil Devshatwar nikhil...@ti.com
Add hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Nikhil Devshatwar nikhil...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 18f333c..3c9a430 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
},
};
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
+
+/* l4_cfg - ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+ .master = dra7xx_l4_cfg_hwmod,
+ .slave = dra7xx_ocp2scp3_hwmod,
+ .clk= l4_root_clk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+ .name = ocp2scp3,
+ .class = dra7xx_ocp2scp_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs =
DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+ .context_offs =
DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
/*
* 'qspi' class
*
@@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
};
/* sata */
-static struct omap_hwmod_opt_clk sata_opt_clks[] = {
- { .role = ref_clk, .clk = sata_ref_clk },
-};
static struct omap_hwmod dra7xx_sata_hwmod = {
.name = sata,
@@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.clkdm_name = l3init_clkdm,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = func_48m_fclk,
+ .mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = sata_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
};
/*
@@ -2683,6 +2703,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
dra7xx_l4_per1__mmc4,
dra7xx_l4_cfg__mpu,
dra7xx_l4_cfg__ocp2scp1,
+ dra7xx_l4_cfg__ocp2scp3,
dra7xx_l3_main_1__qspi,
dra7xx_l4_cfg__sata,
dra7xx_l4_cfg__smartreflex_core,
--
1.8.3.2
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[PATCH v2 08/13] phy: ti-pipe3: Fix suspend/resume and module reload
Due to Errata i783, SATA breaks if its DPLL is idled. The recommeded workaround to issue a softreset to the SATA controller doesn't seem to work. Here we just prevent SATA DPLL from Idling and hence avoid the issue altogether. Signed-off-by: Roger Quadros rog...@ti.com --- drivers/phy/phy-ti-pipe3.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index 12cc900..5913676 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -238,6 +238,10 @@ static int ti_pipe3_exit(struct phy *x) u32 val; unsigned long timeout; + /* SATA DPLL can't be powered down due to Errata i783 */ + if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-sata)) + return 0; + /* Put DPLL in IDLE mode */ val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2); val |= PLL_IDLE; -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 13/13] ARM: dts: dra7: add OCP2SCP3 and SATA nodes
From: Balaji T K balaj...@ti.com
Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9e3caf3..597979b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -772,6 +772,45 @@
dma-names = tx0, rx0;
status = disabled;
};
+
+ omap_control_sata: control-phy@4a002374 {
+ compatible = ti,control-phy-pipe3;
+ reg = 0x4a002374 0x4;
+ reg-names = power;
+ clocks = sys_clkin1;
+ clock-names = sysclk;
+ };
+
+ /* OCP2SCP3 */
+ ocp2scp@4a09 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ reg = 0x4a09 0x20;
+ ti,hwmods = ocp2scp3;
+ sata_phy: phy@4A096000 {
+ compatible = ti,phy-pipe3-sata;
+ reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+ reg-names = phy_rx, phy_tx, pll_ctrl;
+ ctrl-module = omap_control_sata;
+ clocks = sys_clkin1;
+ clock-names = sysclk;
+ #phy-cells = 0;
+ };
+ };
+
+ sata: sata@4a141100 {
+ compatible = snps,dwc-ahci;
+ reg = 0x4a14 0x1100, 0x4a141100 0x7;
+ interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
+ phys = sata_phy;
+ phy-names = sata-phy;
+ clocks = sata_ref_clk;
+ ti,hwmods = sata;
+ };
};
};
--
1.8.3.2
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[PATCH v2 11/13] ARM: dts: omap5: add sata node
From: Balaji T K balaj...@ti.com
Add support for sata.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e47601a..b398cff 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -828,6 +828,46 @@
#thermal-sensor-cells = 1;
};
+
+ omap_control_sata: control-phy@4a002374 {
+ compatible = ti,control-phy-pipe3;
+ reg = 0x4a002374 0x4;
+ reg-names = power;
+ clocks = sys_clkin;
+ clock-names = sysclk;
+ };
+
+ /* OCP2SCP3 */
+ ocp2scp@4a09 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ reg = 0x4a09 0x20;
+ ranges;
+ ti,hwmods = ocp2scp3;
+ sata_phy: phy@4a096000 {
+ compatible = ti,phy-pipe3-sata;
+ reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+ reg-names = phy_rx, phy_tx, pll_ctrl;
+ ctrl-module = omap_control_sata;
+ clocks = sys_clkin;
+ clock-names = sysclk;
+ #phy-cells = 0;
+ };
+ };
+
+ sata: sata@4a141100 {
+ compatible = snps,dwc-ahci;
+ reg = 0x4a14 0x1100, 0x4a141100 0x7;
+ interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
+ phys = sata_phy;
+ phy-names = sata-phy;
+ clocks = sata_ref_clk;
+ ti,hwmods = sata;
+ };
+
};
};
--
1.8.3.2
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[PATCH v2 05/13] phy: ti-pipe3: Add SATA DPLL support
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Update the DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 3 +-
drivers/phy/phy-ti-pipe3.c | 76 +---
2 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 8d13349..2c2d66a 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -53,7 +53,8 @@ usb2phy@4a0ad080 {
TI PIPE3 PHY
Required properties:
- - compatible: Should be ti,phy-usb3. ti,omap-usb3 is deprecated.
+ - compatible: Should be ti,phy-usb3 or ti,phy-pipe3-sata.
+ ti,omap-usb3 is deprecated.
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in reg.
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 211703c..f141237 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -66,6 +66,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct ti_pipe3 {
void __iomem*pll_ctrl_base;
struct device *dev;
@@ -73,20 +78,27 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct pipe3_dpll_map *dpll_map;
};
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{2000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{2600, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { },/* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {1200, {1000, 7, 4, 6, 0} },/* 12 MHz */
+ {1680, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {1920, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {2000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {2600, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {3840, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { },/* Terminator */
};
static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
@@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr,
unsigned offset,
__raw_writel(data, addr + offset);
}
-static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = phy-dpll_map;
- for (i = 0; i ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return dpll_map[i].params;
+ rate = clk_get_rate(phy-sys_clk);
+
+ for (; dpll_map-rate; dpll_map++) {
+ if (rate == dpll_map-rate)
+ return dpll_map-params;
}
+ dev_err(phy-dev, No DPLL configuration for %lu Hz SYS CLK\n, rate);
+
return NULL;
}
@@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
{
u32 val;
- unsigned long rate;
struct pipe3_dpll_params *dpll_params;
- rate = clk_get_rate(phy-sys_clk);
- dpll_params = ti_pipe3_get_dpll_params(rate);
- if (!dpll_params) {
- dev_err(phy-dev,
- No DPLL configuration for %lu Hz SYS CLK\n, rate);
+ dpll_params = ti_pipe3_get_dpll_params(phy);
+ if (!dpll_params)
return -EINVAL;
- }
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION1);
val = ~PLL_REGN_MASK;
@@ -244,6 +256,10 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id ti_pipe3_id_table[];
+#endif
+
static int ti_pipe3_probe(struct platform_device *pdev)
{
struct ti_pipe3 *phy;
@@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
+
[PATCH v2 07/13] phy: ti-pipe3: streamline PHY operations
Limit .power_on() and .power_off() to just control the
PHY power and not the DPLL. The DPLL will be enabled
in .init() and idled in .exit().
Don't reprogram the DPLL if it has been already locked
by the bootloader. This fixes a problem with SATA, where
it fails if SATA was used by the bootloader.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 114 +
1 file changed, 63 insertions(+), 51 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index baa3f78d..12cc900 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -47,7 +47,8 @@
#definePLL_SD_MASK 0x0003FC00
#definePLL_SD_SHIFT10
#defineSET_PLL_GO 0x1
-#definePLL_TICOPWDN0x1
+#define PLL_LDOPWDNBIT(15)
+#define PLL_TICOPWDN BIT(16)
#definePLL_LOCK0x2
#definePLL_IDLE0x1
@@ -56,7 +57,8 @@
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
* to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
*/
-# define PLL_IDLE_TIME 100;
+#define PLL_IDLE_TIME 100 /* in milliseconds */
+#define PLL_LOCK_TIME 100 /* in milliseconds */
struct pipe3_dpll_params {
u16 m;
@@ -132,24 +134,6 @@ static struct pipe3_dpll_params
*ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
static int ti_pipe3_power_off(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int val;
- int timeout = PLL_IDLE_TIME;
-
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
- val |= PLL_IDLE;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- do {
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
- if (val PLL_TICOPWDN)
- break;
- udelay(5);
- } while (--timeout);
-
- if (!timeout) {
- dev_err(phy-dev, power off failed\n);
- return -EBUSY;
- }
omap_control_phy_power(phy-control_dev, 0);
@@ -159,44 +143,34 @@ static int ti_pipe3_power_off(struct phy *x)
static int ti_pipe3_power_on(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int val;
- int timeout = PLL_IDLE_TIME;
-
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
- val = ~PLL_IDLE;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
- do {
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
- if (!(val PLL_TICOPWDN))
- break;
- udelay(5);
- } while (--timeout);
-
- if (!timeout) {
- dev_err(phy-dev, power on failed\n);
- return -EBUSY;
- }
+ omap_control_phy_power(phy-control_dev, 1);
return 0;
}
-static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
+static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
{
u32 val;
unsigned long timeout;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_GO, SET_PLL_GO);
-
- timeout = jiffies + msecs_to_jiffies(20);
+ timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
do {
+ cpu_relax();
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
if (val PLL_LOCK)
break;
- } while (!WARN_ON(time_after(jiffies, timeout)));
+ } while (!time_after(jiffies, timeout));
+
+ if (!(val PLL_LOCK)) {
+ dev_err(phy-dev, DPLL failed to lock\n);
+ return -EBUSY;
+ }
+
+ return 0;
}
-static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
+static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
{
u32 val;
struct pipe3_dpll_params *dpll_params;
@@ -230,27 +204,65 @@ static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
val |= dpll_params-sd PLL_SD_SHIFT;
ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION3, val);
- ti_pipe3_dpll_relock(phy);
+ ti_pipe3_writel(phy-pll_ctrl_base, PLL_GO, SET_PLL_GO);
- return 0;
+ return ti_pipe3_dpll_wait_lock(phy);
}
static int ti_pipe3_init(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int ret;
+ u32 val;
+ int ret = 0;
- ret = ti_pipe3_dpll_lock(phy);
- if (ret)
- return ret;
+ /* Bring it out of IDLE if it is IDLE */
+ val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
+ if (val PLL_IDLE) {
+ val = ~PLL_IDLE;
+ ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
+ ret = ti_pipe3_dpll_wait_lock(phy);
+ }
- omap_control_phy_power(phy-control_dev, 1);
+ /* Program the DPLL only if not locked */
+ val =
[PATCH v2 00/13] ARM: OMAP: SATA support for OMAP5 DRA7
Hi, This series adds SATA support for OMAP5 uevm and DRA7-evm boards. - Cleans up the ti-pipe3 PHY driver - Adds SATA DPLL support to ti-pipe3 PHY driver - Adds SATA nodes to hwmod and SoC DT data Patches are based on 3.14-rc4 with balbi/next, linux-phy/next and omap-for-v3.15/dt merged on top.. To test SATA you will also need [1]. [1] - http://article.gmane.org/gmane.comp.hardware.netbook.arm.sunxi/7285 Changelog: v2 - use 'depends on' instead of 'select' OCP2SCP bus driver. - Changed DT bindings for dra7-usb2 and am437-usb2 phy. cheers, -roger --- Balaji T K (2): ARM: dts: omap5: add sata node ARM: dts: dra7: add OCP2SCP3 and SATA nodes Keshava Munegowda (1): ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods Kishon Vijay Abraham I (1): phy: rename struct omap_control_usb to struct omap_control_phy Nikhil Devshatwar (1): ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods Roger Quadros (8): phy: omap-control: Update DT binding information phy: omap-control: update dra7 and am437 usb2 bindings phy: ti-pipe3: cleanup clock handling phy: ti-pipe3: Add SATA DPLL support phy: ti-pipe3: Don't get 'wkupclk' and 'refclk' for SATA PHY phy: ti-pipe3: streamline PHY operations phy: ti-pipe3: Fix suspend/resume and module reload phy: omap: Depend on OMAP_OCP2SCP bus driver Documentation/devicetree/bindings/phy/ti-phy.txt | 40 ++- Documentation/devicetree/bindings/usb/omap-usb.txt | 24 -- arch/arm/boot/dts/dra7.dtsi| 39 +++ arch/arm/boot/dts/omap5.dtsi | 47 ++- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 + arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 +- drivers/phy/Kconfig| 16 +- drivers/phy/Makefile | 1 + drivers/phy/phy-omap-control.c | 320 + drivers/phy/phy-omap-usb2.c| 8 +- drivers/phy/phy-ti-pipe3.c | 269 ++--- drivers/usb/musb/omap2430.c| 2 +- drivers/usb/phy/Kconfig| 10 - drivers/usb/phy/Makefile | 1 - drivers/usb/phy/phy-omap-control.c | 319 include/linux/phy/omap_control_phy.h | 89 ++ include/linux/usb/omap_control_usb.h | 89 -- 17 files changed, 815 insertions(+), 563 deletions(-) create mode 100644 drivers/phy/phy-omap-control.c delete mode 100644 drivers/usb/phy/phy-omap-control.c create mode 100644 include/linux/phy/omap_control_phy.h delete mode 100644 include/linux/usb/omap_control_usb.h -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 01/13] phy: rename struct omap_control_usb to struct omap_control_phy
From: Kishon Vijay Abraham I kis...@ti.com
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/Kconfig | 14 +-
drivers/phy/Makefile | 1 +
drivers/phy/phy-omap-control.c | 320 +++
drivers/phy/phy-omap-usb2.c | 8 +-
drivers/phy/phy-ti-pipe3.c | 8 +-
drivers/usb/musb/omap2430.c | 2 +-
drivers/usb/phy/Kconfig | 10 --
drivers/usb/phy/Makefile | 1 -
drivers/usb/phy/phy-omap-control.c | 319 --
include/linux/phy/omap_control_phy.h | 89 ++
include/linux/usb/omap_control_usb.h | 89 --
11 files changed, 431 insertions(+), 430 deletions(-)
create mode 100644 drivers/phy/phy-omap-control.c
delete mode 100644 drivers/usb/phy/phy-omap-control.c
create mode 100644 include/linux/phy/omap_control_phy.h
delete mode 100644 include/linux/usb/omap_control_usb.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1b607d7..fe8c009 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -31,12 +31,22 @@ config PHY_MVEBU_SATA
depends on OF
select GENERIC_PHY
+config OMAP_CONTROL_PHY
+ tristate OMAP CONTROL PHY Driver
+ help
+ Enable this to add support for the PHY part present in the control
+ module. This driver has API to power on the USB2 PHY and to write to
+ the mailbox. The mailbox is present only in omap4 and the register to
+ power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
+ additional register to power on USB3 PHY/SATA PHY/PCIE PHY
+ (PIPE3 PHY).
+
config OMAP_USB2
tristate OMAP USB2 PHY Driver
depends on ARCH_OMAP2PLUS
depends on USB_PHY
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the transceiver that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator.
@@ -47,7 +57,7 @@ config TI_PIPE3
tristate TI PIPE3 PHY Driver
depends on ARCH_OMAP2PLUS || COMPILE_TEST
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the PIPE3 PHY that is part of TI SOCs. This
driver takes care of all the PHY functionality apart from comparator.
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index ecf0d3f..8da05a8 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
+obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
new file mode 100644
index 000..17fc200
--- /dev/null
+++ b/drivers/phy/phy-omap-control.c
@@ -0,0 +1,320 @@
+/*
+ * omap-control-phy.c - The PHY part of control module.
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I kis...@ti.com
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/err.h
+#include linux/io.h
+#include linux/clk.h
+#include linux/phy/omap_control_phy.h
+
+/**
+ * omap_control_phy_power - power on/off the phy using control module reg
+ * @dev: the control module device
+ * @on: 0 or 1, based on powering on or off the PHY
+ */
+void omap_control_phy_power(struct device *dev, int on)
+{
+ u32 val;
+ unsigned long rate;
+ struct omap_control_phy *control_phy;
+
+ if (IS_ERR(dev) || !dev) {
+ pr_err(%s: invalid device\n, __func__);
+ return;
+ }
+
+
Re: [PATCH v2 00/13] ARM: OMAP: SATA support for OMAP5 DRA7
On 03/06/2014 04:22 PM, Roger Quadros wrote:
Hi,
This series adds SATA support for OMAP5 uevm and DRA7-evm boards.
- Cleans up the ti-pipe3 PHY driver
- Adds SATA DPLL support to ti-pipe3 PHY driver
- Adds SATA nodes to hwmod and SoC DT data
Patches are based on 3.14-rc4 with balbi/next, linux-phy/next and
omap-for-v3.15/dt merged on top..
To test SATA you will also need [1].
[1] - http://article.gmane.org/gmane.comp.hardware.netbook.arm.sunxi/7285
Changelog:
v2
- use 'depends on' instead of 'select' OCP2SCP bus driver.
- Changed DT bindings for dra7-usb2 and am437-usb2 phy.
cheers,
-roger
---
Balaji T K (2):
ARM: dts: omap5: add sata node
ARM: dts: dra7: add OCP2SCP3 and SATA nodes
Keshava Munegowda (1):
ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
Kishon Vijay Abraham I (1):
phy: rename struct omap_control_usb to struct omap_control_phy
Nikhil Devshatwar (1):
ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods
Roger Quadros (8):
phy: omap-control: Update DT binding information
phy: omap-control: update dra7 and am437 usb2 bindings
phy: ti-pipe3: cleanup clock handling
phy: ti-pipe3: Add SATA DPLL support
phy: ti-pipe3: Don't get 'wkupclk' and 'refclk' for SATA PHY
phy: ti-pipe3: streamline PHY operations
phy: ti-pipe3: Fix suspend/resume and module reload
phy: omap: Depend on OMAP_OCP2SCP bus driver
Documentation/devicetree/bindings/phy/ti-phy.txt | 40 ++-
Documentation/devicetree/bindings/usb/omap-usb.txt | 24 --
arch/arm/boot/dts/dra7.dtsi| 39 +++
arch/arm/boot/dts/omap5.dtsi | 47 ++-
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 +
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 +-
drivers/phy/Kconfig| 16 +-
drivers/phy/Makefile | 1 +
drivers/phy/phy-omap-control.c | 320
+
drivers/phy/phy-omap-usb2.c| 8 +-
drivers/phy/phy-ti-pipe3.c | 269 ++---
drivers/usb/musb/omap2430.c| 2 +-
drivers/usb/phy/Kconfig| 10 -
drivers/usb/phy/Makefile | 1 -
drivers/usb/phy/phy-omap-control.c | 319
include/linux/phy/omap_control_phy.h | 89 ++
include/linux/usb/omap_control_usb.h | 89 --
17 files changed, 815 insertions(+), 563 deletions(-)
create mode 100644 drivers/phy/phy-omap-control.c
delete mode 100644 drivers/usb/phy/phy-omap-control.c
create mode 100644 include/linux/phy/omap_control_phy.h
delete mode 100644 include/linux/usb/omap_control_usb.h
oops. forgot to add -M :(.
I'll resend just the 1st patch since it contains the file rename.
updated diffstat is below.
Documentation/devicetree/bindings/phy/ti-phy.txt | 40 ++-
Documentation/devicetree/bindings/usb/omap-usb.txt | 24 --
arch/arm/boot/dts/dra7.dtsi| 39 +++
arch/arm/boot/dts/omap5.dtsi | 47 +++-
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++-
drivers/phy/Kconfig| 16 +-
drivers/phy/Makefile | 1 +
drivers/{usb = }/phy/phy-omap-control.c | 169 ++---
drivers/phy/phy-omap-usb2.c| 8 +-
drivers/phy/phy-ti-pipe3.c | 269 +
drivers/usb/musb/omap2430.c| 2 +-
drivers/usb/phy/Kconfig| 10 -
drivers/usb/phy/Makefile | 1 -
.../omap_control_usb.h = phy/omap_control_phy.h} | 36 +--
15 files changed, 509 insertions(+), 257 deletions(-)
rename drivers/{usb = }/phy/phy-omap-control.c (53%)
rename include/linux/{usb/omap_control_usb.h = phy/omap_control_phy.h} (68%)
cheers,
-roger
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[PATCH v2 06/13] phy: ti-pipe3: Don't get 'wkupclk' and 'refclk' for SATA PHY
SATA PHY doesn't need 'wkupclk; and 'refclk' so don't
try to get them for SATA PHY.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index f141237..baa3f78d 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -294,16 +294,22 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
- if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get wkupclk\n);
- return PTR_ERR(phy-wkupclk);
- }
+ if (!of_device_is_compatible(node, ti,phy-pipe3-sata)) {
+
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
+ if (IS_ERR(phy-wkupclk)) {
+ dev_err(pdev-dev, unable to get wkupclk\n);
+ return PTR_ERR(phy-wkupclk);
+ }
- phy-refclk = devm_clk_get(phy-dev, refclk);
- if (IS_ERR(phy-refclk)) {
- dev_err(pdev-dev, unable to get refclk\n);
- return PTR_ERR(phy-refclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
+ }
+ } else {
+ phy-wkupclk = ERR_PTR(-ENODEV);
+ phy-refclk = ERR_PTR(-ENODEV);
}
phy-sys_clk = devm_clk_get(phy-dev, sysclk);
--
1.8.3.2
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[PATCH v2 02/13] phy: omap-control: Update DT binding information
Move omap-control binding information to the right location.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 25 ++
Documentation/devicetree/bindings/usb/omap-usb.txt | 24 -
2 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index f671163..5c5b1b0 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -1,5 +1,30 @@
TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
+OMAP CONTROL PHY
+
+Required properties:
+ - compatible: Should be one of
+ ti,control-phy-otghs - if it has otghs_control mailbox register as on OMAP4.
+ ti,control-phy-usb2 - if it has Power down bit in control_dev_conf register
+e.g. USB2_PHY on OMAP5.
+ ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
+e.g. USB3 PHY and SATA PHY on OMAP5.
+ ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+DRA7 platform.
+ ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+AM437 platform.
+ - reg : Address and length of the register set for the device. It contains
+ the address of otghs_control for control-phy-otghs or power register
+ for other types.
+ - reg-names: should be otghs_control control-phy-otghs and power for
+ other types.
+
+omap_control_usb: omap-control-usb@4a002300 {
+compatible = ti,control-phy-otghs;
+reg = 0x4a00233c 0x4;
+reg-names = otghs_control;
+};
+
OMAP USB2 PHY
Required properties:
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index c495135..38b2fae 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -76,27 +76,3 @@ omap_dwc3 {
ranges;
};
-OMAP CONTROL USB
-
-Required properties:
- - compatible: Should be one of
- ti,control-phy-otghs - if it has otghs_control mailbox register as on OMAP4.
- ti,control-phy-usb2 - if it has Power down bit in control_dev_conf register
- e.g. USB2_PHY on OMAP5.
- ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
- e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
- DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
- AM437 platform.
- - reg : Address and length of the register set for the device. It contains
- the address of otghs_control for control-phy-otghs or power register
- for other types.
- - reg-names: should be otghs_control control-phy-otghs and power for
- other types.
-
-omap_control_usb: omap-control-usb@4a002300 {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
-};
--
1.8.3.2
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[PATCH v2 01/13][RESEND] phy: rename struct omap_control_usb to struct omap_control_phy
From: Kishon Vijay Abraham I kis...@ti.com
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/Kconfig| 14 +-
drivers/phy/Makefile | 1 +
drivers/{usb = }/phy/phy-omap-control.c | 165 +++--
drivers/phy/phy-omap-usb2.c| 8 +-
drivers/phy/phy-ti-pipe3.c | 8 +-
drivers/usb/musb/omap2430.c| 2 +-
drivers/usb/phy/Kconfig| 10 --
drivers/usb/phy/Makefile | 1 -
.../omap_control_usb.h = phy/omap_control_phy.h} | 36 ++---
9 files changed, 123 insertions(+), 122 deletions(-)
rename drivers/{usb = }/phy/phy-omap-control.c (55%)
rename include/linux/{usb/omap_control_usb.h = phy/omap_control_phy.h} (68%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1b607d7..fe8c009 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -31,12 +31,22 @@ config PHY_MVEBU_SATA
depends on OF
select GENERIC_PHY
+config OMAP_CONTROL_PHY
+ tristate OMAP CONTROL PHY Driver
+ help
+ Enable this to add support for the PHY part present in the control
+ module. This driver has API to power on the USB2 PHY and to write to
+ the mailbox. The mailbox is present only in omap4 and the register to
+ power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
+ additional register to power on USB3 PHY/SATA PHY/PCIE PHY
+ (PIPE3 PHY).
+
config OMAP_USB2
tristate OMAP USB2 PHY Driver
depends on ARCH_OMAP2PLUS
depends on USB_PHY
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the transceiver that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator.
@@ -47,7 +57,7 @@ config TI_PIPE3
tristate TI PIPE3 PHY Driver
depends on ARCH_OMAP2PLUS || COMPILE_TEST
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the PIPE3 PHY that is part of TI SOCs. This
driver takes care of all the PHY functionality apart from comparator.
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index ecf0d3f..8da05a8 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
+obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
similarity index 55%
rename from drivers/usb/phy/phy-omap-control.c
rename to drivers/phy/phy-omap-control.c
index e725318..17fc200 100644
--- a/drivers/usb/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -1,5 +1,5 @@
/*
- * omap-control-usb.c - The USB part of control module.
+ * omap-control-phy.c - The PHY part of control module.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -24,36 +24,36 @@
#include linux/err.h
#include linux/io.h
#include linux/clk.h
-#include linux/usb/omap_control_usb.h
+#include linux/phy/omap_control_phy.h
/**
- * omap_control_usb_phy_power - power on/off the phy using control module reg
+ * omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
*/
-void omap_control_usb_phy_power(struct device *dev, int on)
+void omap_control_phy_power(struct device *dev, int on)
{
u32 val;
unsigned long rate;
- struct omap_control_usb *control_usb;
+ struct omap_control_phy *control_phy;
if (IS_ERR(dev) || !dev) {
pr_err(%s: invalid device\n, __func__);
return;
}
- control_usb = dev_get_drvdata(dev);
- if (!control_usb) {
- dev_err(dev, %s: invalid control usb device\n, __func__);
+ control_phy = dev_get_drvdata(dev);
+ if (!control_phy) {
+ dev_err(dev, %s: invalid control phy device\n, __func__);
return;
}
- if
Re: [PATCH] ARM: OMAP2+: Use handle_fasteoi_irq for INTC interrupt handling
On Mon, 2014-03-03 at 09:49 -0800, Tony Lindgren wrote: 1. CPSW device asserts TX IRQ 2. CPSW device asserts RX IRQ 3. INTC interrupts CPU, TX IRQ marked as active 4. omap_intc_handle_irq ACKs TX IRQ on the INTC 5. INTC marks RX IRQ as active 6. omap_intc_handle_irq calls cpsw_interrupt 7. cpsw_interrupt disables RX+TX IRQ in CPSW device 8. cpsw_interrupt disables RX+TX IRQ in INTC (the IRQs are masked) 9.. omap_intc_handle_irq sees no unmasked IRQs are pending and returns 10. INTC interrupts CPU, RX IRQ marked as pending 11. omap_intc_handle_irq sees no unmasked IRQs are pending and returns 12. Go to step 10 The problem arises in step 8 where an active IRQ is masked. This will not make it inactive in the INTC but it will be cleared from the pending IRQ registers - this is the register that omap_intc_handle_irq uses to decide which IRQ is active. OK thanks for the info. Looking at your trace above it seems like the two separate TX and RX INTC interrupts are not really treated as separate interrupts in the cpsw driver. It seems the real fix is to fix up the cpsw interrupt handler so it's not racy. It seems that at least step 7 and 8 above should be handled separately for TX and RX based on the INTC interrupts. Looking in drivers/net/ethernet, it looks like a quite common pattern is to handle both RXx and TX interrupts with the same handler, which will disable both interrupts and then hand off to napi. The cpsw driver works the same way, so shouldn't this work on omap? From the INTC point of view we should just have standard level IRQ handling for each interrupt, right? INTC does not need to know about driver specific coordination between two separate interrupts. The problem is that the INTC is not doing 100% level IRQ handling combined with the way we handle the INTC during interrupts. When a IRQ has become active on the INTC it will stay active until we acknowledge it, even if it is masked or de-asserted. My patch does not fix the problem when the active interrupt was de-asserted, so I am looking into other ways of dealing with it. Stefan
[PATCH v2 12/13] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods
From: Nikhil Devshatwar nikhil...@ti.com
Add hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Nikhil Devshatwar nikhil...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 18f333c..3c9a430 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
},
};
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
+
+/* l4_cfg - ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+ .master = dra7xx_l4_cfg_hwmod,
+ .slave = dra7xx_ocp2scp3_hwmod,
+ .clk= l4_root_clk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+ .name = ocp2scp3,
+ .class = dra7xx_ocp2scp_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs =
DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+ .context_offs =
DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
/*
* 'qspi' class
*
@@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
};
/* sata */
-static struct omap_hwmod_opt_clk sata_opt_clks[] = {
- { .role = ref_clk, .clk = sata_ref_clk },
-};
static struct omap_hwmod dra7xx_sata_hwmod = {
.name = sata,
@@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.clkdm_name = l3init_clkdm,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = func_48m_fclk,
+ .mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = sata_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
};
/*
@@ -2683,6 +2703,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
dra7xx_l4_per1__mmc4,
dra7xx_l4_cfg__mpu,
dra7xx_l4_cfg__ocp2scp1,
+ dra7xx_l4_cfg__ocp2scp3,
dra7xx_l3_main_1__qspi,
dra7xx_l4_cfg__sata,
dra7xx_l4_cfg__smartreflex_core,
--
1.8.3.2
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[PATCH v2 11/13] ARM: dts: omap5: add sata node
From: Balaji T K balaj...@ti.com
Add support for sata.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e47601a..b398cff 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -828,6 +828,46 @@
#thermal-sensor-cells = 1;
};
+
+ omap_control_sata: control-phy@4a002374 {
+ compatible = ti,control-phy-pipe3;
+ reg = 0x4a002374 0x4;
+ reg-names = power;
+ clocks = sys_clkin;
+ clock-names = sysclk;
+ };
+
+ /* OCP2SCP3 */
+ ocp2scp@4a09 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ reg = 0x4a09 0x20;
+ ranges;
+ ti,hwmods = ocp2scp3;
+ sata_phy: phy@4a096000 {
+ compatible = ti,phy-pipe3-sata;
+ reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+ reg-names = phy_rx, phy_tx, pll_ctrl;
+ ctrl-module = omap_control_sata;
+ clocks = sys_clkin;
+ clock-names = sysclk;
+ #phy-cells = 0;
+ };
+ };
+
+ sata: sata@4a141100 {
+ compatible = snps,dwc-ahci;
+ reg = 0x4a14 0x1100, 0x4a141100 0x7;
+ interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
+ phys = sata_phy;
+ phy-names = sata-phy;
+ clocks = sata_ref_clk;
+ ti,hwmods = sata;
+ };
+
};
};
--
1.8.3.2
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[PATCH v2 10/13] ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
From: Keshava Munegowda keshava_mgo...@ti.com
Create hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index e297d62..227a69f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -1726,6 +1726,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
},
};
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+/* ocp2scp3 */
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
+/* l4_cfg - ocp2scp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
+ .master = omap54xx_l4_cfg_hwmod,
+ .slave = omap54xx_ocp2scp3_hwmod,
+ .clk= l4_root_clk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
+ .name = ocp2scp3,
+ .class = omap54xx_ocp2scp_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs =
OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+ .context_offs =
OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'sata' class
+ * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
+ .sysc_offs = 0x,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
+ .name = sata,
+ .sysc = omap54xx_sata_sysc,
+};
+
+/* sata */
+static struct omap_hwmod omap54xx_sata_hwmod = {
+ .name = sata,
+ .class = omap54xx_sata_hwmod_class,
+ .clkdm_name = l3init_clkdm,
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = func_48m_fclk,
+ .mpu_rt_idx = 1,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_cfg - sata */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
+ .master = omap54xx_l4_cfg_hwmod,
+ .slave = omap54xx_sata_hwmod,
+ .clk= l3_iclk_div,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
/*
* Interfaces
@@ -2399,6 +2470,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[]
__initdata = {
omap54xx_l4_cfg__usb_tll_hs,
omap54xx_l4_cfg__usb_otg_ss,
omap54xx_l4_wkup__wd_timer2,
+ omap54xx_l4_cfg__ocp2scp3,
+ omap54xx_l4_cfg__sata,
NULL,
};
--
1.8.3.2
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[PATCH v2 09/13] phy: omap: Depend on OMAP_OCP2SCP bus driver
The OMAP_USB2 and OMAP_PIPE3 PHY devices will not be detected if the OMAP_OCP2SCP bus driver is not present. Make them depend on it. Signed-off-by: Roger Quadros rog...@ti.com --- drivers/phy/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index fe8c009..2aead8b 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -47,6 +47,7 @@ config OMAP_USB2 depends on USB_PHY select GENERIC_PHY select OMAP_CONTROL_PHY + depends on OMAP_OCP2SCP help Enable this to support the transceiver that is part of SOC. This driver takes care of all the PHY functionality apart from comparator. @@ -58,6 +59,7 @@ config TI_PIPE3 depends on ARCH_OMAP2PLUS || COMPILE_TEST select GENERIC_PHY select OMAP_CONTROL_PHY + depends on OMAP_OCP2SCP help Enable this to support the PIPE3 PHY that is part of TI SOCs. This driver takes care of all the PHY functionality apart from comparator. -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 06/13] phy: ti-pipe3: Don't get 'wkupclk' and 'refclk' for SATA PHY
SATA PHY doesn't need 'wkupclk; and 'refclk' so don't
try to get them for SATA PHY.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index f141237..baa3f78d 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -294,16 +294,22 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
- if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get wkupclk\n);
- return PTR_ERR(phy-wkupclk);
- }
+ if (!of_device_is_compatible(node, ti,phy-pipe3-sata)) {
+
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
+ if (IS_ERR(phy-wkupclk)) {
+ dev_err(pdev-dev, unable to get wkupclk\n);
+ return PTR_ERR(phy-wkupclk);
+ }
- phy-refclk = devm_clk_get(phy-dev, refclk);
- if (IS_ERR(phy-refclk)) {
- dev_err(pdev-dev, unable to get refclk\n);
- return PTR_ERR(phy-refclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
+ }
+ } else {
+ phy-wkupclk = ERR_PTR(-ENODEV);
+ phy-refclk = ERR_PTR(-ENODEV);
}
phy-sys_clk = devm_clk_get(phy-dev, sysclk);
--
1.8.3.2
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[PATCH v2 04/13] phy: ti-pipe3: cleanup clock handling
As this driver is no longer USB specific, use generic clock names.
- Use 'wkupclk', 'sysclk' and 'refclk' clock-names. Update DT binding info.
- Fix PLL_SD_SHIFT from 9 to 10
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Update omap5 usb3_phy device tree node.
CC: Benoît Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 12 ++
arch/arm/boot/dts/omap5.dtsi | 7 ++-
drivers/phy/phy-ti-pipe3.c | 55
3 files changed, 46 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 28e674b..8d13349 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -59,6 +59,12 @@ Required properties:
filled in reg.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+ clock-names.
+ - clock-names: should include:
+ * wkupclk - wakup clock.
+ * sysclk - system clock.
+ * refclk - reference clock.
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
@@ -74,4 +80,10 @@ usb3phy@4a084400 {
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_usb;
#phy-cells = 0;
+ clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+ clock-names = wkupclk,
+ sysclk,
+ refclk;
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 859a800..e47601a 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -778,7 +778,12 @@
0x4a084800 0x64,
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_usb3phy;
+ clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+ clock-names = wkupclk,
+ sysclk,
+ refclk;
#phy-cells = 0;
};
};
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index fd029b1..211703c 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -45,7 +45,7 @@
#definePLL_SELFREQDCO_MASK 0x000E
#definePLL_SELFREQDCO_SHIFT0x1
#definePLL_SD_MASK 0x0003FC00
-#definePLL_SD_SHIFT0x9
+#definePLL_SD_SHIFT10
#defineSET_PLL_GO 0x1
#definePLL_TICOPWDN0x1
#definePLL_LOCK0x2
@@ -72,7 +72,7 @@ struct ti_pipe3 {
struct device *control_dev;
struct clk *wkupclk;
struct clk *sys_clk;
- struct clk *optclk;
+ struct clk *refclk;
};
struct pipe3_dpll_map {
@@ -270,23 +270,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+ dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
- clk_prepare(phy-wkupclk);
- phy-optclk = devm_clk_get(phy-dev, usb_otg_ss_refclk960m);
- if (IS_ERR(phy-optclk)) {
- dev_err(pdev-dev, unable to get usb_otg_ss_refclk960m\n);
- return PTR_ERR(phy-optclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
}
- clk_prepare(phy-optclk);
- phy-sys_clk = devm_clk_get(phy-dev, sys_clkin);
+ phy-sys_clk = devm_clk_get(phy-dev, sysclk);
if (IS_ERR(phy-sys_clk)) {
- pr_err(%s: unable to get sys_clkin\n, __func__);
+ dev_err(pdev-dev, unable to get sysclk\n);
return -EINVAL;
}
@@ -326,10 +324,6 @@ static int ti_pipe3_probe(struct platform_device *pdev)
static int ti_pipe3_remove(struct platform_device *pdev)
{
- struct ti_pipe3 *phy = platform_get_drvdata(pdev);
-
-
[PATCH v2 08/13] phy: ti-pipe3: Fix suspend/resume and module reload
Due to Errata i783, SATA breaks if its DPLL is idled. The recommeded workaround to issue a softreset to the SATA controller doesn't seem to work. Here we just prevent SATA DPLL from Idling and hence avoid the issue altogether. Signed-off-by: Roger Quadros rog...@ti.com --- drivers/phy/phy-ti-pipe3.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index 12cc900..5913676 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -238,6 +238,10 @@ static int ti_pipe3_exit(struct phy *x) u32 val; unsigned long timeout; + /* SATA DPLL can't be powered down due to Errata i783 */ + if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-sata)) + return 0; + /* Put DPLL in IDLE mode */ val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2); val |= PLL_IDLE; -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 07/13] phy: ti-pipe3: streamline PHY operations
Limit .power_on() and .power_off() to just control the
PHY power and not the DPLL. The DPLL will be enabled
in .init() and idled in .exit().
Don't reprogram the DPLL if it has been already locked
by the bootloader. This fixes a problem with SATA, where
it fails if SATA was used by the bootloader.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 114 +
1 file changed, 63 insertions(+), 51 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index baa3f78d..12cc900 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -47,7 +47,8 @@
#definePLL_SD_MASK 0x0003FC00
#definePLL_SD_SHIFT10
#defineSET_PLL_GO 0x1
-#definePLL_TICOPWDN0x1
+#define PLL_LDOPWDNBIT(15)
+#define PLL_TICOPWDN BIT(16)
#definePLL_LOCK0x2
#definePLL_IDLE0x1
@@ -56,7 +57,8 @@
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
* to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
*/
-# define PLL_IDLE_TIME 100;
+#define PLL_IDLE_TIME 100 /* in milliseconds */
+#define PLL_LOCK_TIME 100 /* in milliseconds */
struct pipe3_dpll_params {
u16 m;
@@ -132,24 +134,6 @@ static struct pipe3_dpll_params
*ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
static int ti_pipe3_power_off(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int val;
- int timeout = PLL_IDLE_TIME;
-
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
- val |= PLL_IDLE;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- do {
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
- if (val PLL_TICOPWDN)
- break;
- udelay(5);
- } while (--timeout);
-
- if (!timeout) {
- dev_err(phy-dev, power off failed\n);
- return -EBUSY;
- }
omap_control_phy_power(phy-control_dev, 0);
@@ -159,44 +143,34 @@ static int ti_pipe3_power_off(struct phy *x)
static int ti_pipe3_power_on(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int val;
- int timeout = PLL_IDLE_TIME;
-
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
- val = ~PLL_IDLE;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
- do {
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
- if (!(val PLL_TICOPWDN))
- break;
- udelay(5);
- } while (--timeout);
-
- if (!timeout) {
- dev_err(phy-dev, power on failed\n);
- return -EBUSY;
- }
+ omap_control_phy_power(phy-control_dev, 1);
return 0;
}
-static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
+static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
{
u32 val;
unsigned long timeout;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_GO, SET_PLL_GO);
-
- timeout = jiffies + msecs_to_jiffies(20);
+ timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
do {
+ cpu_relax();
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
if (val PLL_LOCK)
break;
- } while (!WARN_ON(time_after(jiffies, timeout)));
+ } while (!time_after(jiffies, timeout));
+
+ if (!(val PLL_LOCK)) {
+ dev_err(phy-dev, DPLL failed to lock\n);
+ return -EBUSY;
+ }
+
+ return 0;
}
-static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
+static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
{
u32 val;
struct pipe3_dpll_params *dpll_params;
@@ -230,27 +204,65 @@ static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
val |= dpll_params-sd PLL_SD_SHIFT;
ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION3, val);
- ti_pipe3_dpll_relock(phy);
+ ti_pipe3_writel(phy-pll_ctrl_base, PLL_GO, SET_PLL_GO);
- return 0;
+ return ti_pipe3_dpll_wait_lock(phy);
}
static int ti_pipe3_init(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int ret;
+ u32 val;
+ int ret = 0;
- ret = ti_pipe3_dpll_lock(phy);
- if (ret)
- return ret;
+ /* Bring it out of IDLE if it is IDLE */
+ val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
+ if (val PLL_IDLE) {
+ val = ~PLL_IDLE;
+ ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
+ ret = ti_pipe3_dpll_wait_lock(phy);
+ }
- omap_control_phy_power(phy-control_dev, 1);
+ /* Program the DPLL only if not locked */
+ val =
[PATCH v2 05/13] phy: ti-pipe3: Add SATA DPLL support
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Update the DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 3 +-
drivers/phy/phy-ti-pipe3.c | 76 +---
2 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 8d13349..2c2d66a 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -53,7 +53,8 @@ usb2phy@4a0ad080 {
TI PIPE3 PHY
Required properties:
- - compatible: Should be ti,phy-usb3. ti,omap-usb3 is deprecated.
+ - compatible: Should be ti,phy-usb3 or ti,phy-pipe3-sata.
+ ti,omap-usb3 is deprecated.
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in reg.
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 211703c..f141237 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -66,6 +66,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct ti_pipe3 {
void __iomem*pll_ctrl_base;
struct device *dev;
@@ -73,20 +78,27 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct pipe3_dpll_map *dpll_map;
};
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{2000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{2600, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { },/* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {1200, {1000, 7, 4, 6, 0} },/* 12 MHz */
+ {1680, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {1920, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {2000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {2600, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {3840, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { },/* Terminator */
};
static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
@@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr,
unsigned offset,
__raw_writel(data, addr + offset);
}
-static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = phy-dpll_map;
- for (i = 0; i ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return dpll_map[i].params;
+ rate = clk_get_rate(phy-sys_clk);
+
+ for (; dpll_map-rate; dpll_map++) {
+ if (rate == dpll_map-rate)
+ return dpll_map-params;
}
+ dev_err(phy-dev, No DPLL configuration for %lu Hz SYS CLK\n, rate);
+
return NULL;
}
@@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
{
u32 val;
- unsigned long rate;
struct pipe3_dpll_params *dpll_params;
- rate = clk_get_rate(phy-sys_clk);
- dpll_params = ti_pipe3_get_dpll_params(rate);
- if (!dpll_params) {
- dev_err(phy-dev,
- No DPLL configuration for %lu Hz SYS CLK\n, rate);
+ dpll_params = ti_pipe3_get_dpll_params(phy);
+ if (!dpll_params)
return -EINVAL;
- }
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION1);
val = ~PLL_REGN_MASK;
@@ -244,6 +256,10 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id ti_pipe3_id_table[];
+#endif
+
static int ti_pipe3_probe(struct platform_device *pdev)
{
struct ti_pipe3 *phy;
@@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
+
[PATCH v2 03/13] phy: omap-control: update dra7 and am437 usb2 bindings
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
drivers/phy/phy-omap-control.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 5c5b1b0..28e674b 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,9 +9,9 @@ Required properties:
e.g. USB2_PHY on OMAP5.
ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-dra7-usb2 - if it has power down register like USB2 PHY on
DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-am437-usb2 - if it has power down register like USB2 PHY on
AM437 platform.
- reg : Address and length of the register set for the device. It contains
the address of otghs_control for control-phy-otghs or power register
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-dra7-usb2,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-am437-usb2,
.data = am437usb2_data,
},
{},
--
1.8.3.2
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[PATCH v2 00/13][RESEND] ARM: OMAP: SATA support for OMAP5 DRA7
Hi,
[Resending cause I messed up Kishon's email ID in the original v2.]
This series adds SATA support for OMAP5 uevm and DRA7-evm boards.
- Cleans up the ti-pipe3 PHY driver
- Adds SATA DPLL support to ti-pipe3 PHY driver
- Adds SATA nodes to hwmod and SoC DT data
Patches are based on 3.14-rc4 with balbi/next, linux-phy/next and
omap-for-v3.15/dt merged on top..
To test SATA you will also need [1].
[1] - http://article.gmane.org/gmane.comp.hardware.netbook.arm.sunxi/7285
Changelog:
v2
- use 'depends on' instead of 'select' OCP2SCP bus driver.
- Changed DT bindings for dra7-usb2 and am437-usb2 phy.
cheers,
-roger
---
Balaji T K (2):
ARM: dts: omap5: add sata node
ARM: dts: dra7: add OCP2SCP3 and SATA nodes
Keshava Munegowda (1):
ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
Kishon Vijay Abraham I (1):
phy: rename struct omap_control_usb to struct omap_control_phy
Nikhil Devshatwar (1):
ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods
Roger Quadros (8):
phy: omap-control: Update DT binding information
phy: omap-control: update dra7 and am437 usb2 bindings
phy: ti-pipe3: cleanup clock handling
phy: ti-pipe3: Add SATA DPLL support
phy: ti-pipe3: Don't get 'wkupclk' and 'refclk' for SATA PHY
phy: ti-pipe3: streamline PHY operations
phy: ti-pipe3: Fix suspend/resume and module reload
phy: omap: Depend on OMAP_OCP2SCP bus driver
Documentation/devicetree/bindings/phy/ti-phy.txt | 40 ++-
Documentation/devicetree/bindings/usb/omap-usb.txt | 24 --
arch/arm/boot/dts/dra7.dtsi| 39 +++
arch/arm/boot/dts/omap5.dtsi | 47 +++-
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++-
drivers/phy/Kconfig| 16 +-
drivers/phy/Makefile | 1 +
drivers/{usb = }/phy/phy-omap-control.c | 169 ++---
drivers/phy/phy-omap-usb2.c| 8 +-
drivers/phy/phy-ti-pipe3.c | 269 +
drivers/usb/musb/omap2430.c| 2 +-
drivers/usb/phy/Kconfig| 10 -
drivers/usb/phy/Makefile | 1 -
.../omap_control_usb.h = phy/omap_control_phy.h} | 36 +--
15 files changed, 509 insertions(+), 257 deletions(-)
rename drivers/{usb = }/phy/phy-omap-control.c (53%)
rename include/linux/{usb/omap_control_usb.h = phy/omap_control_phy.h} (68%)
--
1.8.3.2
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[PATCH v2 02/13] phy: omap-control: Update DT binding information
Move omap-control binding information to the right location.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 25 ++
Documentation/devicetree/bindings/usb/omap-usb.txt | 24 -
2 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index f671163..5c5b1b0 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -1,5 +1,30 @@
TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
+OMAP CONTROL PHY
+
+Required properties:
+ - compatible: Should be one of
+ ti,control-phy-otghs - if it has otghs_control mailbox register as on OMAP4.
+ ti,control-phy-usb2 - if it has Power down bit in control_dev_conf register
+e.g. USB2_PHY on OMAP5.
+ ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
+e.g. USB3 PHY and SATA PHY on OMAP5.
+ ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+DRA7 platform.
+ ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+AM437 platform.
+ - reg : Address and length of the register set for the device. It contains
+ the address of otghs_control for control-phy-otghs or power register
+ for other types.
+ - reg-names: should be otghs_control control-phy-otghs and power for
+ other types.
+
+omap_control_usb: omap-control-usb@4a002300 {
+compatible = ti,control-phy-otghs;
+reg = 0x4a00233c 0x4;
+reg-names = otghs_control;
+};
+
OMAP USB2 PHY
Required properties:
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index c495135..38b2fae 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -76,27 +76,3 @@ omap_dwc3 {
ranges;
};
-OMAP CONTROL USB
-
-Required properties:
- - compatible: Should be one of
- ti,control-phy-otghs - if it has otghs_control mailbox register as on OMAP4.
- ti,control-phy-usb2 - if it has Power down bit in control_dev_conf register
- e.g. USB2_PHY on OMAP5.
- ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
- e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
- DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
- AM437 platform.
- - reg : Address and length of the register set for the device. It contains
- the address of otghs_control for control-phy-otghs or power register
- for other types.
- - reg-names: should be otghs_control control-phy-otghs and power for
- other types.
-
-omap_control_usb: omap-control-usb@4a002300 {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
-};
--
1.8.3.2
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[PATCH v2 01/13] phy: rename struct omap_control_usb to struct omap_control_phy
From: Kishon Vijay Abraham I kis...@ti.com
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/Kconfig| 14 +-
drivers/phy/Makefile | 1 +
drivers/{usb = }/phy/phy-omap-control.c | 165 +++--
drivers/phy/phy-omap-usb2.c| 8 +-
drivers/phy/phy-ti-pipe3.c | 8 +-
drivers/usb/musb/omap2430.c| 2 +-
drivers/usb/phy/Kconfig| 10 --
drivers/usb/phy/Makefile | 1 -
.../omap_control_usb.h = phy/omap_control_phy.h} | 36 ++---
9 files changed, 123 insertions(+), 122 deletions(-)
rename drivers/{usb = }/phy/phy-omap-control.c (55%)
rename include/linux/{usb/omap_control_usb.h = phy/omap_control_phy.h} (68%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1b607d7..fe8c009 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -31,12 +31,22 @@ config PHY_MVEBU_SATA
depends on OF
select GENERIC_PHY
+config OMAP_CONTROL_PHY
+ tristate OMAP CONTROL PHY Driver
+ help
+ Enable this to add support for the PHY part present in the control
+ module. This driver has API to power on the USB2 PHY and to write to
+ the mailbox. The mailbox is present only in omap4 and the register to
+ power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
+ additional register to power on USB3 PHY/SATA PHY/PCIE PHY
+ (PIPE3 PHY).
+
config OMAP_USB2
tristate OMAP USB2 PHY Driver
depends on ARCH_OMAP2PLUS
depends on USB_PHY
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the transceiver that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator.
@@ -47,7 +57,7 @@ config TI_PIPE3
tristate TI PIPE3 PHY Driver
depends on ARCH_OMAP2PLUS || COMPILE_TEST
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the PIPE3 PHY that is part of TI SOCs. This
driver takes care of all the PHY functionality apart from comparator.
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index ecf0d3f..8da05a8 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
+obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
similarity index 55%
rename from drivers/usb/phy/phy-omap-control.c
rename to drivers/phy/phy-omap-control.c
index e725318..17fc200 100644
--- a/drivers/usb/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -1,5 +1,5 @@
/*
- * omap-control-usb.c - The USB part of control module.
+ * omap-control-phy.c - The PHY part of control module.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -24,36 +24,36 @@
#include linux/err.h
#include linux/io.h
#include linux/clk.h
-#include linux/usb/omap_control_usb.h
+#include linux/phy/omap_control_phy.h
/**
- * omap_control_usb_phy_power - power on/off the phy using control module reg
+ * omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
*/
-void omap_control_usb_phy_power(struct device *dev, int on)
+void omap_control_phy_power(struct device *dev, int on)
{
u32 val;
unsigned long rate;
- struct omap_control_usb *control_usb;
+ struct omap_control_phy *control_phy;
if (IS_ERR(dev) || !dev) {
pr_err(%s: invalid device\n, __func__);
return;
}
- control_usb = dev_get_drvdata(dev);
- if (!control_usb) {
- dev_err(dev, %s: invalid control usb device\n, __func__);
+ control_phy = dev_get_drvdata(dev);
+ if (!control_phy) {
+ dev_err(dev, %s: invalid control phy device\n, __func__);
return;
}
- if
[PATCH v2 13/13] ARM: dts: dra7: add OCP2SCP3 and SATA nodes
From: Balaji T K balaj...@ti.com
Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9e3caf3..597979b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -772,6 +772,45 @@
dma-names = tx0, rx0;
status = disabled;
};
+
+ omap_control_sata: control-phy@4a002374 {
+ compatible = ti,control-phy-pipe3;
+ reg = 0x4a002374 0x4;
+ reg-names = power;
+ clocks = sys_clkin1;
+ clock-names = sysclk;
+ };
+
+ /* OCP2SCP3 */
+ ocp2scp@4a09 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ reg = 0x4a09 0x20;
+ ti,hwmods = ocp2scp3;
+ sata_phy: phy@4A096000 {
+ compatible = ti,phy-pipe3-sata;
+ reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+ reg-names = phy_rx, phy_tx, pll_ctrl;
+ ctrl-module = omap_control_sata;
+ clocks = sys_clkin1;
+ clock-names = sysclk;
+ #phy-cells = 0;
+ };
+ };
+
+ sata: sata@4a141100 {
+ compatible = snps,dwc-ahci;
+ reg = 0x4a14 0x1100, 0x4a141100 0x7;
+ interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
+ phys = sata_phy;
+ phy-names = sata-phy;
+ clocks = sata_ref_clk;
+ ti,hwmods = sata;
+ };
};
};
--
1.8.3.2
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[PATCH] ARM: OMAP2+: INTC: Acknowledge stuck active interrupts
When an interrupt has become active on the INTC it will stay active
until it is acked, even if masked or de-asserted. The
INTC_PENDING_IRQn registers are however updated and since these are
used by omap_intc_handle_irq to determine which interrupt to handle,
it will never see the active interrupt. This will result in a storm of
useless interrupts that is only stopped when another higher priority
interrupt is asserted.
Fix by sending the INTC an acknowledge if we find no interrupts to
handle.
Signed-off-by: Stefan Sørensen stefan.soren...@spectralink.com
---
arch/arm/mach-omap2/irq.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index e022a86..6037a9a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -222,6 +222,7 @@ void __init ti81xx_init_irq(void)
static inline void omap_intc_handle_irq(void __iomem *base_addr, struct
pt_regs *regs)
{
u32 irqnr;
+ int handled_irq = 0;
do {
irqnr = readl_relaxed(base_addr + 0x98);
@@ -249,8 +250,15 @@ out:
if (irqnr) {
irqnr = irq_find_mapping(domain, irqnr);
handle_IRQ(irqnr, regs);
+ handled_irq = 1;
}
} while (irqnr);
+
+ /* If an irq is masked or deasserted while active, we will
+* keep ending up here with no irq handled. So remove it from
+* the INTC with an ack.*/
+ if (!handled_irq)
+ omap_ack_irq(NULL);
}
asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs
*regs)
--
1.8.5.3
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Re: [RESEND PATCH 1/1] arm: dts: am33xx: correcting dt node unit address for usb
On Thu, Mar 06, 2014 at 06:01:34PM +0530, Mugunthan V N wrote:
DT node's unit address should be its own register offset address to make it a
unique across the system. This patch corrects the incorrect USB entries with
correct register offset for unit address.
Cc: Sebastian Andrzej Siewior bige...@linutronix.de
Cc: Felipe Balbi ba...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
---
This patch was posted long back (Aug. 30, 2013), below is the archive of the
orginal patch.
https://patchwork.kernel.org/patch/2852163/
---
arch/arm/boot/dts/am33xx.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 7073429..9770e35 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -453,7 +453,7 @@
ti,hwmods = usb_otg_hs;
status = disabled;
- usb_ctrl_mod: control@44e1 {
+ usb_ctrl_mod: control@44e10620 {
compatible = ti,am335x-usb-ctrl-module;
reg = 0x44e10620 0x10
0x44e10648 0x4;
@@ -556,7 +556,7 @@
tx14, tx15;
};
- cppi41dma: dma-controller@07402000 {
+ cppi41dma: dma-controller@47402000 {
compatible = ti,am3359-cppi41;
reg = 0x4740 0x1000
0x47402000 0x1000
--
1.9.0
--
balbi
signature.asc
Description: Digital signature
[PATCH v3 06/13] phy: ti-pipe3: Don't get 'wkupclk' and 'refclk' for SATA PHY
SATA PHY doesn't need 'wkupclk; and 'refclk' so don't
try to get them for SATA PHY.
Signed-off-by: Roger Quadros rog...@ti.com
---
v3 - Fixed checkpatch warning
drivers/phy/phy-ti-pipe3.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index f141237..f925f60 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -294,16 +294,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
- if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get wkupclk\n);
- return PTR_ERR(phy-wkupclk);
- }
+ if (!of_device_is_compatible(node, ti,phy-pipe3-sata)) {
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
+ if (IS_ERR(phy-wkupclk)) {
+ dev_err(pdev-dev, unable to get wkupclk\n);
+ return PTR_ERR(phy-wkupclk);
+ }
- phy-refclk = devm_clk_get(phy-dev, refclk);
- if (IS_ERR(phy-refclk)) {
- dev_err(pdev-dev, unable to get refclk\n);
- return PTR_ERR(phy-refclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
+ }
+ } else {
+ phy-wkupclk = ERR_PTR(-ENODEV);
+ phy-refclk = ERR_PTR(-ENODEV);
}
phy-sys_clk = devm_clk_get(phy-dev, sysclk);
--
1.8.3.2
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Re: [PATCH v2 01/13] phy: rename struct omap_control_usb to struct omap_control_phy
Felipe,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
From: Kishon Vijay Abraham I kis...@ti.com
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/Kconfig| 14 +-
drivers/phy/Makefile | 1 +
drivers/{usb = }/phy/phy-omap-control.c | 165 +++--
drivers/phy/phy-omap-usb2.c| 8 +-
drivers/phy/phy-ti-pipe3.c | 8 +-
drivers/usb/musb/omap2430.c| 2 +-
drivers/usb/phy/Kconfig| 10 --
drivers/usb/phy/Makefile | 1 -
Hope you are fine with the changes in drivers/usb/? Can you give your
Acked-by?
Regards
Kishon
.../omap_control_usb.h = phy/omap_control_phy.h} | 36 ++---
9 files changed, 123 insertions(+), 122 deletions(-)
rename drivers/{usb = }/phy/phy-omap-control.c (55%)
rename include/linux/{usb/omap_control_usb.h = phy/omap_control_phy.h} (68%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1b607d7..fe8c009 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -31,12 +31,22 @@ config PHY_MVEBU_SATA
depends on OF
select GENERIC_PHY
+config OMAP_CONTROL_PHY
+ tristate OMAP CONTROL PHY Driver
+ help
+ Enable this to add support for the PHY part present in the control
+ module. This driver has API to power on the USB2 PHY and to write to
+ the mailbox. The mailbox is present only in omap4 and the register to
+ power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
+ additional register to power on USB3 PHY/SATA PHY/PCIE PHY
+ (PIPE3 PHY).
+
config OMAP_USB2
tristate OMAP USB2 PHY Driver
depends on ARCH_OMAP2PLUS
depends on USB_PHY
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the transceiver that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator.
@@ -47,7 +57,7 @@ config TI_PIPE3
tristate TI PIPE3 PHY Driver
depends on ARCH_OMAP2PLUS || COMPILE_TEST
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the PIPE3 PHY that is part of TI SOCs. This
driver takes care of all the PHY functionality apart from comparator.
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index ecf0d3f..8da05a8 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
+obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TI_PIPE3)+= phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
similarity index 55%
rename from drivers/usb/phy/phy-omap-control.c
rename to drivers/phy/phy-omap-control.c
index e725318..17fc200 100644
--- a/drivers/usb/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -1,5 +1,5 @@
/*
- * omap-control-usb.c - The USB part of control module.
+ * omap-control-phy.c - The PHY part of control module.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -24,36 +24,36 @@
#include linux/err.h
#include linux/io.h
#include linux/clk.h
-#include linux/usb/omap_control_usb.h
+#include linux/phy/omap_control_phy.h
/**
- * omap_control_usb_phy_power - power on/off the phy using control module reg
+ * omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
*/
-void omap_control_usb_phy_power(struct device *dev, int on)
+void omap_control_phy_power(struct device *dev, int on)
{
u32 val;
unsigned long rate;
- struct omap_control_usb *control_usb;
+ struct omap_control_phy *control_phy;
if (IS_ERR(dev) || !dev) {
pr_err(%s: invalid device\n, __func__);
return;
}
- control_usb = dev_get_drvdata(dev);
- if (!control_usb) {
- dev_err(dev, %s: invalid control usb device\n,
Re: [PATCH v2 02/13] phy: omap-control: Update DT binding information
Felipe,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
Move omap-control binding information to the right location.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 25 ++
This patch is dependent on
Documentation: dt bindings: move ..usb/usb-phy.txt to
..phy/ti-phy.txt
which got merged in your tree. So can you take this patch also?
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Regards
Kishon
Documentation/devicetree/bindings/usb/omap-usb.txt | 24 -
2 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index f671163..5c5b1b0 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -1,5 +1,30 @@
TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
+OMAP CONTROL PHY
+
+Required properties:
+ - compatible: Should be one of
+ ti,control-phy-otghs - if it has otghs_control mailbox register as on OMAP4.
+ ti,control-phy-usb2 - if it has Power down bit in control_dev_conf register
+e.g. USB2_PHY on OMAP5.
+ ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
+e.g. USB3 PHY and SATA PHY on OMAP5.
+ ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+DRA7 platform.
+ ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+AM437 platform.
+ - reg : Address and length of the register set for the device. It contains
+ the address of otghs_control for control-phy-otghs or power register
+ for other types.
+ - reg-names: should be otghs_control control-phy-otghs and power for
+ other types.
+
+omap_control_usb: omap-control-usb@4a002300 {
+compatible = ti,control-phy-otghs;
+reg = 0x4a00233c 0x4;
+reg-names = otghs_control;
+};
+
OMAP USB2 PHY
Required properties:
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index c495135..38b2fae 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -76,27 +76,3 @@ omap_dwc3 {
ranges;
};
-OMAP CONTROL USB
-
-Required properties:
- - compatible: Should be one of
- ti,control-phy-otghs - if it has otghs_control mailbox register as on OMAP4.
- ti,control-phy-usb2 - if it has Power down bit in control_dev_conf register
- e.g. USB2_PHY on OMAP5.
- ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
- e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
- DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
- AM437 platform.
- - reg : Address and length of the register set for the device. It contains
- the address of otghs_control for control-phy-otghs or power register
- for other types.
- - reg-names: should be otghs_control control-phy-otghs and power for
- other types.
-
-omap_control_usb: omap-control-usb@4a002300 {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
-};
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Re: [PATCH v2 03/13] phy: omap-control: update dra7 and am437 usb2 bindings
Felipe,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
Here too..
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Regards
Kishon
drivers/phy/phy-omap-control.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 5c5b1b0..28e674b 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,9 +9,9 @@ Required properties:
e.g. USB2_PHY on OMAP5.
ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-dra7-usb2 - if it has power down register like USB2 PHY on
DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-am437-usb2 - if it has power down register like USB2 PHY on
AM437 platform.
- reg : Address and length of the register set for the device. It contains
the address of otghs_control for control-phy-otghs or power register
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-dra7-usb2,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-am437-usb2,
.data = am437usb2_data,
},
{},
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Re: [PATCH v2 04/13] phy: ti-pipe3: cleanup clock handling
Roger,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
As this driver is no longer USB specific, use generic clock names.
- Use 'wkupclk', 'sysclk' and 'refclk' clock-names. Update DT binding info.
- Fix PLL_SD_SHIFT from 9 to 10
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Update omap5 usb3_phy device tree node.
CC: Benoît Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 12 ++
arch/arm/boot/dts/omap5.dtsi | 7 ++-
drivers/phy/phy-ti-pipe3.c | 55
Here you have to split the patch. omap5.dtsi should be a separate patch
to Tony. I could take only phy-ti-pipe3.c again since ti-phy.txt is only
in Felipe's branch.
Regards
Kishon
3 files changed, 46 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 28e674b..8d13349 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -59,6 +59,12 @@ Required properties:
filled in reg.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+ clock-names.
+ - clock-names: should include:
+ * wkupclk - wakup clock.
+ * sysclk - system clock.
+ * refclk - reference clock.
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
@@ -74,4 +80,10 @@ usb3phy@4a084400 {
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_usb;
#phy-cells = 0;
+ clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+ clock-names = wkupclk,
+ sysclk,
+ refclk;
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 859a800..e47601a 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -778,7 +778,12 @@
0x4a084800 0x64,
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_usb3phy;
+ clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+ clock-names = wkupclk,
+ sysclk,
+ refclk;
#phy-cells = 0;
};
};
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index fd029b1..211703c 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -45,7 +45,7 @@
#define PLL_SELFREQDCO_MASK 0x000E
#define PLL_SELFREQDCO_SHIFT0x1
#define PLL_SD_MASK 0x0003FC00
-#definePLL_SD_SHIFT0x9
+#definePLL_SD_SHIFT10
#define SET_PLL_GO 0x1
#define PLL_TICOPWDN0x1
#define PLL_LOCK0x2
@@ -72,7 +72,7 @@ struct ti_pipe3 {
struct device *control_dev;
struct clk *wkupclk;
struct clk *sys_clk;
- struct clk *optclk;
+ struct clk *refclk;
};
struct pipe3_dpll_map {
@@ -270,23 +270,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev = pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+ dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
- clk_prepare(phy-wkupclk);
- phy-optclk = devm_clk_get(phy-dev, usb_otg_ss_refclk960m);
- if (IS_ERR(phy-optclk)) {
- dev_err(pdev-dev, unable to get usb_otg_ss_refclk960m\n);
- return PTR_ERR(phy-optclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
}
- clk_prepare(phy-optclk);
- phy-sys_clk = devm_clk_get(phy-dev, sys_clkin);
+ phy-sys_clk = devm_clk_get(phy-dev, sysclk);
if (IS_ERR(phy-sys_clk)) {
- pr_err(%s: unable to get sys_clkin\n, __func__);
+ dev_err(pdev-dev, unable to get sysclk\n);
Re: [PATCH v2 05/13] phy: ti-pipe3: Add SATA DPLL support
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Update the DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 3 +-
drivers/phy/phy-ti-pipe3.c | 76 +---
same here..
-Kishon
2 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 8d13349..2c2d66a 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -53,7 +53,8 @@ usb2phy@4a0ad080 {
TI PIPE3 PHY
Required properties:
- - compatible: Should be ti,phy-usb3. ti,omap-usb3 is deprecated.
+ - compatible: Should be ti,phy-usb3 or ti,phy-pipe3-sata.
+ ti,omap-usb3 is deprecated.
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in reg.
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 211703c..f141237 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -66,6 +66,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct ti_pipe3 {
void __iomem*pll_ctrl_base;
struct device *dev;
@@ -73,20 +78,27 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct pipe3_dpll_map *dpll_map;
};
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{2000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{2600, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { },/* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {1200, {1000, 7, 4, 6, 0} },/* 12 MHz */
+ {1680, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {1920, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {2000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {2600, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {3840, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { },/* Terminator */
};
static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
@@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr,
unsigned offset,
__raw_writel(data, addr + offset);
}
-static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = phy-dpll_map;
- for (i = 0; i ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return dpll_map[i].params;
+ rate = clk_get_rate(phy-sys_clk);
+
+ for (; dpll_map-rate; dpll_map++) {
+ if (rate == dpll_map-rate)
+ return dpll_map-params;
}
+ dev_err(phy-dev, No DPLL configuration for %lu Hz SYS CLK\n, rate);
+
return NULL;
}
@@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
{
u32 val;
- unsigned long rate;
struct pipe3_dpll_params *dpll_params;
- rate = clk_get_rate(phy-sys_clk);
- dpll_params = ti_pipe3_get_dpll_params(rate);
- if (!dpll_params) {
- dev_err(phy-dev,
- No DPLL configuration for %lu Hz SYS CLK\n, rate);
+ dpll_params = ti_pipe3_get_dpll_params(phy);
+ if (!dpll_params)
return -EINVAL;
- }
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION1);
val = ~PLL_REGN_MASK;
@@ -244,6 +256,10 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id ti_pipe3_id_table[];
+#endif
+
static int ti_pipe3_probe(struct platform_device *pdev)
{
struct ti_pipe3 *phy;
@@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
Re: [PATCH v2 01/13] phy: rename struct omap_control_usb to struct omap_control_phy
On Thu, Mar 06, 2014 at 09:07:56PM +0530, Kishon Vijay Abraham I wrote:
Felipe,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
From: Kishon Vijay Abraham I kis...@ti.com
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/Kconfig| 14 +-
drivers/phy/Makefile | 1 +
drivers/{usb = }/phy/phy-omap-control.c | 165
+++--
drivers/phy/phy-omap-usb2.c| 8 +-
drivers/phy/phy-ti-pipe3.c | 8 +-
drivers/usb/musb/omap2430.c| 2 +-
drivers/usb/phy/Kconfig| 10 --
drivers/usb/phy/Makefile | 1 -
Hope you are fine with the changes in drivers/usb/? Can you give your
Acked-by?
sure thing:
Acked-by: Felipe Balbi ba...@ti.com
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Re: [PATCH v2 02/13] phy: omap-control: Update DT binding information
On Thu, Mar 06, 2014 at 09:10:27PM +0530, Kishon Vijay Abraham I wrote: Felipe, On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote: Move omap-control binding information to the right location. Signed-off-by: Roger Quadros rog...@ti.com --- Documentation/devicetree/bindings/phy/ti-phy.txt | 25 ++ This patch is dependent on Documentation: dt bindings: move ..usb/usb-phy.txt to ..phy/ti-phy.txt which got merged in your tree. So can you take this patch also? Acked-by: Kishon Vijay Abraham I kis...@ti.com done -- balbi signature.asc Description: Digital signature
Re: [PATCH v2 03/13] phy: omap-control: update dra7 and am437 usb2 bindings
On Thu, Mar 06, 2014 at 04:38:39PM +0200, Roger Quadros wrote:
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
drivers/phy/phy-omap-control.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 5c5b1b0..28e674b 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,9 +9,9 @@ Required properties:
e.g. USB2_PHY on OMAP5.
ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-dra7-usb2 - if it has power down register like USB2 PHY on
DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-am437-usb2 - if it has power down register like USB2 PHY on
AM437 platform.
- reg : Address and length of the register set for the device. It contains
the address of otghs_control for control-phy-otghs or power register
I can take the Documentation part (which I've just done) but...
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-dra7-usb2,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-am437-usb2,
.data = am437usb2_data,
},
{},
I don't have this file in my tree ;-)
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Re: [RFC] CPSW: dual standalone emac mode / bonding
On Thu, 6 Mar 2014 13:52:41 +0530, Mugunthan V N mugunthan...@ti.com wrote: It seems that some other system in the network is using the same mac in your EVM or there is a loop detected in your network which leads that ALE is learning that there is system with your MAC and updating the ALE table that the mac is there and which leads your own packet will be forwarded to that port and not to host port. When ever you start a transmission the ALE learns the host port MAC is x and updates ALE table with that port number and so there in your network is working. Regarding the duplicate mac address please consider the following scenario: 2 switches are interconnected via a single crosslink. There is no loop in the system. The EVM is configured for dual emac mode and each external port is connected to one of the 2 switches. The 2 ethernet interfaces are enslaved by the bonding driver and setup in active-backup mode - from Documentation/networking/bonding.txt: Active-backup policy: Only one slave in the bond is active. A different slave becomes active if, and only if, the active slave fails. The bond's MAC address is externally visible on only one port (network adapter) to avoid confusing the switch. The default mac failover is used - all slave interfaces are set to the same mac address, so in case of a failure of the active slave the switches have to relearn ports due to issued gratuitous arp, but device caches are not affected. In case the EVM generates an arp request from the active interface the frame is also propagated through the system and received by the backup interfaces as it is a broadcast. Where an actual NIC would not be affected and the stack drops frames received on backup interfaces, I understood from You that the CPSW in dual emac mode is still a switch and relearns. From some of the TI wikis one might assume that that is not the case http://processors.wiki.ti.com/index.php/SK_ETH MAC mode disables the ALE in the AM335x and each of the external Ethernet ports communicates using different MAC addresses. However, the following seems to be more correct and resemble the implementation: http://processors.wiki.ti.com/index.php/AM335x_CPSW_(Ethernet)_Driver's_Guide http://processors.wiki.ti.com/index.php/Linux_Core_CPSW_User's_Guide Both the interfaces should not be connected to the same subnet unless only configuring bridging, and not doing IP routing, then you can configure the two interfaces on the same subnet. Whereas from the observed behaviour I would assume that both interfaces should not only be in different subnets, but also connected to different broadcast domains. It is not obvious to me why the CPSW learns per vlan, but got the persistant addresses configured differently - eg. snippet from /sys/class/net/eth0/ale_table type: vlan+addr(3), vlan: 3, addr: 00:12:3f:5d:96:17, uctype: touched(3), port: 2 type: vlan+addr(3), vlan: 2, addr: 00:12:3f:5d:96:17, uctype: touched(3), port: 1 type: vlan+addr(3), vlan: 3, addr: 34:db:fd:76:7f:be, uctype: untouched(1), port: 2 type: vlan+addr(3), vlan: 2, addr: 34:db:fd:76:7f:be, uctype: untouched(1), port: 1 type: addr(1), addr: 00:18:31:e0:06:69, uctype: persistant(0), port: 0 type: addr(1), addr: 00:18:31:e0:06:6a, uctype: persistant(0), port: 0 Due to this I currently see no change in the behaviour in case I configure the bond to use the interface assigned mac addresses without change or swap the macs just in case of a failover. It might be a solution to this setup if the CPSW would not be able to relearn it's own host macs, or if the learning would be completly separated per port/vlan. I admit that the affected EVM is still on the TI 3.2 Kernel and I have to upgrade the scenario, but as both pieces of code are from You: I saw that the setup of mac addresses has been changed in the current mainline version. cpsw_ale_add_ucast() seems to be merged with the previously split functionality of cpsw_ale_vlan_add_ucast() and in case of priv-data.dual_emac I see vid handling eg. in function cpsw_ndo_set_mac_address() and others. Could this result in a different setup of the ALE that allows relearning of the mac address set on both interfaces on the VLAN used for external backup port 2 without affecting the communication on external active port 1? Regards, Christian -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP2+: Use handle_fasteoi_irq for INTC interrupt handling
* Sørensen, Stefan stefan.soren...@spectralink.com [140306 06:36]: On Mon, 2014-03-03 at 09:49 -0800, Tony Lindgren wrote: 1. CPSW device asserts TX IRQ 2. CPSW device asserts RX IRQ 3. INTC interrupts CPU, TX IRQ marked as active 4. omap_intc_handle_irq ACKs TX IRQ on the INTC 5. INTC marks RX IRQ as active 6. omap_intc_handle_irq calls cpsw_interrupt 7. cpsw_interrupt disables RX+TX IRQ in CPSW device 8. cpsw_interrupt disables RX+TX IRQ in INTC (the IRQs are masked) 9.. omap_intc_handle_irq sees no unmasked IRQs are pending and returns 10. INTC interrupts CPU, RX IRQ marked as pending 11. omap_intc_handle_irq sees no unmasked IRQs are pending and returns 12. Go to step 10 The problem arises in step 8 where an active IRQ is masked. This will not make it inactive in the INTC but it will be cleared from the pending IRQ registers - this is the register that omap_intc_handle_irq uses to decide which IRQ is active. OK thanks for the info. Looking at your trace above it seems like the two separate TX and RX INTC interrupts are not really treated as separate interrupts in the cpsw driver. It seems the real fix is to fix up the cpsw interrupt handler so it's not racy. It seems that at least step 7 and 8 above should be handled separately for TX and RX based on the INTC interrupts. Looking in drivers/net/ethernet, it looks like a quite common pattern is to handle both RXx and TX interrupts with the same handler, which will disable both interrupts and then hand off to napi. The cpsw driver works the same way, so shouldn't this work on omap? Hmm yes at least disable_irq should work no matter when it's called. From the INTC point of view we should just have standard level IRQ handling for each interrupt, right? INTC does not need to know about driver specific coordination between two separate interrupts. The problem is that the INTC is not doing 100% level IRQ handling combined with the way we handle the INTC during interrupts. When a IRQ has become active on the INTC it will stay active until we acknowledge it, even if it is masked or de-asserted. Yes it's starting to sound that INTC has an issuerecovering from the spurious interrupts. My patch does not fix the problem when the active interrupt was de-asserted, so I am looking into other ways of dealing with it. OK. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP2+: INTC: Acknowledge stuck active interrupts
* Stefan Sørensen stefan.soren...@spectralink.com [140306 07:30]:
When an interrupt has become active on the INTC it will stay active
until it is acked, even if masked or de-asserted. The
INTC_PENDING_IRQn registers are however updated and since these are
used by omap_intc_handle_irq to determine which interrupt to handle,
it will never see the active interrupt. This will result in a storm of
useless interrupts that is only stopped when another higher priority
interrupt is asserted.
Fix by sending the INTC an acknowledge if we find no interrupts to
handle.
OK this makes more sense to me.
While playing with this, you may want to also do one more test and
forward port these two patches adding checks for spurious interrupts:
6ccc4c0d ARM: OMAP3: Warn about spurious interrupts
846c29f1 ARM: OMAP3: Clean up spurious interrupt check logic
Those got removed in commit:
667a11fa arm: omap2/3: Use generic irq chip
If you get warnings with those checks about spurious interrupts there's
also something else wrong or we're not understanding the problem fully.
So it might be good to check before we apply this patch.
Regards,
Tony
Signed-off-by: Stefan Sørensen stefan.soren...@spectralink.com
---
arch/arm/mach-omap2/irq.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index e022a86..6037a9a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -222,6 +222,7 @@ void __init ti81xx_init_irq(void)
static inline void omap_intc_handle_irq(void __iomem *base_addr, struct
pt_regs *regs)
{
u32 irqnr;
+ int handled_irq = 0;
do {
irqnr = readl_relaxed(base_addr + 0x98);
@@ -249,8 +250,15 @@ out:
if (irqnr) {
irqnr = irq_find_mapping(domain, irqnr);
handle_IRQ(irqnr, regs);
+ handled_irq = 1;
}
} while (irqnr);
+
+ /* If an irq is masked or deasserted while active, we will
+ * keep ending up here with no irq handled. So remove it from
+ * the INTC with an ack.*/
+ if (!handled_irq)
+ omap_ack_irq(NULL);
}
asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs
*regs)
--
1.8.5.3
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Re: [PATCH 2/5] ARM: dts: AM4372: Add USB nodes
* Roger Quadros rog...@ti.com [140306 00:52]:
On 03/03/2014 03:53 PM, George Cherian wrote:
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -698,6 +698,105 @@
edma 11;
dma-names = tx, rx;
};
+
+ am43xx_control_usb2phy1: control-phy@44e10620 {
+ compatible = ti,control-phy-am437usb2;
Since this is the first usage of this compatible ID, we still have room to
change it to be better. Tony's suggestion was to use
ti,control-phy-am437-usb2
Or from grepping point of view ti,control-phy-usb2-am437 might be better?
Regards,
Tony
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Re: [PATCH 2/2] ARM: dts: duovero-parlor: Add HDMI output
Hi Russell, On Wednesday 26 February 2014 13:28:56 Russell King - ARM Linux wrote: On Wed, Feb 26, 2014 at 02:44:02PM +0200, Tomi Valkeinen wrote: Also - DRM is not going to ever support hotplugging components - this was discussed at kernel summit last year and David Airlie was quite Ok. Very odd stance. Maybe there's a reason for it that I just don't see. DRM is like ALSA - it's a card level subsystem. All components have to be present before the card level is brought up for the subsystem to function correctly. I agree with Tomi here, I believe hot-plug (without hot-unplug) would be useful in case part of a video pipeline fails to probe. In a multi-output system (let's say HDMI and DSI panel for instance) I'd like the HDMI output to work if the DSI panel driver isn't loaded. DRM doesn't support this, and will not in the near future, but let's just keep in mind that real use cases exist. I'm not asking anyone to implement DRM hot- plug support now, but the idea itself shouldn't be nacked if someone can come up with a proper implementation. adamant about that. So, any framework which forces hotplugging of components on subsystems isn't going to fly. CDF doesn't force hotplugging. Although without hotplugging (hot-unplug not needed), or at least some minimal form of it, the system is a bit crippled. Leave one kernel module out, or have one driver probe fail, the whole display subsystem fails, even if some display pipelines would work fine. That is, unfortunately, one of the side effects of the policy - but that's not a policy that's going to change any time soon. As I said, that was made very clear at the last kernel summit - we had a /specific/ session on the issues around multi-device DRM chaired by David. There are some DRM drivers which have tried to do this, but they're all buggy in some regard, whether that be to the point of oopsing the kernel if things don't quite go to plan, or whether it's races between different parts. This is why we now have the component helpers in the driver model - to allow devices to be collected together into one logical subsystem group, and bound/unbound as a group. Yep, it's a good start. The component helpers could well be used with CDF. But if I'm not mistaken, it suffers from the problems above, when there are multiple independent pipelines (simultaneous or non-simultaneous) handled by the same IPs. It may suffer from the problems above that you've raised, but that's by explicit design of it - because that's what subsystems like DRM and ALSA require, and this is _precisely_ the problem it's solving. It's solving the subsystem requires a stable view of hardware components, but we have multiple devices and drivers which need probing problem. And, while I may be mistaken, it sounds that the component helpers leave mostly everything up to the display drivers. Everyone devising their own way to describe the hardware in DT, and the connections between the components. Of course, the core component system shouldn't define anything DT related, as it doesn't. But that part is still needed, which is where CDF comes in. Sigh. It's very easy for people to get the wrong end of the stick. What the component helpers do is provide a _subsystem_ _independent_ method of collecting a set of devices together and binding them to the drivers at an appropriate time, in a way that is _completely_ independent of whether you're using platform data, DT, ACPI, or whatever other hardware description language comes along. I think we all agree here, the component framework is required to implement clean support for component-based, DT-based systems, but doesn't depend on DT and doesn't imply any specific DT binding. What I believe bother people is that the example you have goes in a direction that might not be future-proof, and should thus not be used as an example to create display-related DT bindings. My understanding is that it's just an example to illustrate the kind of use case that the component framework can help with, not a proper DT bindings example that should be followed to design now DT bindings. It's up to the users of this to define how components are grouped together, whether that be at the subsystem level or at the driver level - whatever is appropriate. If a subsystem (eg, a display subsystem) wants to define this is how you define in DT the bindings between all components and provide its own hook for the add_components callback which does this, then it's at liberty to do that. If we can come up with a generic way to describe how all the components in a display subsystem should be connected together, then great - but that needs to happen very quickly. Philipp Zabel is working on replacing the imx-drm binding method right now for 3.15, and is probably completely unaware of anything that's been talked about here. I need to sort out Armada
Re: [PATCH 2/4] power_supply: Introduce generic psy charging driver
On Fri, Feb 28, 2014 at 12:27 PM, Jenny Tc jenny...@intel.com wrote:
On Thu, Feb 27, 2014 at 09:08:01PM +0100, Linus Walleij wrote:
On Thu, Feb 20, 2014 at 6:53 AM, Jenny TC jenny...@intel.com wrote:
+++ b/include/linux/power/power_supply_charger.h
+#define MAX_CUR_VOLT_SAMPLES 3
+#define DEF_CUR_VOLT_SAMPLE_JIFF (30*HZ)
Why are things defined in Jiffies like this insead of seconds, milliseconds
etc? This will vary with the current operating frequency of the system,
why should physical measurements do that?
Is it fine if I use msecs_to_jiffies(3)?
Keep the
#define DEF_CUR_VOLT_SAMPLE_PERIOD 3
Then use msecs_to_jiffies(DEF_CUR_VOLT_SAMPLE_PERIOD)
in the call site.
+enum psy_charger_cable_event {
+ PSY_CHARGER_CABLE_EVENT_DISCONNECT = 0,
+ PSY_CHARGER_CABLE_EVENT_CONNECT,
+ PSY_CHARGER_CABLE_EVENT_UPDATE,
+ PSY_CHARGER_CABLE_EVENT_RESUME,
+ PSY_CHARGER_CABLE_EVENT_SUSPEND,
+};
+
+enum psy_charger_cable_type {
+ PSY_CHARGER_CABLE_TYPE_NONE = 0,
+ PSY_CHARGER_CABLE_TYPE_USB_SDP = 1 0,
+ PSY_CHARGER_CABLE_TYPE_USB_DCP = 1 1,
+ PSY_CHARGER_CABLE_TYPE_USB_CDP = 1 2,
+ PSY_CHARGER_CABLE_TYPE_USB_ACA = 1 3,
+ PSY_CHARGER_CABLE_TYPE_AC = 1 4,
+ PSY_CHARGER_CABLE_TYPE_ACA_DOCK = 1 5,
+ PSY_CHARGER_CABLE_TYPE_ACA_A = 1 6,
+ PSY_CHARGER_CABLE_TYPE_ACA_B = 1 7,
+ PSY_CHARGER_CABLE_TYPE_ACA_C = 1 8,
+ PSY_CHARGER_CABLE_TYPE_SE1 = 1 9,
+ PSY_CHARGER_CABLE_TYPE_MHL = 1 10,
+ PSY_CHARGER_CABLE_TYPE_B_DEVICE = 1 11,
+};
Why is this even an enum? It is clearly bitfields. I would just:
#include linux/bitops.h
#define PSY_CHARGER_CABLE_TYPE_NONE 0x0
#define PSY_CHARGER_CABLE_TYPE_USB_SDP BIT(0)
#define PSY_CHARGER_CABLE_TYPE_USB_DCP BIT(1)
(etc)
This is to ensure type checks when the cable types are handled, #defines will
not help in type checks.
Type checks with static code check tools? But misrepresenting
a bitfield as an enum just to satisfy a static code checker is not
OK IMO.
Yours,
Linus Walleij
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Re: [PATCH 2/4] power_supply: Introduce generic psy charging driver
On Fri, Feb 28, 2014 at 6:01 PM, Pavel Machek pa...@ucw.cz wrote: On Thu 2014-02-27 21:08:01, Linus Walleij wrote: On Thu, Feb 20, 2014 at 6:53 AM, Jenny TC jenny...@intel.com wrote: +++ b/include/linux/power/power_supply_charger.h +#define MAX_CUR_VOLT_SAMPLES 3 +#define DEF_CUR_VOLT_SAMPLE_JIFF (30*HZ) Why are things defined in Jiffies like this insead of seconds, milliseconds etc? This will vary with the current operating frequency of the system, why should physical measurements do that? It is actually ok. The define is relative to jiffies, and that's what interface expects. So consider the option that the interface is wrong. Stating something like a sample period in system-specific jiffies instead of period time T is just weird. What control systems guy would understand this? Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] power_supply: Introduce PSE compliant algorithm
On Fri, Feb 28, 2014 at 11:07 AM, Jenny Tc jenny...@intel.com wrote: On Thu, Feb 27, 2014 at 09:18:57PM +0100, Linus Walleij wrote: On Tue, Feb 4, 2014 at 6:12 AM, Jenny TC jenny...@intel.com wrote: +static inline bool __is_battery_full + (long volt, long cur, long iterm, unsigned long cv) Overall I wonder if you've run checkpatch on these patches, but why are you naming this one function with a double __underscore? Just is_battery_full_check() or something would work fine I guess? Just to convey that is_battery_full is a local function and not generic. You can find similar usage in power_supply_core.c (__power_supply_changed_work) and in other drivers. Isn't it advised to have __ prefixes? The preference is different, usually __ is for compiler things, but while I dislike it (disturbs my perception) I can sure live with it. Why are you packing these structs? If no real reason, remove it. The compiler will pack what it thinks is appropriate anyway. The structure is part of the battery charging profile which can be read directly from an EEPROM or from secondary storage (emmc). So it should be packed to keep it align with the stored format. OK I buy that. Make sure this is noted somewhere (or maybe I missed it). Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] power_supply: Introduce PSE compliant algorithm
On Fri, Mar 07, 2014 at 11:34:14AM +0800, Linus Walleij wrote: On Fri, Feb 28, 2014 at 11:07 AM, Jenny Tc jenny...@intel.com wrote: On Thu, Feb 27, 2014 at 09:18:57PM +0100, Linus Walleij wrote: On Tue, Feb 4, 2014 at 6:12 AM, Jenny TC jenny...@intel.com wrote: +static inline bool __is_battery_full + (long volt, long cur, long iterm, unsigned long cv) Overall I wonder if you've run checkpatch on these patches, but why are you naming this one function with a double __underscore? Just is_battery_full_check() or something would work fine I guess? Just to convey that is_battery_full is a local function and not generic. You can find similar usage in power_supply_core.c (__power_supply_changed_work) and in other drivers. Isn't it advised to have __ prefixes? The preference is different, usually __ is for compiler things, but while I dislike it (disturbs my perception) I can sure live with it. Fixed in patch set v7 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] power_supply: Introduce generic psy charging driver
On Fri, Mar 07, 2014 at 11:03:02AM +0800, Linus Walleij wrote:
On Fri, Feb 28, 2014 at 12:27 PM, Jenny Tc jenny...@intel.com wrote:
On Thu, Feb 27, 2014 at 09:08:01PM +0100, Linus Walleij wrote:
On Thu, Feb 20, 2014 at 6:53 AM, Jenny TC jenny...@intel.com wrote:
+++ b/include/linux/power/power_supply_charger.h
+#define MAX_CUR_VOLT_SAMPLES 3
+#define DEF_CUR_VOLT_SAMPLE_JIFF (30*HZ)
Why are things defined in Jiffies like this insead of seconds, milliseconds
etc? This will vary with the current operating frequency of the system,
why should physical measurements do that?
Is it fine if I use msecs_to_jiffies(3)?
Keep the
#define DEF_CUR_VOLT_SAMPLE_PERIOD 3
Then use msecs_to_jiffies(DEF_CUR_VOLT_SAMPLE_PERIOD)
in the call site.
Ok..fine will fix it in next patch set
+enum psy_charger_cable_event {
+ PSY_CHARGER_CABLE_EVENT_DISCONNECT = 0,
+ PSY_CHARGER_CABLE_EVENT_CONNECT,
+ PSY_CHARGER_CABLE_EVENT_UPDATE,
+ PSY_CHARGER_CABLE_EVENT_RESUME,
+ PSY_CHARGER_CABLE_EVENT_SUSPEND,
+};
+
+enum psy_charger_cable_type {
+ PSY_CHARGER_CABLE_TYPE_NONE = 0,
+ PSY_CHARGER_CABLE_TYPE_USB_SDP = 1 0,
+ PSY_CHARGER_CABLE_TYPE_USB_DCP = 1 1,
+ PSY_CHARGER_CABLE_TYPE_USB_CDP = 1 2,
+ PSY_CHARGER_CABLE_TYPE_USB_ACA = 1 3,
+ PSY_CHARGER_CABLE_TYPE_AC = 1 4,
+ PSY_CHARGER_CABLE_TYPE_ACA_DOCK = 1 5,
+ PSY_CHARGER_CABLE_TYPE_ACA_A = 1 6,
+ PSY_CHARGER_CABLE_TYPE_ACA_B = 1 7,
+ PSY_CHARGER_CABLE_TYPE_ACA_C = 1 8,
+ PSY_CHARGER_CABLE_TYPE_SE1 = 1 9,
+ PSY_CHARGER_CABLE_TYPE_MHL = 1 10,
+ PSY_CHARGER_CABLE_TYPE_B_DEVICE = 1 11,
+};
Why is this even an enum? It is clearly bitfields. I would just:
#include linux/bitops.h
#define PSY_CHARGER_CABLE_TYPE_NONE 0x0
#define PSY_CHARGER_CABLE_TYPE_USB_SDP BIT(0)
#define PSY_CHARGER_CABLE_TYPE_USB_DCP BIT(1)
(etc)
This is to ensure type checks when the cable types are handled, #defines
will
not help in type checks.
Type checks with static code check tools? But misrepresenting
a bitfield as an enum just to satisfy a static code checker is not
OK IMO.
not just for tools, compile time type checks also.
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[PATCHv8 0/4] power_supply: Introduce power supply charging driver
v1: introduced feature as a framework within power supply class driver with separate files for battid framework and charging framework v2: fixed review comments, moved macros and inline functions to power_supply.h v3: moved the feature as a separate driver, combined battid framework and charging framework inside the power supply charging driver. Moved charger specific properties to power_supply_charger.h and plugged the driver with power supply subsystem using power_supply_notifier introduced in my previous patch. Also a sample charger chip driver (bq24261) patch added to give more idea on the psy charging driver usage v4: Fixed review comments, no major design changes. v5: Fixed makefile inconsistencies, removed unused pdata callbacks v6: Fixed nested loops, commenting style v7: added kerneldocs for structs and minor fixes v8: used msecs_to_jiffies instead of HZ directly, modified Kconfig help text for POWER_SUPPLY_CHARGING_ALGO_PSE The Power Supply charging driver connects multiple subsystems to do charging in a generic way. The subsystems involves power_supply, thermal and battery communication subsystems (1wire).With this the charging is handled in a generic way. The driver makes use of different new features - Battery Identification interfaces, pluggable charging algorithms, charger cable arbitrations etc. The patch also introduces generic interface for charger cable notifications. Charger cable events and capabilities can be notified using the generic power_supply_notifier chain. Overall this driver removes the charging logic out of the charger chip driver and the charger chip driver can just listen to the request from the power supply charging driver to set the charger properties. This can be implemented by exposing get_property and set property callbacks. Jenny TC (4): power_supply: Add inlmt,iterm, min/max temp props power_supply: Introduce generic psy charging driver power_supply: Introduce PSE compliant algorithm power_supply: bq24261 charger driver Documentation/power/power_supply_charger.txt | 353 +++ Documentation/power/power_supply_class.txt |6 + drivers/power/Kconfig| 31 + drivers/power/Makefile |3 + drivers/power/bq24261-charger.c | 1350 ++ drivers/power/charging_algo_pse.c| 204 drivers/power/power_supply_charger.c | 1186 ++ drivers/power/power_supply_charger.h | 218 + drivers/power/power_supply_core.c|3 + drivers/power/power_supply_sysfs.c |4 + include/linux/power/bq24261-charger.h| 25 + include/linux/power/power_supply_charger.h | 341 +++ include/linux/power_supply.h | 164 13 files changed, 3888 insertions(+) create mode 100644 Documentation/power/power_supply_charger.txt create mode 100644 drivers/power/bq24261-charger.c create mode 100644 drivers/power/charging_algo_pse.c create mode 100644 drivers/power/power_supply_charger.c create mode 100644 drivers/power/power_supply_charger.h create mode 100644 include/linux/power/bq24261-charger.h create mode 100644 include/linux/power/power_supply_charger.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv8 1/4] power_supply: Add inlmt,iterm, min/max temp props
Add new power supply properties for input current, charge termination
current, min and max temperature
POWER_SUPPLY_PROP_TEMP_MIN - minimum operatable temperature
POWER_SUPPLY_PROP_TEMP_MAX - maximum operatable temperature
POWER_SUPPLY_PROP_INLMT - input current limit programmed by charger. Indicates
the input current for a charging source.
POWER_SUPPLY_PROP_CHARGE_TERM_CUR - Charge termination current used to detect
the end of charge condition
Signed-off-by: Jenny TC jenny...@intel.com
---
Documentation/power/power_supply_class.txt |6 ++
drivers/power/power_supply_sysfs.c |4
include/linux/power_supply.h |4
3 files changed, 14 insertions(+)
diff --git a/Documentation/power/power_supply_class.txt
b/Documentation/power/power_supply_class.txt
index 89a8816..48cff88 100644
--- a/Documentation/power/power_supply_class.txt
+++ b/Documentation/power/power_supply_class.txt
@@ -118,6 +118,10 @@ relative, time-based measurements.
CONSTANT_CHARGE_CURRENT - constant charge current programmed by charger.
CONSTANT_CHARGE_CURRENT_MAX - maximum charge current supported by the
power supply object.
+INPUT_CURRENT_LIMIT - input current limit programmed by charger. Indicates
+the current drawn from a charging source.
+CHARGE_TERM_CURRENT - Charge termination current used to detect the end of
charge
+condition.
CONSTANT_CHARGE_VOLTAGE - constant charge voltage programmed by charger.
CONSTANT_CHARGE_VOLTAGE_MAX - maximum charge voltage supported by the
@@ -140,6 +144,8 @@ TEMP_ALERT_MAX - maximum battery temperature alert.
TEMP_AMBIENT - ambient temperature.
TEMP_AMBIENT_ALERT_MIN - minimum ambient temperature alert.
TEMP_AMBIENT_ALERT_MAX - maximum ambient temperature alert.
+TEMP_MIN - minimum operatable temperature
+TEMP_MAX - maximum operatable temperature
TIME_TO_EMPTY - seconds left for battery to be considered empty (i.e.
while battery powers a load)
diff --git a/drivers/power/power_supply_sysfs.c
b/drivers/power/power_supply_sysfs.c
index 44420d1..750a202 100644
--- a/drivers/power/power_supply_sysfs.c
+++ b/drivers/power/power_supply_sysfs.c
@@ -167,6 +167,7 @@ static struct device_attribute power_supply_attrs[] = {
POWER_SUPPLY_ATTR(constant_charge_voltage_max),
POWER_SUPPLY_ATTR(charge_control_limit),
POWER_SUPPLY_ATTR(charge_control_limit_max),
+ POWER_SUPPLY_ATTR(input_current_limit),
POWER_SUPPLY_ATTR(energy_full_design),
POWER_SUPPLY_ATTR(energy_empty_design),
POWER_SUPPLY_ATTR(energy_full),
@@ -178,6 +179,8 @@ static struct device_attribute power_supply_attrs[] = {
POWER_SUPPLY_ATTR(capacity_alert_max),
POWER_SUPPLY_ATTR(capacity_level),
POWER_SUPPLY_ATTR(temp),
+ POWER_SUPPLY_ATTR(temp_max),
+ POWER_SUPPLY_ATTR(temp_min),
POWER_SUPPLY_ATTR(temp_alert_min),
POWER_SUPPLY_ATTR(temp_alert_max),
POWER_SUPPLY_ATTR(temp_ambient),
@@ -189,6 +192,7 @@ static struct device_attribute power_supply_attrs[] = {
POWER_SUPPLY_ATTR(time_to_full_avg),
POWER_SUPPLY_ATTR(type),
POWER_SUPPLY_ATTR(scope),
+ POWER_SUPPLY_ATTR(charge_term_current),
/* Properties of type `const char *' */
POWER_SUPPLY_ATTR(model_name),
POWER_SUPPLY_ATTR(manufacturer),
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index c9dc4e0..0278600 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -120,6 +120,7 @@ enum power_supply_property {
POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX,
POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT,
POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX,
+ POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN,
POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN,
POWER_SUPPLY_PROP_ENERGY_FULL,
@@ -131,6 +132,8 @@ enum power_supply_property {
POWER_SUPPLY_PROP_CAPACITY_ALERT_MAX, /* in percents! */
POWER_SUPPLY_PROP_CAPACITY_LEVEL,
POWER_SUPPLY_PROP_TEMP,
+ POWER_SUPPLY_PROP_TEMP_MAX,
+ POWER_SUPPLY_PROP_TEMP_MIN,
POWER_SUPPLY_PROP_TEMP_ALERT_MIN,
POWER_SUPPLY_PROP_TEMP_ALERT_MAX,
POWER_SUPPLY_PROP_TEMP_AMBIENT,
@@ -142,6 +145,7 @@ enum power_supply_property {
POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
POWER_SUPPLY_PROP_TYPE, /* use power_supply.type instead */
POWER_SUPPLY_PROP_SCOPE,
+ POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT,
/* Properties of type `const char *' */
POWER_SUPPLY_PROP_MODEL_NAME,
POWER_SUPPLY_PROP_MANUFACTURER,
--
1.7.9.5
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[PATCHv8 3/4] power_supply: Introduce PSE compliant algorithm
As per Product Safety Engineering (PSE) specification for battery charging, the
battery characteristics and thereby the charging rates can vary on different
temperature zones. This patch introduces a PSE compliant charging algorithm with
maintenance charging support. The algorithm can be selected by the power supply
charging driver based on the type of the battery charging profile.
Signed-off-by: Jenny TC jenny...@intel.com
---
drivers/power/Kconfig | 15 ++
drivers/power/Makefile |1 +
drivers/power/charging_algo_pse.c | 204
include/linux/power/power_supply_charger.h | 63 +
4 files changed, 283 insertions(+)
create mode 100644 drivers/power/charging_algo_pse.c
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index f679f82..54a0321 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -22,6 +22,21 @@ config POWER_SUPPLY_CHARGER
drivers to keep the charging logic outside and the charger driver
just need to abstract the charger hardware.
+config POWER_SUPPLY_CHARGING_ALGO_PSE
+ bool PSE compliant charging algorithm
+ depends on POWER_SUPPLY_CHARGER
+ help
+ Say Y here to select Product Safety Engineering (PSE) compliant
+ charging algorithm. As per PSE standard the battery characteristics
+ and thereby the charging rates can vary on different temperature
+ zones. Select this if your charging algorithm need to change the
+ charging parameters based on the battery temperature and the battery
+ charging profile follows the struct psy_pse_chrg_prof definition.
+ This config will enable PSE compliant charging algorithm with
+ maintenance charging support. At runtime the algorithm will be
+ selected by the psy charger driver based on the type of the battery
+ charging profile.
+
config PDA_POWER
tristate Generic PDA/phone power driver
depends on !S390
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 405f0f4..77535fd 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_POWER_SUPPLY) += power_supply.o
obj-$(CONFIG_GENERIC_ADC_BATTERY) += generic-adc-battery.o
obj-$(CONFIG_POWER_SUPPLY_CHARGER) += power_supply_charger.o
+obj-$(CONFIG_POWER_SUPPLY_CHARGING_ALGO_PSE) += charging_algo_pse.o
obj-$(CONFIG_PDA_POWER)+= pda_power.o
obj-$(CONFIG_APM_POWER)+= apm_power.o
obj-$(CONFIG_MAX8925_POWER)+= max8925_power.o
diff --git a/drivers/power/charging_algo_pse.c
b/drivers/power/charging_algo_pse.c
new file mode 100644
index 000..ac95885
--- /dev/null
+++ b/drivers/power/charging_algo_pse.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2012 Intel Corporation
+ *
+ * ~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the GNU
+ * General Public License for more details.
+ *
+ * ~~
+ * Author: Jenny TC jenny...@intel.com
+ */
+
+#include linux/module.h
+#include linux/types.h
+#include linux/init.h
+#include linux/slab.h
+#include linux/device.h
+#include linux/err.h
+#include linux/power_supply.h
+#include linux/thermal.h
+#include power_supply.h
+#include power_supply_charger.h
+
+/* 98% of CV is considered as voltage to detect Full */
+#define FULL_CV_MIN 98
+
+/*
+ * Offset to exit from maintenance charging. In maintenance charging
+ * if the volatge is less than the (maintenance_lower_threshold -
+ * MAINT_EXIT_OFFSET) then system can switch to normal charging
+ */
+
+#define MAINT_EXIT_OFFSET 50 /* mV */
+
+static int get_tempzone(struct psy_pse_chrg_prof *pse_mod_bprof,
+ int temp)
+{
+ int i = 0;
+ int temp_range_cnt = min_t(u16, pse_mod_bprof-temp_mon_ranges,
+ BATT_TEMP_NR_RNG);
+
+ if ((temp pse_mod_bprof-temp_low_lim) ||
+ (temp pse_mod_bprof-temp_mon_range[0].temp_up_lim))
+ return -EINVAL;
+
+ for (i = 0; i temp_range_cnt; ++i)
+ if (temp pse_mod_bprof-temp_mon_range[i].temp_up_lim)
+ break;
+ return i-1;
+}
+
+static inline bool is_charge_terminated(long volt, long cur,
+ long iterm, unsigned long cv)
+{
+ pr_devel(%s:current=%ld pse_mod_bprof-chrg_term_mA =%ld
voltage_now=%ld full_cond=%ld,
+ __func__, cur, iterm, volt * 100, (FULL_CV_MIN
[PATCHv8 4/4] power_supply: bq24261 charger driver
This patch introduces BQ24261 charger driver. The driver makes use of power supply charging driver to setup charging. So the driver does hardware abstraction and handles h/w specific corner cases. The charging logic resides with power supply charging driver Signed-off-by: Jenny TC jenny...@intel.com --- drivers/power/Kconfig | 10 + drivers/power/Makefile|1 + drivers/power/bq24261-charger.c | 1350 + include/linux/power/bq24261-charger.h | 25 + 4 files changed, 1386 insertions(+) create mode 100644 drivers/power/bq24261-charger.c create mode 100644 include/linux/power/bq24261-charger.h diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 54a0321..4ff080c 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -411,6 +411,16 @@ config BATTERY_GOLDFISH Say Y to enable support for the battery and AC power in the Goldfish emulator. +config CHARGER_BQ24261 + tristate BQ24261 charger driver + select POWER_SUPPLY_CHARGER + depends on I2C + help + Say Y to include support for BQ24261 Charger driver. This driver + makes use of power supply charging driver. So the driver gives + the charger hardware abstraction only. Charging logic is abstracted + in the power supply charging driver. + source drivers/power/reset/Kconfig endif # POWER_SUPPLY diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 77535fd..9dde895 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -59,4 +59,5 @@ obj-$(CONFIG_CHARGER_BQ24735) += bq24735-charger.o obj-$(CONFIG_POWER_AVS)+= avs/ obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o obj-$(CONFIG_CHARGER_TPS65090) += tps65090-charger.o +obj-$(CONFIG_CHARGER_BQ24261) += bq24261-charger.o obj-$(CONFIG_POWER_RESET) += reset/ diff --git a/drivers/power/bq24261-charger.c b/drivers/power/bq24261-charger.c new file mode 100644 index 000..187c1fe --- /dev/null +++ b/drivers/power/bq24261-charger.c @@ -0,0 +1,1350 @@ +/* + * bq24261-charger.c - BQ24261 Charger I2C client driver + * + * Copyright (C) 2011 Intel Corporation + * + * ~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the GNU + * General Public License for more details. + * + * ~~ + * Author: Jenny TC jenny...@intel.com + */ + +#include linux/delay.h +#include linux/device.h +#include linux/err.h +#include linux/i2c.h +#include linux/init.h +#include linux/interrupt.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/pm_runtime.h +#include linux/power_supply.h +#include linux/power/power_supply_charger.h +#include linux/power/bq24261-charger.h +#include linux/sched.h +#include linux/seq_file.h +#include linux/slab.h +#include linux/usb/otg.h +#include linux/version.h + + +#define DEV_NAME bq24261_charger +#define MODEL_NAME_SIZE 8 + +#define EXCEPTION_MONITOR_DELAY (60 * HZ) +#define WDT_RESET_DELAY (15 * HZ) + +/* BQ24261 registers */ +#define BQ24261_STAT_CTRL0_ADDR0x00 +#define BQ24261_CTRL_ADDR 0x01 +#define BQ24261_BATT_VOL_CTRL_ADDR 0x02 +#define BQ24261_VENDOR_REV_ADDR0x03 +#define BQ24261_TERM_FCC_ADDR 0x04 +#define BQ24261_VINDPM_STAT_ADDR 0x05 +#define BQ24261_ST_NTC_MON_ADDR0x06 + +#define BQ24261_RESET_MASK (0x01 7) +#define BQ24261_RESET_ENABLE (0x01 7) + +#define BQ24261_FAULT_MASK 0x07 +#define BQ24261_STAT_MASK (0x03 4) +#define BQ24261_BOOST_MASK (0x01 6) +#define BQ24261_TMR_RST_MASK (0x01 7) +#define BQ24261_TMR_RST(0x01 7) + +#define BQ24261_ENABLE_BOOST (0x01 6) + +#define BQ24261_VOVP 0x01 +#define BQ24261_LOW_SUPPLY 0x02 +#define BQ24261_THERMAL_SHUTDOWN 0x03 +#define BQ24261_BATT_TEMP_FAULT0x04 +#define BQ24261_TIMER_FAULT0x05 +#define BQ24261_BATT_OVP 0x06 +#define BQ24261_NO_BATTERY 0x07 +#define BQ24261_STAT_READY 0x00 + +#define BQ24261_STAT_CHRG_PRGRSS (0x01 4) +#define BQ24261_STAT_CHRG_DONE (0x02 4) +#define BQ24261_STAT_FAULT (0x03 4) + +#define BQ24261_CE_MASK(0x01 1) +#define BQ24261_CE_DISABLE (0x01 1) + +#define BQ24261_HZ_MASK(0x01) +#define
Re: power_supply mailing list
On Sat, Feb 01, 2014 at 09:06:48AM -0700, Dmitry Eremin-Solenikov wrote: Hello, On Thu, Jan 30, 2014 at 10:46 PM, Jenny Tc jenny...@intel.com wrote: Do we have any mailing list for power_supply subsystem? If not what about having one - linux-power-sup...@vger.kernel.org? I'm not sure that if that ML will have enough traffic to be fully usefull or enough reviewers on it. However as currently most of the power_supply patches receive a long list of To and Cc people, let's try that ML. David, could you please create a mailing list for power_supply discussions? Dmitry/David, Any update on this. Appreciate your help on this. Thanks Jenny -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3] phy: omap-control: update dra7 and am437 usb2 bindings
From: Roger Quadros rog...@ti.com
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v2:
Kept only the drivers/phy part in this patch
drivers/phy/phy-omap-control.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-dra7-usb2,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-am437-usb2,
.data = am437usb2_data,
},
{},
--
1.7.9.5
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[PATCH v3] phy: ti-pipe3: cleanup clock handling
From: Roger Quadros rog...@ti.com
As this driver is no longer USB specific, use generic clock names.
- Fix PLL_SD_SHIFT from 9 to 10
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v2:
* Kept only the drivers/phy part in this patch
drivers/phy/phy-ti-pipe3.c | 55 ++--
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index fd029b1..211703c 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -45,7 +45,7 @@
#definePLL_SELFREQDCO_MASK 0x000E
#definePLL_SELFREQDCO_SHIFT0x1
#definePLL_SD_MASK 0x0003FC00
-#definePLL_SD_SHIFT0x9
+#definePLL_SD_SHIFT10
#defineSET_PLL_GO 0x1
#definePLL_TICOPWDN0x1
#definePLL_LOCK0x2
@@ -72,7 +72,7 @@ struct ti_pipe3 {
struct device *control_dev;
struct clk *wkupclk;
struct clk *sys_clk;
- struct clk *optclk;
+ struct clk *refclk;
};
struct pipe3_dpll_map {
@@ -270,23 +270,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+ dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
- clk_prepare(phy-wkupclk);
- phy-optclk = devm_clk_get(phy-dev, usb_otg_ss_refclk960m);
- if (IS_ERR(phy-optclk)) {
- dev_err(pdev-dev, unable to get usb_otg_ss_refclk960m\n);
- return PTR_ERR(phy-optclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
}
- clk_prepare(phy-optclk);
- phy-sys_clk = devm_clk_get(phy-dev, sys_clkin);
+ phy-sys_clk = devm_clk_get(phy-dev, sysclk);
if (IS_ERR(phy-sys_clk)) {
- pr_err(%s: unable to get sys_clkin\n, __func__);
+ dev_err(pdev-dev, unable to get sysclk\n);
return -EINVAL;
}
@@ -326,10 +324,6 @@ static int ti_pipe3_probe(struct platform_device *pdev)
static int ti_pipe3_remove(struct platform_device *pdev)
{
- struct ti_pipe3 *phy = platform_get_drvdata(pdev);
-
- clk_unprepare(phy-wkupclk);
- clk_unprepare(phy-optclk);
if (!pm_runtime_suspended(pdev-dev))
pm_runtime_put(pdev-dev);
pm_runtime_disable(pdev-dev);
@@ -343,8 +337,10 @@ static int ti_pipe3_runtime_suspend(struct device *dev)
{
struct ti_pipe3 *phy = dev_get_drvdata(dev);
- clk_disable(phy-wkupclk);
- clk_disable(phy-optclk);
+ if (!IS_ERR(phy-wkupclk))
+ clk_disable_unprepare(phy-wkupclk);
+ if (!IS_ERR(phy-refclk))
+ clk_disable_unprepare(phy-refclk);
return 0;
}
@@ -354,22 +350,27 @@ static int ti_pipe3_runtime_resume(struct device *dev)
u32 ret = 0;
struct ti_pipe3 *phy = dev_get_drvdata(dev);
- ret = clk_enable(phy-optclk);
- if (ret) {
- dev_err(phy-dev, Failed to enable optclk %d\n, ret);
- goto err1;
+ if (!IS_ERR(phy-refclk)) {
+ ret = clk_prepare_enable(phy-refclk);
+ if (ret) {
+ dev_err(phy-dev, Failed to enable refclk %d\n, ret);
+ goto err1;
+ }
}
- ret = clk_enable(phy-wkupclk);
- if (ret) {
- dev_err(phy-dev, Failed to enable wkupclk %d\n, ret);
- goto err2;
+ if (!IS_ERR(phy-wkupclk)) {
+ ret = clk_prepare_enable(phy-wkupclk);
+ if (ret) {
+ dev_err(phy-dev, Failed to enable wkupclk %d\n, ret);
+ goto err2;
+ }
}
return 0;
err2:
- clk_disable(phy-optclk);
+ if (!IS_ERR(phy-refclk))
+ clk_disable_unprepare(phy-refclk);
err1:
return ret;
--
1.7.9.5
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Re: [PATCH v3] phy: omap-control: update dra7 and am437 usb2 bindings
On 3/7/2014 11:18 AM, Kishon Vijay Abraham I wrote:
From: Roger Quadros rog...@ti.com
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v2:
Kept only the drivers/phy part in this patch
drivers/phy/phy-omap-control.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-dra7-usb2,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-am437-usb2,
Tony suggested to keep the compatible
ti,control-phy-usb2-dra7 and ti,control-phy-usb2-am437
http://www.spinics.net/lists/linux-omap/msg104040.html
Since we already have a ti,control-phy-usb2 I think it make sense to keep the
new comaptible for dra7 and am437 as above.
.data = am437usb2_data,
},
{},
--
-George
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[PATCH v3] phy: ti-pipe3: Add SATA DPLL support
From: Roger Quadros rog...@ti.com
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v2:
* kept only the drivers/phy part
drivers/phy/phy-ti-pipe3.c | 76
1 file changed, 55 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 211703c..f141237 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -66,6 +66,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct ti_pipe3 {
void __iomem*pll_ctrl_base;
struct device *dev;
@@ -73,20 +78,27 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct pipe3_dpll_map *dpll_map;
};
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{2000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{2600, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { },/* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {1200, {1000, 7, 4, 6, 0} },/* 12 MHz */
+ {1680, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {1920, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {2000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {2600, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {3840, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { },/* Terminator */
};
static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
@@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr,
unsigned offset,
__raw_writel(data, addr + offset);
}
-static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = phy-dpll_map;
- for (i = 0; i ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return dpll_map[i].params;
+ rate = clk_get_rate(phy-sys_clk);
+
+ for (; dpll_map-rate; dpll_map++) {
+ if (rate == dpll_map-rate)
+ return dpll_map-params;
}
+ dev_err(phy-dev, No DPLL configuration for %lu Hz SYS CLK\n, rate);
+
return NULL;
}
@@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
{
u32 val;
- unsigned long rate;
struct pipe3_dpll_params *dpll_params;
- rate = clk_get_rate(phy-sys_clk);
- dpll_params = ti_pipe3_get_dpll_params(rate);
- if (!dpll_params) {
- dev_err(phy-dev,
- No DPLL configuration for %lu Hz SYS CLK\n, rate);
+ dpll_params = ti_pipe3_get_dpll_params(phy);
+ if (!dpll_params)
return -EINVAL;
- }
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION1);
val = ~PLL_REGN_MASK;
@@ -244,6 +256,10 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id ti_pipe3_id_table[];
+#endif
+
static int ti_pipe3_probe(struct platform_device *pdev)
{
struct ti_pipe3 *phy;
@@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
+ const struct of_device_id *match;
- if (!node)
+ match = of_match_device(of_match_ptr(ti_pipe3_id_table), pdev-dev);
+ if (!match)
return -EINVAL;
phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
@@ -263,6 +281,12 @@ static int ti_pipe3_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ phy-dpll_map = (struct pipe3_dpll_map *)match-data;
+ if (!phy-dpll_map) {
+ dev_err(pdev-dev, no DPLL data\n);
+ return -EINVAL;
+ }
+
res = platform_get_resource_byname(pdev,
