64KiB is allocated for qspi dtb partition which is not
sufficient, so updating the partition table size to 512KiB
for device tree partition.
This also aligns the QSPI partition definitions between
kernel and U-Boot.
Fixes: dc2dd5b8 (ARM: dts: dra7: Add qspi device)
Signed-off-by: Mugunthan V N
Lokesh,
On 19/12/14 07:21, Lokesh Vutla wrote:
Hi Roger,
On Thursday 18 December 2014 09:22 PM, Roger Quadros wrote:
Fixing up Paul's email id.
cheers,
-roger
On 18/12/14 17:49, Roger Quadros wrote:
There are quite a few hwmods that don't have sysconfig register and so
'dss_fck' clock was recently removed, but a clock alias for it was left.
This causes a warning:
ti_dt_clocks_register: failed to lookup clock node dss_fck
Remove the unneeded clock alias.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/clk/ti/clk-44xx.c | 1 -
1 file changed, 1
The omapdss_dss driver has not used 'ick' clock for a long time, and
thus the clock alias for 'ick' is not needed and can be removed.
On OMAP4 the 'dss_fck' clock was recently removed, and as 'ick' was an
alias for 'dss_fck', it causes a warning:
ti_dt_clocks_register: failed to lookup clock
Hi!
And you want to set the QUIRK_INVALID_BADDR. At least you want to do that in
the final submission.
Ok, I found out that I can do it and result works, provided that I do
hciconfig hci0 up/down first.
I have trouble understanding... h4p_hci_open() seems to be called as
soon as I insmod
Hi Pavel,
And you want to set the QUIRK_INVALID_BADDR. At least you want to do that in
the final submission.
Ok, I found out that I can do it and result works, provided that I do
hciconfig hci0 up/down first.
that should not be the case. Actually hciconfig uses old ioctl. A full
On 3 December 2014 at 00:42, Doug Anderson diand...@chromium.org wrote:
Bing Zhao at Marvell found a problem with dw_mmc where interrupts
weren't firing sometimes. He tracked it down to a read-modify-write
problem with the INTMASK. These patches fix the problem.
Note: I've picked up a
Hi,
Here are similar patches for AM43xx and DRA7xxx than was done earlier for
OMAP4/5 in
543b2847d4bdb07eb1b50003095bc65cf2a1e2c0
(ARM: OMAP4: hwmod: set DSS submodule parent hwmods)
and
9ed69650897e8738c959fe8242ec41499f3f3f35
(ARM: OMAP5: hwmod: set DSS submodule parent hwmods)
I don't
Set DSS core hwmod as the parent for all the DSS submodules. This fixes
the boot time DSS reset, removing the following warnings:
omap_hwmod: dss_dispc: cannot be enabled for reset (3)
omap_hwmod: dss_rfbi: cannot be enabled for reset (3)
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
Set DSS core hwmod as the parent for all the DSS submodules. This fixes
the boot time DSS reset, removing the following warnings:
omap_hwmod: dss_dispc: cannot be enabled for reset (3)
omap_hwmod: dss_hdmi: cannot be enabled for reset (3)
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
Hi Everybody,
After several test with IGEPv2 board (OMAP3) and linux kernel 3.17 and
3.18, the OTG works but, (from my point of view) with an weird
behaviour.
The OTG like a Host only is activated after load a gadget driver, I
mean that, If I plug a USB memory dongle in the OTG port before load
On 11 December 2014 at 22:43, NeilBrown ne...@suse.de wrote:
Using the common code removes some code duplication, and
makes it easier to switch to using mmc_of_parse() which
will remove more duplication.
As hsmmc has a slightly different interrupt service routine
for card-detect, enhance
On 11 December 2014 at 22:43, NeilBrown ne...@suse.de wrote:
The only function of these 'prepare' and 'complete' is to
disable the 'card detect' irq during suspend.
The commit which added this,
commit a48ce884d5819d5df2cf1139ab3c43f8e9e419b3
mmc: omap_hsmmc: Introduce
Hi,
During system suspend L3INIT_960M_GFCLK and L3INIT_480M_GFCLK clocks remain
active on the DRA7 platform. This is because the pipe3 driver doesn't shut
them off as part of .suspend(). Patch 1 addresses this issue.
SATA on both OMAP5 and DRA7 breaks when SATA drive is plugged in after a
system
On system suspend, the runtime_suspend() driver hook doesn't get
called and so the clocks are not disabled in the driver.
This causes the L3INIT_960M_GFCLK and L3INIT_480M_GFCLK to remain
active on the DRA7 platform while in system suspend.
Add suspend/resume hooks to the driver.
In case of
Failed test case: Boot without SATA drive connected. Suspend/resume
the board and then connect SATA drive. It fails to enumerate.
Due to Errata i783 SATA Lockup After SATA DPLL Unlock/Relock
we can't allow SATA DPLL to be in the unlocked state.
The SATA refclk (sata_ref_clk) is the source of the
Fixed pr_debug to pr_err when hwmod returns an error when enabling
a module.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c
On Wed, 17 Dec 2014, Tero Kristo wrote:
The dual parent issue required by the DPLL code is caused by the introduction
of determine-rate / set-parent / set-rate-and-parent logic to OMAP DPPLs. I
took a short-cut here, making the assumption that every DPLL has both of these
clocks defined
Ulf,
On Fri, Dec 19, 2014 at 2:17 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 3 December 2014 at 00:42, Doug Anderson diand...@chromium.org wrote:
Bing Zhao at Marvell found a problem with dw_mmc where interrupts
weren't firing sometimes. He tracked it down to a read-modify-write
Hi Stephen,
Might you be willing to include this branch in your linux-next builds?
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git#for-next
It will include OMAP clock, bus architecture, and low-level power
management patches that are planned to be included in pull requests
* Paul Walmsley p...@pwsan.com [141219 11:30]:
Hi Stephen,
Might you be willing to include this branch in your linux-next builds?
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git#for-next
It will include OMAP clock, bus architecture, and low-level power
management
If the boot loader enables HYP mode on the boot CPU, the secondary CPU
also needs to call into the ROM to switch to HYP mode before booting.
The firmwares on the omap5 and dra7xx unfortunately do not take care
of this, so it has to be handled by the kernel.
This patch is based on [PATCH 2/2] ARM:
Using the common code removes some code duplication, and
makes it easier to switch to using mmc_of_parse() which
will remove more duplication.
This uses the new mmc_gpio_request_cd_isr to provide a non-standard
interrupt service routine for card-detect interrupts.
Signed-off-by: NeilBrown
One of the reasons omap_hsmmc doesn't use the slot-gpio library
is that it has some non-standard functionality in the card-detect
interrupt service routine.
To make it possible for omap_hsmmc (and maybe others) to be converted
to use slot-gpio, add 'mmc_gpio_request_cd_isr' which provide an
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