Add ti,dra742-uart to the compatible list so the driver
workaround for UART module disable errata is enabled.
This does not break backward compatibility as existing DTBs
should continue to work with newer kernels albeit without the
capability to idle the UART module when DMA is used.
Acked-by:
Hi Greg,
On Fri, Jul 10, 2015 at 10:28 AM, Kevin Hilman khil...@kernel.org wrote:
From: Tony Lindgren t...@atomide.com
We get a NULL pointer dereference on omap3 for thumb2 compiled kernels:
Internal error: Oops: 8005 [#1] SMP THUMB2
...
[c046497b] (_raw_spin_unlock_irqrestore) from
On Thu, Jul 30, 2015 at 03:27:54PM -0500, Kevin Hilman wrote:
Hi Greg,
On Fri, Jul 10, 2015 at 10:28 AM, Kevin Hilman khil...@kernel.org wrote:
From: Tony Lindgren t...@atomide.com
We get a NULL pointer dereference on omap3 for thumb2 compiled kernels:
Internal error: Oops: 8005
If DMA is active during a shutdown, a delayed restore of the
registers may be pending. The restore must be performed after
the DMA is stopped, otherwise the delayed restore remains
pending and will fire upon the first DMA TX complete of a
totally different serial session.
Signed-off-by: John
uart_write_wakeup() should be called without holding the port lock.
Otherwise a possible recursive spinlock issue can occur, such as
the following callchain:
8250_core.c:serial8250_tx_chars() - called with port locked
serial_core.c:uart_write_wakeup()
tty_io.c:tty_wakeup()
This patch series addresses some locking, race condition, and cleanup
issues identified with the 8250 serial driver on omap boards.
John Ogness (3):
serial: 8250: unlock port for uart_write_wakeup()
serial: 8250: move rx_running out of the bitfield
serial: 8250: omap: restore registers on
On 07/30/2015 07:15 PM, Peter Hurley wrote:
On 07/30/2015 06:54 PM, John Ogness wrote:
uart_write_wakeup() should be called without holding the port lock.
Otherwise a possible recursive spinlock issue can occur, such as
the following callchain:
8250_core.c:serial8250_tx_chars() - called with
That bitfield is modified by read + or + write operation. If someone
sets any of the other two bits it might render the lock useless.
Signed-off-by: John Ogness john.ogn...@linutronix.de
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
drivers/tty/serial/8250/8250.h |2 +-
On 07/30/2015 06:54 PM, John Ogness wrote:
uart_write_wakeup() should be called without holding the port lock.
Otherwise a possible recursive spinlock issue can occur, such as
the following callchain:
8250_core.c:serial8250_tx_chars() - called with port locked
Hi John,
On 07/30/2015 06:54 PM, John Ogness wrote:
If DMA is active during a shutdown, a delayed restore of the
registers may be pending. The restore must be performed after
the DMA is stopped, otherwise the delayed restore remains
pending and will fire upon the first DMA TX complete of a
On 07/30/2015 06:54 PM, John Ogness wrote:
That bitfield is modified by read + or + write operation. If someone
sets any of the other two bits it might render the lock useless.
Good catch.
Let's just make all of the fields not bitfield though.
Regards,
Peter Hurley
Signed-off-by: John Ogness
Hi Roger,
I add minor comment about code clean.
After I modified it by myself, I applied it on extcon-fixes.
Best Regards,
Chanwoo Choi
On 07/07/2015 10:06 PM, Roger Quadros wrote:
Users of find_cable_index_by_name() will cause a kernel hang
as the while loop counter is never incremented and
Hello,
I hope some will have some idea:
I am using iperf to check bandwidth and I see that with small tcp
windows in the test there is always high degredation in performance
compared to version without cpuidle.
I've noticed that C3 state (core inactive) is entered several times
during the test,
Add support for vmmc_aux to switch to 1.8v. Also use iov instead of
vdd to indicate io voltage. This is in preparation for adding support
for io signal voltage switch.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 47
According to errata i802, DCRC error interrupts
(MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.
The DCRC interrupt, occurs when the last tuning block fails
(the last ratio tested). The delay from CRC check until the
interrupt is asserted is bigger than the delay until assertion
Now that vmmc regulator is made optional, do not bail out if vmmc
regulator is not found.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/mmc/host/omap_hsmmc.c |7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c
Add a separate function to set the UHSMS field to one
of SDR104, SDR50, DDR50, SDR25 or SDR12 depending on the
inserted SD card. This is required for
tuning to succeed in the case of SDR104/HS200 or SDR50.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/mmc/host/omap_hsmmc.c |
From: Mugunthan V N mugunthan...@ti.com
DRA7 Errata No i834: When using high speed HS200 and SDR104
cards, the functional clock for MMC module will be 192MHz.
At this frequency, the maximum obtainable timeout (DTO =0xE)
in hardware is (1/192MHz)*2^27 = 700ms. Commands taking longer
than 700ms
ios-vdd is set only in mmc_power_up and mmc_power_off and not in
mmc_select_voltage as mentioned in the code comment. This seems to be
legacy code that has been carried for a long time without being
tested.
This will be replaced with a proper voltage switch sequence and
populated in
Miscellaneous fixes in dts files for MMC device tree nodes.
Did basic read/write test in J6, J6 Eco and Beagle-x15
Balaji T K (1):
ARM: dts: dra7-evm: add evm_3v3_sd regulator
Kishon Vijay Abraham I (5):
ARM: dts: dra72-evm: add evm_3v3_sd regulator
ARM: dts: dra72-evm: Set max clock
From: Balaji T K balaj...@ti.com
MMC tuning procedure is required to support SD card
UHS1-SDR104 mode and EMMC HS200 mode.
The tuning function omap_execute_tuning() will only
be called by the MMC/SD core if the corresponding
speed modes are supported by the OMAP silicon which
is set in the mmc
From: Balaji T K balaj...@ti.com
UHS sd card i/o data line can operate at 3V and 1.8V on UHS speed
modes. Add support for signal voltage switch and check for card_busy.
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[kis...@ti.com : cleanup the
Set the clock rate of the functional clock to the max frequency
that is passed to the driver either using pdata or dt.
Also remove unnecessary setting of host-fclk to NULL.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/mmc/host/omap_hsmmc.c |7 ++-
1 file changed, 6
Added a separate function to set the voltage capabilities of the host
controller. Voltage capabilities should be set only once during
controller initialization but bus power can be changed every time there
is a voltage switch and whenever a different card is inserted.
This allows
HCTL is now set based on ios.signal_voltage set by mmc core and not
hardcoded to 3V0 if OMAP_HSMMC_SUPPORTS_DUAL_VOLT is set. If
OMAP_HSMMC_SUPPORTS_DUAL_VOLT is set, it means HCTL can be set to either
3V0 or 1V8. And it should be set to 3V0 or 1V8 depending on
ios.signal_voltage.
Also it is now
Patch series implements voltage switching and tuning for omap_hsmmc
driver.
Did basic read/write test in J6, J6 Eco, Beagle-x15, AM437x EVM,
Beaglebone black, OMAP5 uEVM and OMAP4 PANDA.
Balaji T K (2):
mmc: host: omap_hsmmc: add voltage switch support for UHS SD card
mmc: host: omap_hsmmc:
ldo1_reg in addition to being connected to the io lines is also
connected to the card detect line. On card removal, omap_hsmmc
driver does a regulator_disable causing card detect line to be
pulled down. This raises a card insertion interrupt and once the
MMC core detects there is no card inserted,
ldo1_reg in addition to being connected to the io lines is also
connected to the card detect line. On card removal, omap_hsmmc
driver does a regulator_disable causing card detect line to be
pulled down. This raises a card insertion interrupt and once the
MMC core detects there is no card inserted,
pbias-supply is initialized in dra7.dtsi. Remove redundant initialization
of pbias-supply from MMC1 dt node in am57xx-beagle-x15.dts
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts |1 -
1 file changed, 1 deletion(-)
diff --git
MMC1 supports SDR104 and MMC2 supports HS200 both of which requires
192MHz clock. Set the maximum operating clock frequency to 192 MHz.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts |2 ++
1 file changed, 2 insertions(+)
diff --git
Add a node for evm_3v3_sd using pcf which feeds on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts | 13 +++--
1
From: Nishanth Menon n...@ti.com
SDMMC Card Detect can be used over default GPIO map.
Reported-by: Yan Liu yan-...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Sekhar Nori nsek...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts |
From: Balaji T K balaj...@ti.com
Add a node for evm_3v3_sd using onboard pcf GPIO expander which feeds
on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by:
Hello Dmitry,
Thanks a lot for your feedback.
On 07/30/2015 06:37 PM, Dmitry Torokhov wrote:
On Thu, Jul 30, 2015 at 09:35:17AM -0700, Dmitry Torokhov wrote:
Hi Javier,
On Thu, Jul 30, 2015 at 06:18:25PM +0200, Javier Martinez Canillas wrote:
Hello,
Short version:
This series add the
On 07/29/2015 05:20 PM, Felipe Balbi wrote:
On Mon, Jul 27, 2015 at 11:16:14AM +0200, Robert Baldyga wrote:
Convert endpoint configuration to new capabilities model.
Fixed typo in epc-nulk to epc-bulk.
Signed-off-by: Robert Baldyga r.bald...@samsung.com
---
An I2C driver that supports both OF and legacy platforms, will have
both a OF and I2C ID table. This means that when built as a module,
the aliases will be filled from both tables but currently always an
alias of the form i2c:deviceId is reported, e.g:
$ cat
On Thu, Jul 30, 2015 at 09:35:17AM -0700, Dmitry Torokhov wrote:
Hi Javier,
On Thu, Jul 30, 2015 at 06:18:25PM +0200, Javier Martinez Canillas wrote:
Hello,
Short version:
This series add the missing MODULE_DEVICE_TABLE() for OF and I2C tables
to export that information so
The I2C core always reports the MODALIAS uevent as i2c:client name
regardless if the driver was matched using the I2C id_table or the
of_match_table. So technically there's no need for a driver to export
the OF table since currently it's not used.
In fact, the I2C device ID table is mandatory for
Hi Javier,
On Thu, Jul 30, 2015 at 06:18:25PM +0200, Javier Martinez Canillas wrote:
Hello,
Short version:
This series add the missing MODULE_DEVICE_TABLE() for OF and I2C tables
to export that information so modules have the correct aliases built-in
and autoloading works correctly.
Hello,
Short version:
This series add the missing MODULE_DEVICE_TABLE() for OF and I2C tables
to export that information so modules have the correct aliases built-in
and autoloading works correctly.
Longer version:
Currently it's mandatory for I2C drivers to have an I2C device ID table
Here are some basic OMAP test results for Linux v4.2-rc3.
Logs and other details at:
http://www.pwsan.com/omap/testlogs/test_v4.2-rc3/20150728081114/
Test summary
Build: uImage:
Pass ( 3/ 3): omap1_defconfig, omap1_defconfig_1510innovator_only,
Here are some basic OMAP test results for Linux v4.2-rc4.
Logs and other details at:
http://www.pwsan.com/omap/testlogs/test_v4.2-rc4/20150730100856/
Test summary
Build: uImage:
Pass ( 3/ 3): omap1_defconfig, omap1_defconfig_1510innovator_only,
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