-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi,
On 03/09/15 18:48, Felipe Balbi wrote:
> Hi,
>
> On Thu, Sep 03, 2015 at 03:46:43PM +0300, Roger Quadros wrote:
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA256
>>
>> On 02/09/15 17:34, Felipe Balbi wrote:
>>> On Wed, Sep 02, 2015 at
On 4 September 2015 at 13:59, Vignesh R wrote:
> In addition to providing direct access to SPI bus, some spi controller
> hardwares (like ti-qspi) provide special memory mapped port
> to accesses SPI flash devices in order to increase read performance.
> This means the controller
vsel_reg and enable_reg of the pbias regulator descriptor should actually
have the offset from syscon.
However after
"ARM: dts: : add minimal l4 bus layout with control module
support"
vsel_reg and enable_reg started to have the absolute address because
of address translation that happens due to
PBIAS regulator is required for MMC module in OMAP2, OMAP3, OMAP4,
OMAP5 and DRA7 SoCs. Enable it here.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/configs/multi_v7_defconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Felipe,
On 03/09/15 18:44, Felipe Balbi wrote:
> Hi,
>
> On Thu, Sep 03, 2015 at 03:21:48PM +0300, Roger Quadros wrote:
+ dwc->fsm->id = id;
+ dwc->fsm->b_sess_vld = vbus;
+ usb_otg_sync_inputs(dwc->fsm);
+}
+
Add separate compatible strings for every platform and populate the
pbias register offset in the driver data.
This helps avoid depending on the dt for pbias register offset.
Also update the dt binding documentation with the new compatible
strings.
Suggested-by: Tony Lindgren
Use platform specific compatible strings instead of the common
"ti,pbias-omap" compatible string.
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Tony Lindgren
---
arch/arm/boot/dts/dra7.dtsi |2 +-
arch/arm/boot/dts/omap2430.dtsi |2 +-
On 09/03/2015 08:31 PM, Tony Lindgren wrote:
If gpio-omap probe fails with -EPROBE_DEFER, the GPIO numbering
keeps increasing. Only increase the gpio count if gpiochip_add()
was successful as otherwise the numbers will increase for each
probe attempt.
Cc: Grygorii Strashko
Hi Tony,
On Thursday 03 September 2015 08:40 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I [150903 04:31]:
>> pbias device stopped having memory resource after
>> "ARM: dts: : add minimal l4 bus layout with control module
>> support" got merged. This results in
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 03/09/15 18:51, Felipe Balbi wrote:
> Hi,
>
> On Thu, Sep 03, 2015 at 04:52:02PM +0300, Roger Quadros wrote:
if (on) {
- dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
+ /* OCTL.PeriMode = 0 */
+ reg
"ARM: dts: : add minimal l4 bus
layout with control module support" moved pbias_regulator dt node
from being a child node of ocp to be the child node of
'syscon'. Since 'syscon' doesn't have the 'ranges' property,
address translation fails while trying to convert the address
to resource. Fix it
Hi,
On Thursday 03 September 2015 08:53 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I [150903 02:58]:
>> PBIAS regulator is required for MMC module in OMAP2, OMAP3, OMAP4,
>> OMAP5 and DRA7 SoCs. Enable it here.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>
On 4 September 2015 at 14:00, Kishon Vijay Abraham I wrote:
> vsel_reg and enable_reg of the pbias regulator descriptor should actually
> have the offset from syscon.
>
> However after
> "ARM: dts: : add minimal l4 bus layout with control module
> support"
> vsel_reg and enable_reg
When CONFIG_CHARGER_TWL4030=y and CONFIG_TWL4030_MADC=m we get a
compile error:
drivers/built-in.o: In function `twl4030_charger_update_current':
twl4030_charger.c:(.text+0x504681): undefined reference to
`twl4030_get_madc_conversion'
Use IS_REACHABLE to fix it.
Cc: NeilBrown
* Grygorii Strashko [150904 03:04]:
> On 09/03/2015 08:31 PM, Tony Lindgren wrote:
> >If gpio-omap probe fails with -EPROBE_DEFER, the GPIO numbering
> >keeps increasing. Only increase the gpio count if gpiochip_add()
> >was successful as otherwise the numbers will
* Grazvydas Ignotas [150904 16:36]:
> When CONFIG_CHARGER_TWL4030=y and CONFIG_TWL4030_MADC=m we get a
> compile error:
>
> drivers/built-in.o: In function `twl4030_charger_update_current':
> twl4030_charger.c:(.text+0x504681): undefined reference to
>
On Fri, Sep 04, 2015 at 05:30:24PM +0530, Kishon Vijay Abraham I wrote:
> Add separate compatible strings for every platform and populate the
> pbias register offset in the driver data.
> This helps avoid depending on the dt for pbias register offset.
If there are any changes from the already
On Monday, July 13, 2015 11:20:35 PM Shawn Guo wrote:
> On Tue, Jul 07, 2015 at 04:02:53PM -0400, Joel Porquet wrote:
> > The IRQCHIP_DECLARE macro migrated to 'include/linux/irqchip.h', making it
> > globally accessible.
> >
> > See commit 91e20b5040c67c51aad88cf87db4305c5bd7f79d
> > ("irqchip:
Add qspi memory mapped region entries for AM43xx based SoCs. Also,
update the binding documents for the controller to document this change.
Signed-off-by: Vignesh R
---
Documentation/devicetree/bindings/spi/ti_qspi.txt | 5 +++--
arch/arm/boot/dts/am4372.dtsi
Certain spi controllers may support memory mapped interface to read from
m25p80 type flash devices. This interface provides better read
performance than regular SPI interface.
Call spi_mtd_mmap_read() function, if available, to make use of
memory-mapped interface.
Signed-off-by: Vignesh R
Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
update the binding documents for the controller to document this change.
Signed-off-by: Vignesh R
---
Documentation/devicetree/bindings/spi/ti_qspi.txt | 13 +
arch/arm/boot/dts/dra7.dtsi
In addition to providing direct access to SPI bus, some spi controller
hardwares (like ti-qspi) provide special memory mapped port
to accesses SPI flash devices in order to increase read performance.
This means the controller can automatically send the SPI signals
required to read data from the
ti-qspi controller provides mmap port to read data from SPI flashes.
mmap port is enabled in QSPI_SPI_SWITCH_REG (ctrl module bits may
also need to be updated for some SoCs). The QSPI_SPI_SETUP_REGx needs to
be populated with flash specific information like read opcode, read
mode(quad, dual,
Hi,
This patch series adds support for memory mapped read port of ti-qspi.
ti-qspi has a special memory mapped port through which SPI flash
memories can be accessed directly via SoC specific memory region.
First patch adds a method to pass flash specific information like read
opcode, dummy
24 matches
Mail list logo