On Friday 01 July 2011 08:11 AM, Todd Poynor wrote:
On Fri, Jul 01, 2011 at 07:37:56AM +0530, Rajendra Nayak wrote:
From: Aneesh Vane...@ti.com
Macros for identifying the max frequency supported by various
OMAP4 variants - Expanding along the lines of OMAP3's feature
handling.
[n...@ti.com:
On Friday 01 July 2011 11:55 AM, Tony Lindgren wrote:
* Rajendra Nayakrna...@ti.com [110630 19:03]:
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -331,8 +331,8 @@ static void __init omap3_check_revision(void)
static void __init omap4_check_revision(void)
{
u32
On Thursday 16 February 2012 10:00 PM, Cousson, Benoit wrote:
Hi Aneesh,
[...]
+struct emif_data {
+ u8 duplicate;
+ u8 temperature_level;
+ u32 irq;
+ spinlock_t
From: Benoit Cousson b-cous...@ti.com
Add hwmod data for EMIF IP instances in OMAP4.
Signed-off-by: Benoit Cousson b-cous...@ti.com
---
Changes since RFC:
- Improved commit log
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 110
1 files changed, 110
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane
Add register offsets and bit field definitions
for EMIF module in TI SoCs
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
Changes since RFC:
- Improved commit log
- Corrected copyright year
- Changed file name in order to add other defines
needed by the driver in the same
Signed-off-by: Aneesh V ane...@ti.com
---
Changes since RFC:
- Removed emif_cleanup() function and instead used
devm_* variant of APIs for resource allocations
- Split include/linux/emif.h into two parts. The first
part now becomes include/linux/platform_data/emif_plat.h
and the other part is now
needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
Changes since RFC:
- Added comment in commit log as well as code about
missing
of going back to nominal settings
when temperature falls back to nominal levels.
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
Changes since RFC:
- Improved commit log
- Improved synchronization with thread context
---
drivers/misc/emif.c | 211
-by: Aneesh V ane...@ti.com
---
Changes since RFC:
- Improved commit log
- Changes for errata i728 workaround
---
drivers/misc/emif.c | 147 +++
1 files changed, 147 insertions(+), 0 deletions(-)
diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index
Cc: Greg KH g...@kroah.com
Aneesh V (7):
misc: ddr: add LPDDR2 data from JESD209-2
misc: emif: add register definitions for EMIF
misc: emif: add basic infrastructure for EMIF driver
misc: emif: handle frequency and voltage change events
misc: emif: add interrupt and temperature handling
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
Changes since RFC:
- None
---
drivers/misc/emif.c | 138
Aneesh V (4):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI's EMIF sdram controller
arm: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
misc: emif: add device tree support to emif driver
.../devicetree/bindings/lpddr2/lpddr2-timings.txt
...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
Changes since RFC v4:
- Removed two DDR3 only timing parameters that were
inadvertently added in the binding
---
.../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ++
.../devicetree/bindings/lpddr2/lpddr2.txt | 102
Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
Changes sice RFC v4:
- None
---
.../bindings/memory-controllers/ti/emif.txt| 55
1 files changed, 55 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/ti
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
Changes since RFC v4:
- Removed DDR3 only parameters from
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
Changes since RFC v4:
- Rebased to the latest version of EMIF series
- Replace kzalloc()/kfree() with devm_* variants
---
drivers/misc/emif.c | 289
On Thursday 08 March 2012 10:11 PM, Cousson, Benoit wrote:
Hi Aneesh
On 3/8/2012 4:54 PM, Aneesh V wrote:
From: Benoit Coussonb-cous...@ti.com
Add hwmod data for EMIF IP instances in OMAP4.
Paul has just posted an OMAP4 hwmod series (ARM: OMAP4: hwmod data: add
almost all remaining IP
On Friday 09 March 2012 02:29 AM, Greg KH wrote:
On Thu, Mar 08, 2012 at 09:24:17PM +0530, Aneesh V wrote:
Add a driver for the EMIF SDRAM controller used in TI SoCs
EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds
Hi Grant,
On Friday 09 March 2012 11:07 AM, Grant Likely wrote:
On Thu, 8 Mar 2012 22:03:57 +0530, Aneesh Vane...@ti.com wrote:
Cc: Rajendra Nayakrna...@ti.com
Cc: Benoit Coussonb-cous...@ti.com
Signed-off-by: Aneesh Vane...@ti.com
---
Changes since RFC v4:
- Rebased to the latest version of
to __init_or_module
[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/72855
Aneesh V (7):
misc: ddr: add LPDDR2 data from JESD209-2
misc: emif: add register definitions for EMIF
misc: emif: add basic infrastructure for EMIF driver
misc: emif: handle frequency and voltage change events
misc: emif
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane
Signed-off-by: Aneesh V ane...@ti.com
---
v2:
- replaced __init with __init_or_module
v1:
- Removed emif_cleanup() function and instead used
devm_* variant of APIs for resource allocations
- Split include/linux/emif.h into two parts. The first
part now becomes include/linux/platform_data
Add register offsets and bit field definitions
for EMIF module in TI SoCs
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v1:
- Improved commit log
- Corrected copyright year
- Changed file name in order to add other defines
needed by the driver in the same file
needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v1:
- Added comment in commit log as well as code about
missing integration part
of going back to nominal settings
when temperature falls back to nominal levels.
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v2:
- replaced __init with __init_or_module
v1:
- Improved commit log
- Improved synchronization with thread context
---
drivers/misc/emif.c | 211
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v2:
- Corrected the frequency value shown in
register cache dump
-by: Aneesh V ane...@ti.com
---
v2:
- replaced __init with __init_or_module
- fixed bug in the implementation of i728 errata workaround
v1:
- Improved commit log
- Changes for errata i728 workaround
---
drivers/misc/emif.c | 148 +++
1 files changed, 148
=133183554007498w=2
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Aneesh V (4):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI's EMIF sdram controller
arm: dts: EMIF and LPDDR2 device tree data for OMAP4
...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Aneesh V ane...@ti.com
---
v1:
- Removed two DDR3 only timing parameters that were
inadvertently added in the binding
---
.../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ++
.../devicetree/bindings/lpddr2/lpddr2.txt
Cousson b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Aneesh V ane...@ti.com
---
---
.../bindings/memory-controllers/ti/emif.txt| 55
1 files changed, 55 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Aneesh V ane...@ti.com
---
v1:
- Removed DDR3 only parameters
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Aneesh V ane...@ti.com
---
v2:
- Addressed comments from Grant Likely:
Converted occurences of __init to __init_or_module
Removed un-necessary instances of #ifdef
On Friday 16 March 2012 12:32 AM, Greg KH wrote:
On Thu, Mar 15, 2012 at 11:47:31PM +0530, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data
On Friday 16 March 2012 12:34 AM, Greg KH wrote:
On Thu, Mar 15, 2012 at 11:47:30PM +0530, Aneesh V wrote:
Add a driver for the EMIF SDRAM controller used in TI SoCs
EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane
.
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v4:
- Removed 'ifndef __ASSEMBLY__' from jedec_ddr.h
- Updated commit log to be more specific on where
this patch is used currently
v3:
- Converted EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
- Removed un-necessary newline
v1:
- Moved
Hi Greg,
On Friday 16 March 2012 12:32 AM, Greg KH wrote:
On Thu, Mar 15, 2012 at 11:47:31PM +0530, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data
On Saturday 17 March 2012 03:13 AM, Greg KH wrote:
On Sat, Mar 17, 2012 at 02:20:07AM +0530, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data
the hwmod patch as Paul has already posted a
a hwmod series [1] that adds hwmod for EMIF
- Converted instances of __init to __init_or_module
[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/72855
Aneesh V (7):
misc: ddr: add LPDDR2 data from JESD209-2
misc: emif: add register definitions
.
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v4:
- Removed 'ifndef __ASSEMBLY__' from jedec_ddr.h
- Updated commit log to be more specific on where
this patch is used currently
- Converted EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
- Removed un-necessary newline
v1:
- Moved
Add register offsets and bit field definitions
for EMIF module in TI SoCs
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v1:
- Improved commit log
- Corrected copyright year
- Changed file name in order to add other defines
needed by the driver in the same file
needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v1:
- Added comment in commit log as well as code about
missing integration part
of going back to nominal settings
when temperature falls back to nominal levels.
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v2:
- replaced __init with __init_or_module
v1:
- Improved commit log
- Improved synchronization with thread context
---
drivers/misc/emif.c | 211
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Cc: Greg KH g...@kroah.com
Signed-off-by: Aneesh V ane...@ti.com
---
v2:
- Corrected the frequency value shown in
register cache dump
On Saturday 17 March 2012 03:03 AM, Greg KH wrote:
On Sat, Mar 17, 2012 at 02:28:47AM +0530, Aneesh V wrote:
Hi Greg,
[...]
I have fixed these comments and pushed my latest patches at:
git://github.com/aneeshv/linux.git
branch: emif-upstream-v4
Sorry, but I don't take git pulls for stuff
-by: Aneesh V ane...@ti.com
---
v2:
- replaced __init with __init_or_module
- fixed bug in the implementation of i728 errata workaround
v1:
- Improved commit log
- Changes for errata i728 workaround
---
drivers/misc/emif.c | 148 +++
1 files changed, 148
Signed-off-by: Aneesh V ane...@ti.com
---
v2:
- replaced __init with __init_or_module
v1:
- Removed emif_cleanup() function and instead used
devm_* variant of APIs for resource allocations
- Split include/linux/emif.h into two parts. The first
part now becomes include/linux/platform_data
Hi Paul,
On 04/11/2012 07:44 PM, Paul Walmsley wrote:
Cc Mark Greer, Mark Salter
Hi Greg, Aneesh,
On Sat, 17 Mar 2012, Aneesh V wrote:
Add a driver for the EMIF SDRAM controller used in TI SoCs
EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2
-post of the RFC that was posted to devicetree-discuss ml,
now sent to a larger audience and looping out an internal list.
Please ignore the previous version.
Aneesh V (3):
dt: device tree bindings for DDR memories
dt: device tree bindings for TI's EMIF sdram controller
arm/dts: EMIF and lpddr2
'
for specifying the AC timing parameters of the memory device
at different speed-bins.
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
Documentation/devicetree/bindings/ddr/ddr.txt | 114
.../devicetree
Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
.../bindings/memory-controllers/ti/emif.txt| 64
1 files changed, 64 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git
Device tree data for the EMIF sdram controllers in OMAP4
and DDR memories attached to OMAP4 boards.
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/boot/dts/omap-common-devices.dtsi | 63
arch
Hi Olof,
On Monday 19 December 2011 10:22 PM, Olof Johansson wrote:
Hi,
Some comments below, but also a more general question: How much of
this generic data makes sense to encode in the device tree? Final
hardware configuration usually has to take into consideration board
layout/signal delays,
On Monday 19 December 2011 10:26 PM, Olof Johansson wrote:
Hi,
Fewer comments here. :) But see below.
On Mon, Dec 19, 2011 at 6:05 AM, Aneesh Vane...@ti.com wrote:
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,64 @@
+* EMIF family of TI
On Monday 19 December 2011 10:29 PM, Olof Johansson wrote:
Oh wait, when I saw 3/3 I realized the following too:
On Mon, Dec 19, 2011 at 6:05 AM, Aneesh Vane...@ti.com wrote:
+- phy-type : string indicating the phy type. Should be one of the
+ following:
+
+ phy-type-omap4 : PHY used
On Tuesday 20 December 2011 04:31 AM, Rob Herring wrote:
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently,
we have added properties for only
On Tuesday 20 December 2011 05:05 AM, Tony Lindgren wrote:
* Rob Herringrobherri...@gmail.com [111219 14:29]:
On 12/19/2011 08:05 AM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
snip
In general, is it really feasible to parse the DTB before DDR is
initialized?
Changing timings is still needed for DVFS during runtime.
But we can boot to userspace with bootloader set timings, so I'm
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
snip
In general, is it really feasible to parse the DTB before DDR is
initialized?
Changing timings is still needed for DVFS during runtime
Hi Olof,
On Monday 09 January 2012 11:12 AM, Olof Johansson wrote:
Hi,
On Sun, Jan 8, 2012 at 9:23 AM, Aneesh Vane...@ti.com wrote:
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
snip
Santosh, Russel,
On Monday 16 January 2012 06:52 PM, Shilimkar, Santosh wrote:
On Mon, Jan 16, 2012 at 2:13 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Mon, Jan 16, 2012 at 01:43:03PM +0100, Shilimkar, Santosh wrote:
This code will be in assembly and that's what I have
been
Hi Olof,
On Saturday 14 January 2012 01:06 AM, Aneesh V wrote:
Hi Olof,
snip
We wish to drop the DDR3 support because we have concluded that our
platforms with DDR3 memories will not scale DDR frequency due to
limitations in DDR3 protocol(operating frequency can vary only in a
small range
Hi Catalin,
On Tuesday 17 January 2012 05:41 PM, Catalin Marinas wrote:
On Tue, Jan 17, 2012 at 08:54:44AM +, Joe Woodward wrote:
So, is the upshot of this that the kernel isn't going to be in a
position to enable the L2/outer cache on OMAP3 (due to the need for
hacky/unmaintainable code)?
Hi Olof,
On Tuesday 20 December 2011 12:39 PM, Aneesh V wrote:
Hi Olof,
On Monday 19 December 2011 10:22 PM, Olof Johansson wrote:
Hi,
Some comments below, but also a more general question: How much of
this generic data makes sense to encode in the device tree? Final
hardware configuration
-post of the RFC that was posted to devicetree-discuss ml,
now sent to a larger audience and looping out an internal list.
Please ignore the previous version.
Aneesh V (3):
dt: device tree bindings for DDR memories
dt: device tree bindings for TI's EMIF sdram controller
arm/dts: EMIF and lpddr2
'
for specifying the AC timing parameters of the memory device
at different speed-bins.
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
Changes in RFC v2:
* Removed the manufacturer property and added it in
compatible property instead
Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
.../bindings/memory-controllers/ti/emif.txt| 62
1 files changed, 62 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git
Device tree data for the EMIF sdram controllers in OMAP4
and DDR memories attached to OMAP4 boards.
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 64 +
arch
On Thursday 19 January 2012 07:58 PM, Aneesh V wrote:
This is an RFC to add new device tree bindings for DDR memories and
EMIF - TI's DDR SDRAM controller.
The first patch adds bindings for DDR memories. Currently,
we have added properties for only DDR3 and LPDDR2 memories.
However, the binding
and LPDDR2 memories attached to them on various boards.
Thanks to Rajendra for answering my numerous queries on device tree.
Changes in RFC v3:
* Removed support for DDR3
* Incorporated review comments from Olof
Aneesh V (3):
dt: device tree bindings for DDR memories
dt: device tree bindings for TI's
...@ti.com
Cc: Olof Johansson o...@lixom.net
Signed-off-by: Aneesh V ane...@ti.com
Changes in RFC v2:
* Removed the manufacturer property and added it in
compatible property instead
* Changed the DDR device names in example to indicate
the part number
Changes in RFC v3:
* Removed DDR3 support
Cousson b-cous...@ti.com
Cc: Olof Johansson o...@lixom.net
Signed-off-by: Aneesh V ane...@ti.com
---
Changes in RFC v3:
* Fixed review comments from RFC v2
---
.../bindings/memory-controllers/ti/emif.txt| 49
1 files changed, 49 insertions(+), 0 deletions(-)
create mode
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR memory devices attached to OMAP4 boards.
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Olof Johansson o...@lixom.net
Signed-off-by: Aneesh V ane...@ti.com
---
Changes in RFC v3:
* Fixed review comments
Hi Olof,
On Friday 20 January 2012 01:01 AM, Olof Johansson wrote:
Hi,
Sorry for the delay in responding, I know you pinged me about it yesterday.
On Thu, Jan 19, 2012 at 6:31 AM, Aneesh Vane...@ti.com wrote:
device tree bindings for LPDDR2 SDRAM memories compliant
to JESD209-2 standard.
On Saturday 21 January 2012 12:58 PM, Olof Johansson wrote:
On Thu, Jan 19, 2012 at 12:56 PM, Aneesh Vane...@ti.com wrote:
Hi Olof,
On Friday 20 January 2012 01:01 AM, Olof Johansson wrote:
Hi,
Sorry for the delay in responding, I know you pinged me about it
yesterday.
On Thu, Jan 19,
Hi Catalin,
On Friday 27 January 2012 11:00 PM, Catalin Marinas wrote:
On Fri, Jan 20, 2012 at 08:57:11AM +, Joe Woodward wrote:
So I re-iterate that we need to have solution to this problem.
... I don't want to be a pain, but it seems to me that this dicussion
didn't reach a full
doesn't have DVFS support yet,
testing was done using a test module.
- Temperature alert handling was tested with simulated interrupts
and faked temperature values as testing all cases in real-life
scenarios is difficult.
Aneesh V (7):
misc: ddr: add LPDDR2 data from JESD209-2
misc: emif: add
From: Benoit Cousson b-cous...@ti.com
Signed-off-by: Benoit Cousson b-cous...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 110
1 files changed, 110 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data.
This data will useful for memory controller device drivers
Signed-off-by: Aneesh V ane...@ti.com
---
drivers/misc
Signed-off-by: Aneesh V ane...@ti.com
---
drivers/misc/emif_regs.h | 461 ++
1 files changed, 461 insertions(+), 0 deletions(-)
create mode 100644 drivers/misc/emif_regs.h
diff --git a/drivers/misc/emif_regs.h b/drivers/misc/emif_regs.h
new file mode
EMIF is an SDRAM controller used in various Texas Instruments
SoCs. EMIF supports, based on its revision, one or more of
LPDDR2/DDR2/DDR3 protocols.
Add the basic infrastructure for EMIF driver that includes
driver registration, probe, parsing of platform data etc.
Signed-off-by: Aneesh V ane
Change SDRAM timings and other settings as necessary
on voltage and frequency changes. We calculate these
register settings based on data from the device data
sheet and inputs such a frequency, voltage state(stable
or ramping), temperature level etc.
Signed-off-by: Aneesh V ane...@ti.com
-by: Aneesh V ane...@ti.com
---
drivers/misc/emif.c | 209 ++-
1 files changed, 207 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 36ba6f4..5c2b0ae 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
Add settings that are not dependent on frequency
or any other transient parameters
Signed-off-by: Aneesh V ane...@ti.com
---
drivers/misc/emif.c | 147 +++
1 files changed, 147 insertions(+), 0 deletions(-)
diff --git a/drivers/misc/emif.c b
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)
Signed-off-by: Aneesh V ane...@ti.com
---
drivers/misc/emif.c | 129 +++
1 files changed, 129
* Incorporated review comments from Olof
Changes from RFC v3 to RFC v4:
* Added a new patch to add DT support in the EMIF driver
[1] http://marc.info/?l=linux-omapm=132835811606125w=2
Aneesh V (4):
dt: device tree bindings for LPDDR2 memories
dt: emif: device tree bindings for TI's EMIF sdram
...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
---
.../devicetree/bindings/lpddr2/lpddr2-timings.txt | 54 ++
.../devicetree/bindings/lpddr2/lpddr2.txt | 102
2 files changed, 156 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree
Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
---
.../bindings/memory-controllers/ti/emif.txt| 55
1 files changed, 55 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
diff --git
Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 71
Cc: Rajendra Nayak rna...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
drivers/misc/emif.c | 281 ++-
1 files changed, 280 insertions(+), 1 deletions(-)
diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
On Thursday 09 February 2012 04:55 PM, Bedia, Vaibhav wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of V, Aneesh
Sent: Saturday, February 04, 2012 5:46 PM
To: linux-omap@vger.kernel.org
Cc:
Santosh,
Thanks for the review.
On Thursday 16 February 2012 03:32 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
From: Benoit Coussonb-cous...@ti.com
One line of change log will do here.
Ok. Will add.
br,
Aneesh
--
To unsubscribe from this list: send
On Thursday 16 February 2012 03:37 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:
1. Addressing information for LPDDR2 memories of different
densities and types(S2/S4)
2. AC timing data
On Thursday 16 February 2012 03:40 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Signed-off-by: Aneesh Vane...@ti.com
---
drivers/misc/emif_regs.h | 461 ++
1 files changed, 461 insertions(+), 0 deletions
On Thursday 16 February 2012 04:03 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
EMIF is an SDRAM controller used in various Texas Instruments
SoCs. EMIF supports, based on its revision, one or more of
LPDDR2/DDR2/DDR3 protocols.
Add the basic
On Thursday 16 February 2012 04:08 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Change SDRAM timings and other settings as necessary
on voltage and frequency changes. We calculate these
register settings based on data from the device data
sheet and inputs
On Thursday 16 February 2012 04:11 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Add an ISR for EMIF that:
1. reports details of access errors
2. takes action on thermal events
On thermal events SDRAM timing parameters are
adjusted
On Thursday 16 February 2012 04:40 PM, Alan Cox wrote:
On Thu, 16 Feb 2012 15:57:57 +0530
Aneesh Vane...@ti.com wrote:
On Thursday 16 February 2012 03:37 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
add LPDDR2 data from the JEDEC spec JESD209-2
On Thursday 16 February 2012 04:14 PM, Santosh Shilimkar wrote:
On Saturday 04 February 2012 05:46 PM, Aneesh V wrote:
Add settings that are not dependent on frequency
or any other transient parameters
Expand the changelog a bit. One time settings like
SDRAM_CONFIG, PHY_CONTROL, TEMP alert
1 - 100 of 105 matches
Mail list logo
