Re: AM335x, early printk
Hi! You need to add 'earlyprintk' in the kernel command line, given (I suppose) by U-Boot. I hope this helps! Jean On Mon, Aug 19, 2013 at 1:21 PM, Sebastian Andrzej Siewior bige...@linutronix.de wrote: Hi, I activated: [*] Kernel low-level debugging functions Kernel low-level debugging port (Kernel low-level debugging messages via OMAP2PLUS UART) Low-level debug console UART (AM33XX UART1) [*] Early printk and booted my am335x-evm. I haven't seen any early output in the decompressor or during the kernel boot. I believe that all I saw is just regular ttyO0 output. I saw also: |44e09000.serial: ttyO0 at MMIO 0x44e09000 (irq = 88) is a OMAP UART0 |console [ttyO0] enabled and I would also except the bootconsole (if any) to be deactivated here. What am I missing? Sebastian -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: OMAP2+: Drop plat/cpu.h for omap2plus
Hi Tony, On Sun, Dec 16, 2012 at 9:03 PM, Tony Lindgren t...@atomide.com wrote: The cpu_is_omap macros are now local to arch/arm/mach-omap2 in soc.h and plat/cpu.h can finally be dropped for omap2+. Thanks everybody for help with fixing the drivers. Great! Note that we can now also remove the unused plat/cpu.h from smartreflex.c and isp.c as they will cause compile errors with ARCH_MULTIPLATFORM enabled. Cc: Jean Pihet jean.pi...@newoldbits.com Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Laurent Pinchart laurent.pinch...@ideasonboard.com Cc: Mauro Carvalho Chehab mche...@redhat.com Signed-off-by: Tony Lindgren t...@atomide.com --- arch/arm/mach-omap2/drm.c |1 - arch/arm/mach-omap2/dss-common.c |3 +-- arch/arm/mach-omap2/prm2xxx.c |3 +-- arch/arm/mach-omap2/prm3xxx.c |3 +-- arch/arm/plat-omap/include/plat/cpu.h |4 drivers/media/platform/omap3isp/isp.c |2 -- drivers/power/avs/smartreflex.c |2 -- 7 files changed, 3 insertions(+), 15 deletions(-) For the smartreflex driver: Acked-by: Jean Pihet j-pi...@ti.com Regards, Jean ... diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c index a17d084..6b2238b 100644 --- a/drivers/power/avs/smartreflex.c +++ b/drivers/power/avs/smartreflex.c @@ -27,8 +27,6 @@ #include linux/pm_runtime.h #include linux/power/smartreflex.h -#include plat/cpu.h - #define SMARTREFLEX_NAME_LEN 16 #define NVALUE_NAME_LEN40 #define SR_DISABLE_TIMEOUT 200 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/8] ARM: OMAP2+: PM QoS: control the power domains next state from the constraints
Hi Paul, On Tue, Dec 11, 2012 at 1:05 AM, Paul Walmsley p...@pwsan.com wrote: Hi On Tue, 18 Sep 2012, Jean Pihet wrote: When a PM QoS device latency constraint is requested or removed the constraint is stored in the constraints list of the corresponding power domain, then the aggregated constraint value is applied by programming the next functional power state using pwrdm_set_fpwrst. The per-device PM QoS locking requires a spinlock to be used. The reasons is that some drivers need to use the per-device PM QoS functionality from interrupt context or spinlock protected context, as reported by Djamil. An example of such a driver is the OMAP HSI (high-speed synchronous serial interface) driver which needs to control the IP block idle state from the FIFO empty state, from interrupt context. Tested on OMAP3 Beagleboard and OMAP4 Pandaboard in RET/OFF using wake-up latency constraints on MPU, CORE and PER. Signed-off-by: Jean Pihet j-pi...@ti.com Cc: Djamil Elaidi d-ela...@ti.com This patch has been changed here. Details below, but the major changes Thanks for reworking this! were to fix the locking and to not attempt GFP_ATOMIC allocations. Hopefully the reasons why are clear, but if not, feel free to ask. This is fine. Note about the locking and the allocations: The locking had been changed to spinlocks because of the potential need to call the per-device PM QoS API from interrupt or spinlock protected context. Unfortunately the per-device PM QoS cannot be called from such a context, because (1) it internally uses mutexes and (2) it relies on a blocking notification mechanism. However after discussion with Rafael W at ELCE, the PM QoS framework will be reworked to get rid of the overly complex notification mechanism [1]. The generic power domain framework will be used instead to apply the constraints to the power domains at the time the power domain is set up to transition to a lower power state (e.g. when the last active device of a power domain is set up to idle automatically). The implementation on OMAP needs some thinking. This very patch is ok but the registration mechanism to the PM QoS framework [2] will need to change. [1] http://marc.info/?l=linux-pmm=134856516908683w=2 [2] http://marc.info/?l=linux-omapm=134795836304294w=2 The following patch has only been compile-tested, and a few more minor changes will probably be needed. Reviewed only from my side. More comments here below. - Paul From: Jean Pihet jean.pi...@newoldbits.com Date: Sun, 9 Dec 2012 18:38:12 -0700 Subject: [PATCH] ARM: OMAP2+: PM QoS: control the power domains next state from the constraints When a PM QoS device latency constraint is requested or removed the constraint is stored in the constraints list of the corresponding power domain, then the aggregated constraint value is applied by programming the next functional power state using pwrdm_set_fpwrst. The per-device PM QoS locking requires a spinlock to be used. The reasons is that some drivers need to use the per-device PM QoS functionality from interrupt context or spinlock protected context, as reported by Djamil. An example of such a driver is the OMAP HSI (high-speed synchronous serial interface) driver which needs to control the IP block idle state from the FIFO empty state, from interrupt context. Tested on OMAP3 Beagleboard and OMAP4 Pandaboard in RET/OFF using wake-up latency constraints on MPU, CORE and PER. Has it been tested already? Signed-off-by: Jean Pihet j-pi...@ti.com Cc: Djamil Elaidi d-ela...@ti.com [p...@pwsan.com: updated to apply; renamed *state to *fpwrst and define as u8; use existing powerdomain spinlock; pack the struct powerdomain variables; removed the GFP_ATOMIC allocation; drop expensive operations from the _pwrdm_wakeuplat_update_pwrst() debug; ensure that the entire wakeuplat update process takes place under the spinlock; remove UNSUP_STATE; remove assumption that fpwrsts start at 0; remove unnecessary plist_empty test from update path; standardize 'wakeuplat' naming; add kerneldoc] XXX conform debug to other powerdomain debugging There are a few 'XXX' comments left. --- arch/arm/mach-omap2/powerdomain.c | 208 + arch/arm/mach-omap2/powerdomain.h | 27 - 2 files changed, 233 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 7caceaa..bcba0af 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -21,8 +21,10 @@ #include linux/kernel.h #include linux/types.h #include linux/list.h +#include linux/slab.h #include linux/errno.h #include linux/string.h +#include linux/pm_qos.h #include linux/spinlock.h #include linux/sched.h #include linux/seq_file.h @@ -125,6 +127,9 @@ static int _pwrdm_register(struct powerdomain *pwrdm) for (i = 0; i PWRDM_FPWRSTS_COUNT; i++) pwrdm
Re: [RFC 1/5] ARM: CORESIGHT: Add generic lock/unlock helpers
Hi Jon, Will,
On Thu, Dec 13, 2012 at 8:18 PM, Jon Hunter jon-hun...@ti.com wrote:
On 12/13/2012 08:58 AM, Will Deacon wrote:
Hi Jon,
On Wed, Dec 12, 2012 at 09:43:04PM +, Jon Hunter wrote:
The Cross Trigger Interface (CTI) helpers in cti.h include definitions
for the Coresight Lock Access Register (LAR) and Lock Status Register
(LSR). These registers are already defined in coresight.h and so rather
than having multiple definitions, just use the definitions from
coresight.h.
Add the following coresight macros ...
- coresight_unlock() -- Unlocks coresight module
- coresight_lock() -- Locks coresight module
Use the above macros for ETB, ETM and CTI. The do-while(0) statement
has been removed from the macro as it is not a multi-line macro.
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
arch/arm/include/asm/cti.h| 16 +++-
arch/arm/include/asm/hardware/coresight.h | 16
2 files changed, 11 insertions(+), 21 deletions(-)
[...]
diff --git a/arch/arm/include/asm/hardware/coresight.h
b/arch/arm/include/asm/hardware/coresight.h
index 7ecd793..dcd0e66 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -141,17 +141,17 @@
#define ETBFF_TRIGEVT BIT(9)
#define ETBFF_TRIGFLBIT(10)
-#define etb_writel(t, v, x) \
-(__raw_writel((v), (t)-etb_regs + (x)))
+#define etb_writel(t, v, x) (__raw_writel((v), (t)-etb_regs + (x)))
#define etb_readl(t, x) (__raw_readl((t)-etb_regs + (x)))
-#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
-#define etm_unlock(t) \
-do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+#define etb_lock(t) coresight_lock((t)-etb_regs)
+#define etb_unlock(t) coresight_unlock((t)-etb_regs)
+#define etm_lock(t) coresight_lock((t)-etm_regs)
+#define etm_unlock(t) coresight_unlock((t)-etm_regs)
-#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
-#define etb_unlock(t) \
-do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+#define coresight_lock(base) (__raw_writel(0, base + CSMR_LOCKACCESS))
+#define coresight_unlock(base) \
+(__raw_writel(UNLOCK_MAGIC, base + CSMR_LOCKACCESS))
#endif /* __ASM_HARDWARE_CORESIGHT_H */
How about we take this opportunity to divorce the more general coresight
bits from the etb specific parts, like you've done for the cti. We could
move the ETB stuff out into asm/etb.h (although it might be nice to keep all
the coresight device headers in one place... answers on a postcard) and just
have the architected coresight functionality in this header.
Yes I have been wondering about that too. Long term it would be good to
find a home in the drivers directory for all these coresight devices
too. For now, we could extract the etb/etm parts from coresight.h into
etb.h and etm.h, respectively.
I am now writing a HW trace driver that extracts traces from the CMI
and PMI IP blocks (and later L2CC). It is still in early development
status.
The idea I have in mind is to have the implementation in
drivers/power/hw_trace. Eventually this directory would contain the
drivers for ETM/ETB, CMI, PMI and also the coresight support. It would
be architected so that the lower level drivers export the necessary
functions for the higher level code to use the resource. Example: the
PMI driver would use the ETB and coresight drivers.
What do you think?
Regards,
Jean
Cheers
Jon
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Re: [PATCH 06/10] ARM: OMAP2+: powerdomain/clockdomain: add a per-powerdomain spinlock
Paul, -resending in plain text only, sorry about that- On Sun, Dec 9, 2012 at 2:23 AM, Paul Walmsley p...@pwsan.com wrote: Add a per-powerdomain spinlock. Use that instead of the clockdomain spinlock. Add pwrdm_lock()/pwrdm_unlock() functions to allow other code to acquire or release the powerdomain spinlock without reaching directly into the struct powerdomain. Since clockdomains are part of powerdomains it seems weird for the clockdomain code to take a powerdoamin lock. Is there a reason why the powerdomain could not take the lock before calling the clockdomain functions? Also, are the lock and nolock version the clockdomain function needed? Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/12] ARM: OMAP3xxx: PM: convert to use the functional power states API
Paul, -resending in plain text only, sorry about that- On Sun, Dec 9, 2012 at 6:53 PM, Paul Walmsley p...@pwsan.com wrote: From: Jean Pihet jean.pi...@newoldbits.com Use the functional power states as the API to control power domains: - use the PWRDM_FUNC_PWRST_* macros for the power states and logic settings, - the function pwrdm_set_next_fpwrst(), which controls the power domains next power and logic settings, shall be used instead of pwrdm_set_next_pwrst() to program the power domains next states, - the function pwrdm_set_fpwrst(), which programs the power domains power and logic settings, shall be used instead of omap_set_pwrdm_state(). Signed-off-by: Jean Pihet j-pi...@ti.com [p...@pwsan.com: split the original patch into OMAP2/3/4 variants; clean up omap3_save_secure_ram_context(); fix commit message; warn if sets fail; various other changes] There are a lot of 'XXX' comments, can this be fixed by a proper comment? Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/10] ARM: OMAP2+: PM/powerdomain: move omap_set_pwrdm_state() to powerdomain code
Hi Paul,
-resending in plain text only, sorry about that-
On Sun, Dec 9, 2012 at 2:23 AM, Paul Walmsley p...@pwsan.com wrote:
Move omap_set_pwrdm_state() from the PM code to the powerdomain code,
and refactor it to split it up into several functions. A subsequent patch
will rename it to conform with the existing powerdomain function names.
Glad to see this rather cryptic function getting a rewrite. It had
never been clear what the function is doing so I think it owes some
more comments.
More comments below.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Jean Pihet jean.pi...@newoldbits.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
arch/arm/mach-omap2/pm.c | 61
arch/arm/mach-omap2/pm.h |1
arch/arm/mach-omap2/powerdomain.c | 112
+++--
arch/arm/mach-omap2/powerdomain.h |3 +
4 files changed, 85 insertions(+), 92 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index cc8ed0f..2e2a897 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -76,10 +76,6 @@ static void __init omap2_init_processor_devices(void)
}
}
-/* Types of sleep_switch used in omap_set_pwrdm_state */
-#define FORCEWAKEUP_SWITCH 0
-#define LOWPOWERSTATE_SWITCH 1
-
int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
{
if ((clkdm-flags CLKDM_CAN_ENABLE_AUTO)
@@ -92,63 +88,6 @@ int __init omap_pm_clkdms_setup(struct clockdomain *clkdm,
void *unused)
}
/*
- * This sets pwrdm state (other than mpu core. Currently only ON
- * RET are supported.
- */
-int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst)
-{
- u8 curr_pwrst, next_pwrst;
- int sleep_switch = -1, ret = 0, hwsup = 0;
-
- if (!pwrdm || IS_ERR(pwrdm))
- return -EINVAL;
-
- while (!(pwrdm-pwrsts (1 pwrst))) {
- if (pwrst == PWRDM_POWER_OFF)
- return ret;
- pwrst--;
- }
-
- next_pwrst = pwrdm_read_next_pwrst(pwrdm);
- if (next_pwrst == pwrst)
- return ret;
-
- curr_pwrst = pwrdm_read_pwrst(pwrdm);
- if (curr_pwrst PWRDM_POWER_ON) {
- if ((curr_pwrst pwrst)
- (pwrdm-flags PWRDM_HAS_LOWPOWERSTATECHANGE)) {
- sleep_switch = LOWPOWERSTATE_SWITCH;
- } else {
- hwsup = clkdm_in_hwsup(pwrdm-pwrdm_clkdms[0]);
- clkdm_wakeup(pwrdm-pwrdm_clkdms[0]);
- sleep_switch = FORCEWAKEUP_SWITCH;
- }
- }
-
- ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
- if (ret)
- pr_err(%s: unable to set power state of powerdomain: %s\n,
- __func__, pwrdm-name);
-
- switch (sleep_switch) {
- case FORCEWAKEUP_SWITCH:
- if (hwsup)
- clkdm_allow_idle(pwrdm-pwrdm_clkdms[0]);
- else
- clkdm_sleep(pwrdm-pwrdm_clkdms[0]);
- break;
- case LOWPOWERSTATE_SWITCH:
- pwrdm_set_lowpwrstchange(pwrdm);
- pwrdm_state_switch(pwrdm);
- break;
- }
-
- return ret;
-}
-
-
-
-/*
* This API is to be called during init to set the various voltage
* domains to the voltage as per the opp table. Typically we boot up
* at the nominal voltage. So this function finds out the rate of
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 686137d..707e9cb 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -33,7 +33,6 @@ static inline int omap4_idle_init(void)
extern void *omap3_secure_ram_storage;
extern void omap3_pm_off_mode_enable(int);
extern void omap_sram_idle(void);
-extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
extern int (*omap_pm_suspend)(void);
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 97b3881..05f00660 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -921,35 +921,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
return (pwrdm pwrdm-flags PWRDM_HAS_HDWR_SAR) ? 1 : 0;
}
-/**
- * pwrdm_set_lowpwrstchange - Request a low power state change
- * @pwrdm: struct powerdomain *
- *
- * Allows a powerdomain to transtion to a lower power sleep state
- * from an existing sleep state without waking up the powerdomain.
- * Returns -EINVAL if the powerdomain pointer is null or if the
- * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0
- * upon success.
- */
Can this kerneldoc be reused in the new code?
Could you add some more documentation here?
What is the goal of the function
Re: [PATCH 02/12] ARM: OMAP2+: PM: introduce power domains functional states
Hi Paul,
-resending in plain text only, sorry about that-
On Sun, Dec 9, 2012 at 6:53 PM, Paul Walmsley p...@pwsan.com wrote:
From: Jean Pihet jean.pi...@newoldbits.com
Introduce the functional states for power domains, which include
the power states and the logic states.
This patch provides the API functions to set and read the power
domains functional state and internal functions to convert between
the functional (i.e. logical) and the internal (or registers) values.
In the new API only the functions pwrdm_set_next_fpwrst() and
pwrdm_set_fpwrst() shall be used to change a power domain target
state, along with the associated PWRDM_FUNC_* macros as the state
parameters.
Note about the power domains allowed states:
Power domains have varied capabilities, as defined by the value of
the pwrsts and pwrsts_logic_ret fields of the powerdomain struct.
When reading or setting a low power state such as OFF/RET, a specific
requested state may not be supported on the given power domain.
In the states conversion functions a power or logic state is first
looked for in the lower power states in order to maximize the power
savings, then if not found in the higher power states. An iteration
function is used, as suggested by Rajendra Nayak rna...@ti.com
This function is temporary and will be removed later in the series.
This functionality brings consistency in the functional power states
core code and acts as a guard against hardware implementations
discrepancies, e.g. some power domains only support the RET logic
state although reading the logic state registers (previous, current
and next) always returns OFF. The DSS power domain on OMAP3 is an
example.
Signed-off-by: Jean Pihet j-pi...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Nishanth Menon n...@ti.com
[p...@pwsan.com: add offset for functional powerstates so it's not
possible to confuse them with the old API; use one fn to convert func
pwrsts to low-level hardware bits; skip hardware reads when hardware
logic retst and logic pwrst bits are missing; fix kerneldoc and
commit message; remove unnecessary PWRDM_LOGIC_MEM_PWRST_* macros;
combine spinlock patch into this patch; expand the number of operations
which take the spinlock]
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/powerdomain.c | 525
+
arch/arm/mach-omap2/powerdomain.h | 33 ++
2 files changed, 553 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 94b89a25..18f33de 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1,7 +1,7 @@
...
+/**
+ * _match_pwrst: determine the closest supported power state
+ * @pwrsts: list of allowed states, defined as a bitmask
+ * @pwrst: initial state to be used as a starting point
+ * @min: minimum (i.e. lowest consumption) allowed state
+ * @max: maximum (i.e. highest consumption) allowed state
+ *
+ * Search down then up for a valid state from a list of allowed
+ * states. Used by states conversion functions (_pwrdm_fpwrst_to_*)
+ * to look for allowed power and logic states for a powerdomain.
+ * Returns the matching allowed state. XXX Deprecated. The software
+ * should not try to program unsupported powerstates.
Why is this new code already deprecated? Does this require a rewrite?
+ */
+static int _match_pwrst(u32 pwrsts, int pwrst, int min, int max)
+{
+ int found = 1, new_pwrst = pwrst;
+
+ /*
+* If the power domain does not allow any state programmation
+* return the max state which is always allowed
+*/
+ if (!pwrsts)
+ return max;
+
+ /*
+* Search lower: if the requested state is not supported
+* try the lower states, stopping at the minimum allowed
+* state
+*/
+ while (!(pwrsts (1 new_pwrst))) {
+ if (new_pwrst = min) {
+ found = 0;
+ break;
+ }
+ new_pwrst--;
+ }
+
+ /*
+* Search higher: if no lower state found fallback to the higher
+* states, stopping at the maximum allowed state
+*/
+ if (!found) {
+ new_pwrst = pwrst;
+ while (!(pwrsts (1 new_pwrst))) {
+ if (new_pwrst = max) {
+ new_pwrst = max;
+ break;
+ }
+ new_pwrst++;
+ }
+ }
+
+ return new_pwrst;
+}
+
+/**
+ * _pwrdm_fpwrst_to_pwrst - Convert functional (i.e. logical) to
+ * internal (i.e. registers) values for the power domains states.
+ * @pwrdm: struct powerdomain * to convert the values for
+ * @fpwrst: functional power state
+ * @pwrdm_pwrst: ptr to u8 to return
Re: [PATCH 06/12] ARM: OMAP44xx: PM: convert to use the functional power states API
Paul,
On Sun, Dec 9, 2012 at 6:53 PM, Paul Walmsley p...@pwsan.com wrote:
From: Jean Pihet jean.pi...@newoldbits.com
Use the functional power states as the API to control power
domains:
- use the PWRDM_FUNC_PWRST_* and PWRDM_LOGIC_MEM_PWRST_*
macros for the power states and logic settings,
- the function pwrdm_set_next_fpwrst, which controls
the power domains next power and logic settings, shall
be used instead of pwrdm_set_next_pwrst to program the
power domains next states,
- the function pwrdm_set_fpwrst, which programs the power
domains power and logic settings, shall be used instead
of omap_set_pwrdm_state.
Signed-off-by: Jean Pihet j-pi...@ti.com
[p...@pwsan.com: split the original patch into OMAP2/3/4 variants;
warn if sets fail; various other changes]
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/common.h |7 +--
arch/arm/mach-omap2/cpuidle44xx.c | 32 +
arch/arm/mach-omap2/omap-hotplug.c|2 -
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 69
+
arch/arm/mach-omap2/pm44xx.c | 42 +-
5 files changed, 79 insertions(+), 73 deletions(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index c57eeea..5ad846a 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -235,14 +235,13 @@ extern void omap5_secondary_startup(void);
#if defined(CONFIG_SMP) defined(CONFIG_PM)
extern int omap4_mpuss_init(void);
-extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+extern int omap4_mpuss_enter_lowpower(unsigned int cpu, u8 fpwrst);
extern int omap4_finish_suspend(unsigned long cpu_state);
extern void omap4_cpu_resume(void);
-extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
+extern int omap4_mpuss_hotplug_cpu(unsigned int cpu, u8 fpwrst);
extern u32 omap4_mpuss_read_prev_context_state(void);
#else
-static inline int omap4_enter_lowpower(unsigned int cpu,
- unsigned int power_state)
+static inline int omap4_mpuss_enter_lowpower(unsigned int cpu, u8 fpwrst)
{
cpu_do_idle();
return 0;
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
b/arch/arm/mach-omap2/cpuidle44xx.c
index d639aef..2cb5332 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -25,26 +25,22 @@
/* Machine specific information */
struct omap4_idle_statedata {
- u32 cpu_state;
- u32 mpu_logic_state;
- u32 mpu_state;
+ u8 cpu_pwrst;
+ u8 mpu_pwrst;
This should be cpu_fpwrst and mpu_fwprst for consistency.
};
static struct omap4_idle_statedata omap4_idle_data[] = {
{
- .cpu_state = PWRDM_POWER_ON,
- .mpu_state = PWRDM_POWER_ON,
- .mpu_logic_state = PWRDM_POWER_RET,
+ .cpu_pwrst = PWRDM_FUNC_PWRST_ON,
+ .mpu_pwrst = PWRDM_FUNC_PWRST_ON,
},
{
- .cpu_state = PWRDM_POWER_OFF,
- .mpu_state = PWRDM_POWER_RET,
- .mpu_logic_state = PWRDM_POWER_RET,
+ .cpu_pwrst = PWRDM_FUNC_PWRST_OFF,
+ .mpu_pwrst = PWRDM_FUNC_PWRST_CSWR,
},
{
- .cpu_state = PWRDM_POWER_OFF,
- .mpu_state = PWRDM_POWER_RET,
- .mpu_logic_state = PWRDM_POWER_OFF,
+ .cpu_pwrst = PWRDM_FUNC_PWRST_OFF,
+ .mpu_pwrst = PWRDM_FUNC_PWRST_OSWR,
},
};
@@ -93,7 +89,7 @@ static int omap4_enter_idle_coupled(struct cpuidle_device
*dev,
* out of coherency and in OFF mode.
*/
if (dev-cpu == 0 cpumask_test_cpu(1, cpu_online_mask)) {
- while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
+ while (pwrdm_read_fpwrst(cpu_pd[1]) != PWRDM_FUNC_PWRST_OFF) {
cpu_relax();
/*
@@ -118,19 +114,17 @@ static int omap4_enter_idle_coupled(struct
cpuidle_device *dev,
cpu_pm_enter();
if (dev-cpu == 0) {
- pwrdm_set_logic_retst(mpu_pd, cx-mpu_logic_state);
- omap_set_pwrdm_state(mpu_pd, cx-mpu_state);
+ WARN_ON(pwrdm_set_fpwrst(mpu_pd, cx-mpu_pwrst));
/*
* Call idle CPU cluster PM enter notifier chain
* to save GIC and wakeupgen context.
*/
- if ((cx-mpu_state == PWRDM_POWER_RET)
- (cx-mpu_logic_state == PWRDM_POWER_OFF))
- cpu_cluster_pm_enter();
+ if (cx-mpu_pwrst == PWRDM_FUNC_PWRST_OSWR)
+ cpu_cluster_pm_enter();
}
- omap4_enter_lowpower(dev-cpu, cx-cpu_state);
+ omap4_mpuss_enter_lowpower(dev-cpu, cx-cpu_pwrst);
cpu_done[dev
Re: [PATCH 07/12] ARM: OMAP2+: PM: use power domain functional state in stats counters
Paul,
On Sun, Dec 9, 2012 at 6:53 PM, Paul Walmsley p...@pwsan.com wrote:
From: Jean Pihet jean.pi...@newoldbits.com
The PM code uses some counters to keep track of the power domains
transitions, in order to provide the information to drivers (in
pwrdm_get_context_loss_count) and to expose the information to
sysfs for debug purpose.
This patch provides the information for each functional state.
Signed-off-by: Jean Pihet j-pi...@ti.com
[p...@pwsan.com: use PWRDM_FPWRSTS_COUNT due to functional power state offset;
use powerdomain.c fn to convert func pwrsts to names; rename 'state' to
'fpwrst' to indicate use of func pwrsts; convert remaining users of the
non-func pwrst API; add some kerneldoc]
Signed-off-by: Paul Walmsley p...@pwsan.com
The patch does more than the description is telling. The function
_update_logic_membank_counters is removed by this patch, is this
intentional?
---
arch/arm/mach-omap2/pm-debug.c| 42 -
arch/arm/mach-omap2/powerdomain.c | 167
++---
arch/arm/mach-omap2/powerdomain.h | 17 ++--
3 files changed, 108 insertions(+), 118 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 806a06b..72cf9e0 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -53,13 +53,6 @@ enum {
DEBUG_FILE_TIMERS,
};
-static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
- OFF,
- RET,
- INA,
- ON
-};
-
void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
{
s64 t;
@@ -70,7 +63,7 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
/* Update timer for previous state */
t = sched_clock();
- pwrdm-state_timer[prev] += t - pwrdm-timer;
+ pwrdm-fpwrst_timer[prev - PWRDM_FPWRST_OFFSET] += t - pwrdm-timer;
pwrdm-timer = t;
}
@@ -79,6 +72,7 @@ static int clkdm_dbg_show_counter(struct clockdomain
*clkdm, void *user)
{
struct seq_file *s = (struct seq_file *)user;
+ /* XXX This needs to be implemented in a better way */
if (strcmp(clkdm-name, emu_clkdm) == 0 ||
strcmp(clkdm-name, wkup_clkdm) == 0 ||
strncmp(clkdm-name, dpll, 4) == 0)
@@ -94,23 +88,26 @@ static int pwrdm_dbg_show_counter(struct powerdomain
*pwrdm, void *user)
{
struct seq_file *s = (struct seq_file *)user;
int i;
+ int curr_fpwrst;
if (strcmp(pwrdm-name, emu_pwrdm) == 0 ||
strcmp(pwrdm-name, wkup_pwrdm) == 0 ||
strncmp(pwrdm-name, dpll, 4) == 0)
return 0;
- if (pwrdm-state != pwrdm_read_pwrst(pwrdm))
- printk(KERN_ERR pwrdm state mismatch(%s) %d != %d\n,
- pwrdm-name, pwrdm-state, pwrdm_read_pwrst(pwrdm));
+ curr_fpwrst = pwrdm_read_fpwrst(pwrdm);
+ if (pwrdm-fpwrst != curr_fpwrst)
+ pr_err(pwrdm state mismatch(%s) %s != %s\n,
+ pwrdm-name,
+ pwrdm_convert_fpwrst_to_name(pwrdm-fpwrst),
+ pwrdm_convert_fpwrst_to_name(curr_fpwrst));
seq_printf(s, %s (%s), pwrdm-name,
- pwrdm_state_names[pwrdm-state]);
- for (i = 0; i PWRDM_MAX_PWRSTS; i++)
- seq_printf(s, ,%s:%d, pwrdm_state_names[i],
- pwrdm-state_counter[i]);
+ pwrdm_convert_fpwrst_to_name(pwrdm-fpwrst));
+ for (i = PWRDM_FPWRST_OFFSET; i PWRDM_MAX_FUNC_PWRSTS; i++)
+ seq_printf(s, ,%s:%d, pwrdm_convert_fpwrst_to_name(i),
+ pwrdm-fpwrst_counter[i - PWRDM_FPWRST_OFFSET]);
- seq_printf(s, ,RET-LOGIC-OFF:%d, pwrdm-ret_logic_off_counter);
for (i = 0; i pwrdm-banks; i++)
seq_printf(s, ,RET-MEMBANK%d-OFF:%d, i + 1,
pwrdm-ret_mem_off_counter[i]);
@@ -133,11 +130,12 @@ static int pwrdm_dbg_show_timer(struct powerdomain
*pwrdm, void *user)
pwrdm_state_switch(pwrdm);
seq_printf(s, %s (%s), pwrdm-name,
- pwrdm_state_names[pwrdm-state]);
+ pwrdm_convert_fpwrst_to_name(pwrdm-fpwrst));
- for (i = 0; i 4; i++)
- seq_printf(s, ,%s:%lld, pwrdm_state_names[i],
- pwrdm-state_timer[i]);
+ for (i = 0; i PWRDM_FPWRSTS_COUNT; i++)
+ seq_printf(s, ,%s:%lld,
+ pwrdm_convert_fpwrst_to_name(i +
PWRDM_FPWRST_OFFSET),
+ pwrdm-fpwrst_timer[i]);
seq_printf(s, \n);
return 0;
@@ -209,8 +207,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm,
void *dir)
t = sched_clock();
- for (i = 0; i 4; i++)
- pwrdm-state_timer[i] = 0;
+ for (i = 0; i PWRDM_FPWRSTS_COUNT; i++)
+ pwrdm-fpwrst_timer[i] = 0
Re: [PATCHv2] i2c: omap: Move the remove constraint
Hi Shubhrajyoti, On Thu, Nov 15, 2012 at 8:34 AM, Shubhrajyoti D shubhrajy...@ti.com wrote: Currently we just queue the transfer and release the qos constraints, however we donot wait for the transfer Typo: donot to complete to release the constraint. Move the remove constraint after the bus busy as we are sure that the transfers are completed by then. Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com Looks good! Acked-by: Jean Pihet j-pi...@ti.com Regards, Jean --- v2: rebase to the for-next branch drivers/i2c/busses/i2c-omap.c |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 482c63d..fabcbe1 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -654,13 +654,14 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) break; } - if (dev-set_mpu_wkup_lat != NULL) - dev-set_mpu_wkup_lat(dev-dev, -1); - if (r == 0) r = num; omap_i2c_wait_for_bb(dev); + + if (dev-set_mpu_wkup_lat != NULL) + dev-set_mpu_wkup_lat(dev-dev, -1); + out: pm_runtime_mark_last_busy(dev-dev); pm_runtime_put_autosuspend(dev-dev); -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2] i2c: omap: Move the remove constraint
On Thu, Nov 15, 2012 at 9:51 AM, Shubhrajyoti Datta omaplinuxker...@gmail.com wrote: On Thu, Nov 15, 2012 at 1:46 PM, Jean Pihet jean.pi...@newoldbits.com wrote: Hi Shubhrajyoti, On Thu, Nov 15, 2012 at 8:34 AM, Shubhrajyoti D shubhrajy...@ti.com wrote: Currently we just queue the transfer and release the qos constraints, however we donot wait for the transfer Typo: donot Just fixed and resent. to complete to release the constraint. Move the remove constraint after the bus busy as we are sure that the transfers are completed by then. Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com Looks good! Acked-by: Jean Pihet j-pi...@ti.com Thanks for review. Thanks! Regards, Jean Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: AM335x: Beaglebone stops to boot with current git kernel
Hi Tony, On Wed, Nov 14, 2012 at 6:51 PM, Tony Lindgren t...@atomide.com wrote: * Jean Pihet jean.pi...@newoldbits.com [121114 08:43]: The patch should change the name of the hwmod entry as well, can you fold this change in the current patch? This was caused by the merge of omap-for-v3.8/pm into omap-for-v3.8/clock. I noticed a smilar issue for omap3, but missed at least this one. Jean, can you please check omap-for-v3.8/clock for the smartreflex clock names in case there are more issues like this remaining? The hwmod clock names are OK for 3xxx, 36xx, 33xx and 44xx. The hwmod names are OK excepted for 33xx where they respectively should be smartreflex_mpu_iva and smartreflex_core. This issue is caused by 99e7938d ARM: OMAP3: clock: Add 3xxx data using common struct clk in omap-for-v3.8/clock. Regards, Tony Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Revert ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints
Hi Wolfram, On Wed, Nov 14, 2012 at 11:51 AM, Wolfram Sang w.s...@pengutronix.de wrote: On Tue, Nov 06, 2012 at 04:31:32PM +, Paul Walmsley wrote: This reverts commit 3db11feffc1ad2ab9dea27789e6b5b3032827adc. Here giving the patch name in parens would have really made sense. Will fix that. The title is ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints. This commit causes I2C timeouts to appear on several OMAP3430/3530-based boards: http://marc.info/?l=linux-arm-kernelm=135071372426971w=2 http://marc.info/?l=linux-arm-kernelm=135067558415214w=2 http://marc.info/?l=linux-arm-kernelm=135216013608196w=2 There is no formal piecof evidence that the commit is the cause of it. and appears to have been sent for merging before one of its prerequisites was merged: However this is correct. My fault ;-| http://marc.info/?l=linux-arm-kernelm=135219411617621w=2 Hmm, any ideas how to avoid such things in the future? The only way is to figure out the dependencies with other features. In this case I overlooked them and assumed some other features were already merged in. Will take care next time. Signed-off-by: Paul Walmsley p...@pwsan.com Applied to for-current, thanks! Thanks! Jean -- Pengutronix e.K. | Wolfram Sang| Industrial Linux Solutions | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] i2c: omap: Move the remove constraint
Hi Wolfram, Shubhrajyoti, On Wed, Nov 14, 2012 at 11:57 AM, Wolfram Sang w.s...@pengutronix.de wrote: Currently we just queue the transfer and release the qos constraints, however we donot wait for the transfer to complete to release the constraint. Move the remove constraint after the bus busy as we are sure that the transfers are completed by then. Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com Good catch, the change definitely makes sense. Feel free to add: Acked-by: Jean Pihet j-pi...@ti.com Since I just reverted the QoS patch, I suppose this gets merged into the original patch when resent? The best for now is to re-submit a new patch that moves the constraint release in the original code. Later the PM QoS patch will be applied on the new code base. What do you think? I can provide a patch if needed. Regards, Jean -- Pengutronix e.K. | Wolfram Sang| Industrial Linux Solutions | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: AM335x: Beaglebone stops to boot with current git kernel
Hi,
On Wed, Nov 14, 2012 at 4:28 PM, Igor Mazanov i.maza...@gmail.com wrote:
Hello,
Beaglebone boot process is broken with the current git kernel. I use
omap2plus_defconfig for tests.
It looks like the boot process stops due to the last changes in the AM33xx
clock sysbsystem. A following patch resolves this issue:
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index ad8d43b..858e180 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -586,7 +586,7 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
.class = am33xx_smartreflex_hwmod_class,
.clkdm_name = l4_wkup_clkdm,
.mpu_irqs = am33xx_smartreflex0_irqs,
- .main_clk = smartreflex0_fck,
+ .main_clk = smartreflex_mpu_fck,
.prcm = {
.omap4 = {
.clkctrl_offs =
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
@@ -606,7 +606,7 @@ static struct omap_hwmod am33xx_smartreflex1_hwmod = {
.class = am33xx_smartreflex_hwmod_class,
.clkdm_name = l4_wkup_clkdm,
.mpu_irqs = am33xx_smartreflex1_irqs,
- .main_clk = smartreflex1_fck,
+ .main_clk = smartreflex_core_fck,
.prcm = {
.omap4 = {
.clkctrl_offs =
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
About the name field in the hwmod entry: the SR code checks on the
value of smartreflex_mpu_iva to differentiate the SR IP blocks and
to apply the correct parameters to each of them. Cf. the function
sr_set_regfields in drivers/power/avs/smartreflex.c.
The patch should change the name of the hwmod entry as well, can you
fold this change in the current patch?
Note: I know the name smartreflex_mpu_iva is not perfect since it
does not apply to all OMAP3 variants, maybe we could change the SR
code to be more generic.
Nishant, what do you think?
Regards,
Jean
Regards,
Igor.
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Re: OMAP baseline test results for v3.7-rc1
Hi Kevin, Paul, On Tue, Nov 6, 2012 at 1:01 AM, Kevin Hilman khil...@deeprootsystems.com wrote: Jean Pihet jean.pi...@newoldbits.com writes: [...] I ran some intensive stress tests on the I2C and ... unfortunately I could not trigger the problem. It looks like the issue is caused by some transient situation where the CORE and/or I2C is in a low power state. FYI... I just ran across what appears to be the same bug on 3430/n900 during suspend/resume testing. With CPUidle enabled, this happens every time. Reverting the I2C QoS patch makes it work again. That makes sense with CPU_IDLE enabled and suspend. The cause of the problem is that the cpuidle influences the MPU and CORE states, depending on the constraints set and the latency figures for the power domains (in arch/arm/mach-omap2/cpuidle34xx.c). Since the latency numbers have not been updated to measured (i.e. realistic) values in too-low power state is used, hence the timeout problem. Note: that does not explain why the I2C timeout issue is present without CPU_IDLE enabled, since in that case PM QoS should not have any effect on the power domains states. So yes the PM QoS I2C patch shall be reverted as long as the PM QoS support for OMAP is not merged in. For the records here are the patches that have been submitted to support the OMAP PM QoS: - func power states [1], - OMAP PM QoS support [2], which includes the latency figures update and which depends on [1], - the conversion of I2C to PM QoS [3], - the removal of the old no-op OMAP PM API [4], which depends on [3], The chicken-and-egg problem is clearly visible since [3] depends on [2]. What to do now with those patches? As said above [3] and [4] must be held until [1] and [2] are merged in. [1] http://marc.info/?l=linux-arm-kernelm=134744383120921w=2 [2] http://marc.info/?l=linux-omapm=134795835604288w=2 [3] http://marc.info/?l=linux-omapm=134815730108344w=2 [4] http://marc.info/?l=linux-omapm=134795836904299w=2 Kevin Thanks for testing and reporting the issue. Jean # rtcwake -m mem -s 1 Date:Fri Dec 31 17:00:34 MST 1999 hwclock: Sat Jan 1 00:00:34 2000 0.00 seconds [ 38.819732] omap_i2c omap_i2c.1: timeout waiting for bus ready wakeup from mem at Sat Jan 1 00:00:36 2000 [ 38.841949] PM: Syncing filesystems ... done. [ 38.859466] Freezing user space processes ... (elapsed 0.01 seconds) done. [ 38.885284] Freezing remaining freezable tasks ... (elapsed 0.02 seconds) done. [ 38.916412] Suspending console(s) (use no_console_suspend to debug) [ 39.944274] omap_i2c omap_i2c.1: timeout waiting for bus ready [ 39.944305] twl: i2c_read failed to transfer all messages [ 39.944305] twl_rtc: Could not read TWLregister D - error -110 [ 39.944335] twl_rtc twl_rtc: twl_rtc_read_time: reading CTRL_REG, error -110 [ 40.975524] omap_i2c omap_i2c.1: timeout waiting for bus ready [ 40.97] twl: i2c_read failed to transfer all messages [ 40.97] VMMC2_IO_18: failed to disable [ 40.978698] PM: suspend of devices complete after 2049.163 msecs [ 40.984222] PM: late suspend of devices complete after 5.493 msecs [ 40.992126] PM: noirq suspend of devices complete after 7.873 msecs [ 40.992187] Disabling non-boot CPUs ... [ 40.992675] Successfully put all powerdomains to target state [ 40.997009] PM: noirq resume of devices complete after 4.058 msecs [ 41.002014] PM: early resume of devices complete after 3.601 msecs [ 41.179016] PM: resume of devices complete after 176.818 msecs [ 41.277740] Restarting tasks ... done. real0m 3.50s user0m 0.00s sys 0m 0.10s Date:Fri Dec 31 17:00:40 MST 1999 hwclock: Sat Jan 1 00:00:40 2000 0.00 seconds -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] i2c: omap: Move the remove constraint
Hi Shubhrajyoti, On Tue, Nov 6, 2012 at 10:54 AM, Shubhrajyoti D shubhrajy...@ti.com wrote: Currently we just queue the transfer and release the qos constraints, however we donot wait for the transfer to complete to release the constraint. Move the remove constraint after the bus busy as we are sure that the transfers are completed by then. Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com Good catch, the change definitely makes sense. Feel free to add: Acked-by: Jean Pihet j-pi...@ti.com Thanks, Jean. --- drivers/i2c/busses/i2c-omap.c |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 94ff685..8b079d7 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -655,13 +655,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) break; } - if (dev-latency) - pm_qos_remove_request(dev-pm_qos_request); - if (r == 0) r = num; omap_i2c_wait_for_bb(dev); + + if (dev-latency) + pm_qos_remove_request(dev-pm_qos_request); out: pm_runtime_mark_last_busy(dev-dev); pm_runtime_put_autosuspend(dev-dev); -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Revert ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints
On Tue, Nov 6, 2012 at 5:31 PM, Paul Walmsley p...@pwsan.com wrote:
This reverts commit 3db11feffc1ad2ab9dea27789e6b5b3032827adc.
This commit causes I2C timeouts to appear on several OMAP3430/3530-based
boards:
http://marc.info/?l=linux-arm-kernelm=135071372426971w=2
http://marc.info/?l=linux-arm-kernelm=135067558415214w=2
http://marc.info/?l=linux-arm-kernelm=135216013608196w=2
and appears to have been sent for merging before one of its prerequisites
was merged:
http://marc.info/?l=linux-arm-kernelm=135219411617621w=2
Indeed.
Acked-by: Jean Pihet j-pi...@ti.com
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Jean Pihet jean.pi...@newoldbits.com
Cc: Kevin Hilman khil...@ti.com
Cc: Aaro Koskinen aaro.koski...@iki.fi
Cc: Felipe Balbi ba...@ti.com
---
Intended for 3.7-rc.
arch/arm/plat-omap/i2c.c | 21 +
drivers/i2c/busses/i2c-omap.c | 32 ++--
include/linux/i2c-omap.h |1 +
3 files changed, 36 insertions(+), 18 deletions(-)
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5683a8..6013831 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,12 +26,14 @@
#include linux/kernel.h
#include linux/platform_device.h
#include linux/i2c.h
+#include linux/i2c-omap.h
#include linux/slab.h
#include linux/err.h
#include linux/clk.h
#include mach/irqs.h
#include plat/i2c.h
+#include plat/omap-pm.h
#include plat/omap_device.h
#define OMAP_I2C_SIZE 0x3f
@@ -127,6 +129,16 @@ static inline int omap1_i2c_add_bus(int bus_id)
#ifdef CONFIG_ARCH_OMAP2PLUS
+/*
+ * XXX This function is a temporary compatibility wrapper - only
+ * needed until the I2C driver can be converted to call
+ * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
+ */
+static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
+{
+ omap_pm_set_max_mpu_wakeup_lat(dev, t);
+}
+
static inline int omap2_i2c_add_bus(int bus_id)
{
int l;
@@ -158,6 +170,15 @@ static inline int omap2_i2c_add_bus(int bus_id)
dev_attr = (struct omap_i2c_dev_attr *)oh-dev_attr;
pdata-flags = dev_attr-flags;
+ /*
+* When waiting for completion of a i2c transfer, we need to
+* set a wake up latency constraint for the MPU. This is to
+* ensure quick enough wakeup from idle, when transfer
+* completes.
+* Only omap3 has support for constraints
+*/
+ if (cpu_is_omap34xx())
+ pdata-set_mpu_wkup_lat =
omap_pm_set_max_mpu_wakeup_lat_compat;
pdev = omap_device_build(name, bus_id, oh, pdata,
sizeof(struct omap_i2c_bus_platform_data),
NULL, 0, 0);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index db31eae..0b02543 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -43,7 +43,6 @@
#include linux/slab.h
#include linux/i2c-omap.h
#include linux/pm_runtime.h
-#include linux/pm_qos.h
/* I2C controller revisions */
#define OMAP_I2C_OMAP1_REV_2 0x20
@@ -187,8 +186,9 @@ struct omap_i2c_dev {
int reg_shift; /* bit shift for I2C register
addresses */
struct completion cmd_complete;
struct resource *ioarea;
- u32 latency;/* maximum MPU wkup latency */
- struct pm_qos_request pm_qos_request;
+ u32 latency;/* maximum mpu wkup latency */
+ void(*set_mpu_wkup_lat)(struct device *dev,
+ long latency);
u32 speed; /* Speed of bus in kHz */
u32 dtrev; /* extra revision from DT */
u32 flags;
@@ -494,7 +494,9 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev
*dev, u8 size, bool is_rx)
dev-b_hw = 1; /* Enable hardware fixes */
/* calculate wakeup latency constraint for MPU */
- dev-latency = (100 * dev-threshold) / (1000 * dev-speed / 8);
+ if (dev-set_mpu_wkup_lat != NULL)
+ dev-latency = (100 * dev-threshold) /
+ (1000 * dev-speed / 8);
}
/*
@@ -629,16 +631,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
if (r 0)
goto out;
- /*
-* When waiting for completion of a i2c transfer, we need to
-* set a wake up latency constraint for the MPU. This is to
-* ensure quick enough wakeup from idle, when transfer
-* completes.
-*/
- if (dev-latency)
- pm_qos_add_request(dev-pm_qos_request,
- PM_QOS_CPU_DMA_LATENCY
Re: OMAP baseline test results for v3.7-rc1
Paul, On Mon, Nov 5, 2012 at 4:15 AM, Paul Walmsley p...@pwsan.com wrote: Hi Jean, On Sat, 3 Nov 2012, Jean Pihet wrote: The setup is as identical as possible to yours: - U-Boot 2011.06-dirty (Sep 04 2012 - 17:06:58) from http://www.pwsan.com/tmp/3530es3beagle-MLO-u-boot-20121023.tar.bz2. Please note that the MLO image does not run on my board and so I had to use my known-to-work image. Interesting... The result is that I could reproduce the issue but it happens much more rarely on my side (only once vs quasi 100% on ~50 boot cycles). Hmm... The issue is triggered by running 'hwclock --systohc' while the system is heavily loaded (running depmod etc.). OK. More investigation on-going, so more to come! Great, keep us posted. I ran some intensive stress tests on the I2C and ... unfortunately I could not trigger the problem. It looks like the issue is caused by some transient situation where the CORE and/or I2C is in a low power state. Here are the tests that have been performed from the user space: - stress test the I2C IRQ handler by reading and writing the RTC, and checking the amount of IRQs for the I2C bus. In that case the CORE never goes in low power mode, - stress test the CORE low power and wake-up transition by adjusting the autosuspend delay (e.g. /sys/devices/platform/omap_i2c.1/power/autosuspend_delay_ms) and accessing the RTC after the CORE has gone in low power. Those tests have been run for hours (20 IRQs) and the I2C timeout issue could not be observed. The target low power mode is RET (not tried with OFF). The next step is to detect an error situation and have data logged about the state at that moment. What do you think? This brings an interesting discussion. As you indicated earlier, withtout CPU_IDLE enabled nothing except the autosuspend delay is preventing the power domains to go in low power mode. This could lead to situations where latency constraints are not respected. The easy and straight forward solution is to enable CPU_IDLE and use the PM QoS constraints. What do you think? Regards, Jean Will try to kick off those tests you requested within the next 24-48 hours. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 0/6] ARM: OMAP3+: move smartreflex-class3.c to drivers/power/avs
Hi Nishant, On Sat, Nov 3, 2012 at 2:14 PM, Kevin Hilman khil...@deeprootsystems.com wrote: Hi Nishanth, On 10/25/2012 09:21 AM, Jean Pihet wrote: Hi Nishant, On Tue, Oct 23, 2012 at 11:43 PM, Nishanth Menon n...@ti.com wrote: smartreflex.c now resides in drivers/power/avs directory, but class driver is in mach-omap2. High time we move it off to drivers/power/avs. Great to see the SR fully moved to drivers/. After review of the code I am OK with the changes besides remarks sent on the patches: Acked-by: Jean Pihet j-pi...@ti.com I let Kevin comment on the VC/VP aspect though. This move looks good to me. Thanks! Just had one nit, but after that. Feel free to post without the RFC, and be sure to include Rafael and linux-pm since it's moving to drivers/power. Please also include Anton, cf. http://marc.info/?l=linux-pmm=134424298230568w=2 Regards, Jean I'll then queue it up for Rafael for v3.8. Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.7-rc1
Hi Paul, On Thu, Nov 1, 2012 at 8:51 AM, Jean Pihet jean.pi...@newoldbits.com wrote: Hi Paul, On Wed, Oct 31, 2012 at 10:44 PM, Paul Walmsley p...@pwsan.com wrote: Hi On Wed, 31 Oct 2012, Jean Pihet wrote: Paul, Could you please check with the 2 calls to PM QoS from the I2C code commented out? This will rule out the PM QoS impact. Will be happy to do a test run for you, after the boot log from your local test run is posted: http://marc.info/?l=linux-arm-kernelm=135167153510814w=2 Here are some more details after investigation. The setup is as identical as possible to yours: - U-Boot 2011.06-dirty (Sep 04 2012 - 17:06:58) from http://www.pwsan.com/tmp/3530es3beagle-MLO-u-boot-20121023.tar.bz2. Please note that the MLO image does not run on my board and so I had to use my known-to-work image. - 3.7.0-rc1 kernel, omap2plus_defconfig, - same kernel parameters, - Angstrom rootfs from http://www.pwsan.com/tmp/20121023-beagleboard-angstrom-userspace.tar.bz2 The differences are: - OMAP revision (ES2.1 vs ES3.0), - Beagleboard revision (B5 vs Cx), - RAM amount (128 vs 256MB), - compiler: gcc version 4.5.1 (Sourcery G++ Lite 2010.09-50) vs 4.5.2 (Sourcery G++ Lite 2011.03-41) The result is that I could reproduce the issue but it happens much more rarely on my side (only once vs quasi 100% on ~50 boot cycles). The issue is triggered by running 'hwclock --systohc' while the system is heavily loaded (running depmod etc.). The system recovers nicely after the issue, the RTC can be used correctly later on. Here is the log: U-Boot 2011.06-dirty (Sep 04 2012 - 17:06:58) OMAP3530-GP ES2.1, CPU-OPP2, L3-165MHz, Max CPU Clock 600 mHz OMAP3 Beagle board + LPDDR/NAND I2C: ready DRAM: 128 MiB NAND: 256 MiB MMC: OMAP SD/MMC: 0 In:serial Out: serial Err: serial Beagle Rev Ax/Bx timed out in wait_for_pin: I2C_STAT=0 I2C read: I/O error Unrecognized expansion board: 0 Die ID #0f6204013ef109008009 Hit any key to stop autoboot: 0 reading uimage 4148008 bytes read ## Booting kernel from Legacy Image at 8030 ... Image Name: Linux-3.7.0-rc1 Image Type: ARM Linux Kernel Image (uncompressed) Data Size:4147944 Bytes = 4 MiB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. [0.00] Booting Linux on physical CPU 0 [0.00] Linux version 3.7.0-rc1 (def@rachael) (gcc version 4.5.2 (Sourcery G++ Lite 2011.03-41) ) #2 SMP Sat Nov 3 21:56:11 CET 2012 [0.00] CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), cr=10c53c7d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache [0.00] Machine: OMAP3 Beagle Board [0.00] Memory policy: ECC disabled, Data cache writeback [0.00] OMAP3430/3530 ES2.1 (l2cache iva sgx neon isp ) [0.00] Clocking rate (Crystal/Core/MPU): 26.0/332/500 MHz [0.00] PERCPU: Embedded 9 pages/cpu @c0e4 s12928 r8192 d15744 u36864 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256 [0.00] Kernel command line: console=ttyO2,230400n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait [0.00] PID hash table entries: 512 (order: -1, 2048 bytes) [0.00] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [0.00] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [0.00] Memory: 127MB = 127MB total [0.00] Memory: 115316k/115316k available, 15756k reserved, 0K highmem [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xfff0 - 0xfffe ( 896 kB) [0.00] vmalloc : 0xc880 - 0xff00 ( 872 MB) [0.00] lowmem : 0xc000 - 0xc800 ( 128 MB) [0.00] pkmap : 0xbfe0 - 0xc000 ( 2 MB) [0.00] modules : 0xbf00 - 0xbfe0 ( 14 MB) [0.00] .text : 0xc0008000 - 0xc07037dc (7150 kB) [0.00] .init : 0xc0704000 - 0xc0754280 ( 321 kB) [0.00] .data : 0xc0756000 - 0xc07e15a0 ( 558 kB) [0.00].bss : 0xc07e15c4 - 0xc0d3bfac (5483 kB) [0.00] Hierarchical RCU implementation. [0.00] RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1. [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] IRQ: Found an INTC at 0xfa20 (revision 4.0) with 96 interrupts [0.00] Total of 96 interrupts on 1 active controller [0.00] OMAP clockevent source: GPTIMER12 at 32768 Hz [0.00] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms [0.00] OMAP clocksource: 32k_counter at 32768 Hz [0.00] Console: colour dummy device 80x30 [0.00] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [0.00] ... MAX_LOCKDEP_SUBCLASSES: 8
Re: OMAP baseline test results for v3.7-rc1
Hi Paul, On Wed, Oct 31, 2012 at 10:44 PM, Paul Walmsley p...@pwsan.com wrote: Hi On Wed, 31 Oct 2012, Jean Pihet wrote: Paul, Could you please check with the 2 calls to PM QoS from the I2C code commented out? This will rule out the PM QoS impact. Will be happy to do a test run for you, after the boot log from your local test run is posted: http://marc.info/?l=linux-arm-kernelm=135167153510814w=2 As said earlier [1] the test has been done already. I did check the boot messages and tried to read/write the RTC. All test were successfull and the only difference in the logs was the absence of the I2C timeout messages. I can redo the tests and provide a log but that will not happen before Saturday. [1] http://marc.info/?l=linux-omapm=135161909714517w=2 Regards, Jean - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.7-rc1
Hi Paul, On Tue, Oct 30, 2012 at 7:23 AM, Paul Walmsley p...@pwsan.com wrote: Hi Jean, On Tue, 30 Oct 2012, Jean Pihet wrote: On Tue, Oct 30, 2012 at 5:16 AM, Paul Walmsley p...@pwsan.com wrote: On Tue, 23 Oct 2012, Jean Pihet wrote: Let me try with the same setup as yours (bootloader images, omap2pus_defconfig, angstrom roots). Had any luck reproducing this one that Aaro I are seeing? Unfortunately not. I could not reproduce the issue on my side, using an ES2.1 Beagleboard with the latest l-o kernel and your bootloader and rootfs images. Is there some specific to enable in order to reproduce the issue? Could you please post a bootlog from your terminal program, similar to http://www.pwsan.com/omap/testlogs/test_v3.7-rc3/20121028162003/boot/3530es3beagle/3530es3beagle_log.txt ? Yes sure. Let me try to reproduce the problem again. As said previously I cannot have the timeouts issue. More to come. Jean - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.7-rc1
On Tue, Oct 30, 2012 at 9:17 AM, Paul Walmsley p...@pwsan.com wrote: On Tue, 30 Oct 2012, Felipe Balbi wrote: On Tue, Oct 30, 2012 at 12:50:52PM +, Paul Walmsley wrote: certainly PM-idle related, given that the problem goes away by reverting Jean's commit 3db11feffc1ad2ab9dea27789e6b5b3032827adc ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints. The problem is consistent and easy to reproduce here. I don't doubt that :-) What I think, however, is that PM QoS just made I dont doubt either but cannot have it reproduced. the problem a bit easier to trigger for whatever reason. Maybe because pm qos defers constraint updates, or something similar ? PM QoS just influences the cpuidle decision on the next power state of the CPU and CORE power domains. Based on a very quick look, I'd say the original patch 3db11fe is broken. I don't see how it can ensure that its PM_QOS_CPU_DMA_LATENCY request is honored when CONFIG_CPU_IDLE=n. CONFIG_CPU_IDLE=n is the default for omap2plus_defconfig. Withtout CPU_IDLE set the PM QoS has no influence on the power domains states. - Paul Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.7-rc1
Paul, - Added Rafael for the PM QoS discussion - On Tue, Oct 30, 2012 at 10:04 AM, Paul Walmsley p...@pwsan.com wrote: On Tue, 30 Oct 2012, Paul Walmsley wrote: Based on a very quick look, I'd say the original patch 3db11fe is broken. I don't see how it can ensure that its PM_QOS_CPU_DMA_LATENCY request is honored when CONFIG_CPU_IDLE=n. CONFIG_CPU_IDLE=n is the default for omap2plus_defconfig. So in fact to follow up on this, looks like one of two changes are needed: 1. Revert 3db11fe or 2. If CONFIG_CPU_IDLE=n, the driver needs to call disable_hlt() in place of the pm_qos constraint add, and call enable_hlt() in place of the pm_qos constraint remove. I do not think this is correct. Using disable_hlt is a too radical solution and will prevent the idle completely, this is not what we want. Rafael, what do you think? Furthermore without the patch 3db11fe enable_hlt and disable_hlt are not used in the driver so this change is not the real fix for the issue. To me the cause is somewhere else. I was hoping Felipe's ordering fix would do it... Jean, could you please pick a solution and send a patch for the 3.7-rc timeframe, to fix the bug in 3db11fe? ? Let me try to reproduce the issue and hopefully investigate a bit more. Feel free to revert the patch if you feel like it is the thing to do. - Paul Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.7-rc1
Hi Kevin, On Wed, Oct 31, 2012 at 6:49 AM, Kevin Hilman khil...@deeprootsystems.com wrote: Hi Jean, Jean Pihet jean.pi...@newoldbits.com writes: [...] Based on a very quick look, I'd say the original patch 3db11fe is broken. I don't see how it can ensure that its PM_QOS_CPU_DMA_LATENCY request is honored when CONFIG_CPU_IDLE=n. CONFIG_CPU_IDLE=n is the default for omap2plus_defconfig. Withtout CPU_IDLE set the PM QoS has no influence on the power domains states. Exactly, which means there is *no* constraint set when CPUidle is disabled, Correct. With CPU_IDLE disabled PM QoS manages the constraints list but cpuidle does not request the aggregated value nor does it restrict the CPU and CORE power domains states. and it's exactly this that is different from the behavior before your patch. No. Before your patch, the constraint would be set whether or not CPUidle was enabled, correct? No. In the linux-omap source tree the OMAP PM API for the latency constraints simply is a no-op. The only difference with the code after the patch is that PM QoS manages the constraints list, which should be neglictable in terms of CPU execution time. Paul, Could you please check with the 2 calls to PM QoS from the I2C code commented out? This will rule out the PM QoS impact. The solution to this will probably be to make OMAPs non-CPUidle idle path check the constraints. This is the idea behind the per-device PM QoS support, which allows to set a constraint on any device and so on any power domain (note that cpuidle influences CPU and CORE only). However in the current context -the I2C timeouts issue- there is no apparent link between the issue and the patch 3db11fef [1]. [1] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=3db11feffc1ad2ab9dea27789e6b5b3032827adc Kevin Thanks, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.7-rc1
Hi Paul, On Tue, Oct 30, 2012 at 5:16 AM, Paul Walmsley p...@pwsan.com wrote: Hello Jean, On Tue, 23 Oct 2012, Jean Pihet wrote: Let me try with the same setup as yours (bootloader images, omap2pus_defconfig, angstrom roots). Had any luck reproducing this one that Aaro I are seeing? Unfortunately not. I could not reproduce the issue on my side, using an ES2.1 Beagleboard with the latest l-o kernel and your bootloader and rootfs images. Is there some specific to enable in order to reproduce the issue? Regards, Jean - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 0/6] ARM: OMAP3+: move smartreflex-class3.c to drivers/power/avs
Hi Nishant,
On Tue, Oct 23, 2012 at 11:43 PM, Nishanth Menon n...@ti.com wrote:
smartreflex.c now resides in drivers/power/avs directory, but class driver
is in mach-omap2. High time we move it off to drivers/power/avs.
Great to see the SR fully moved to drivers/.
After review of the code I am OK with the changes besides remarks sent
on the patches:
Acked-by: Jean Pihet j-pi...@ti.com
I let Kevin comment on the VC/VP aspect though.
This series *does not* try to fix VP/VC to be voltage regulator OR introduce
a new OMAP voltage regulator series. instead, it purely tries to do the
minimal
changes needed to move code to drivers/power/avs as a start.
Baseline: k.org v3.7-rc2
Testing: Platform: beagle XM C1 (3730)
while [ 1 ]
do
echo -n 0 /sys/kernel/debug/smartreflex/smartreflex_core/autocomp
date
echo -n 1 /sys/kernel/debug/smartreflex/smartreflex_core/autocomp
done
Screen capture after the series: on inductor L5 (VDD2 - core):
https://plus.google.com/photos/112464029509057661457/albums/5715034179943520193/5802619719180530114
RFC for a view if this is ok as an intermediate step.
Thanks!
Jean
Nishanth Menon (6):
PM / AVS / OMAP: move Kconfig definition of smartreflex to avs
directory
ARM: OMAP: voltage: remove duplicate header definitions
ARM: OMAP: voltage: move voltdm_reset to platform_data header
ARM: OMAP: SmartReflex: provide SoC integration API for VP
ARM: OMAP: SmartReflex: use pr_warn instead of pr_warning
PM / AVS / OMAP: move Smartreflex-class3 driver to power/avs
arch/arm/mach-omap2/Makefile |1 -
arch/arm/mach-omap2/sr_device.c|5
arch/arm/mach-omap2/voltage.h |4 ---
arch/arm/plat-omap/Kconfig | 31
drivers/power/avs/Kconfig | 31
drivers/power/avs/Makefile |1 +
.../power/avs}/smartreflex-class3.c| 20 +
drivers/power/avs/smartreflex.c|2 ++
include/linux/platform_data/voltage-omap.h |1 +
include/linux/power/smartreflex.h | 18
10 files changed, 73 insertions(+), 41 deletions(-)
rename {arch/arm/mach-omap2 = drivers/power/avs}/smartreflex-class3.c (75%)
Regards,
Nishanth Menon
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1.7.9.5
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Re: [RFC PATCH 4/6] ARM: OMAP: SmartReflex: provide SoC integration API for VP
Nishant,
On Tue, Oct 23, 2012 at 11:43 PM, Nishanth Menon n...@ti.com wrote:
SoC integration of SmartReflex AVS block is varied. Some use
Voltage Processor for a hardware loop in certain OMAP SoC (called
hardware loop), while others have just the AVS block without
hardware loop automatic calibration mechanism for AVS block
to talk through. So provide the Voltage Processor API
to allow for SmartReflex class drivers to use the same.
NOTE: SmartReflex class 3 mode of operation mandates VP APIs
so, refuse to enable AVS driver if corresponding APIs are
not available.
As part of this change, remove the inclusion of voltage.h
which is no longer needed as smartreflex.h includes
linux/platform_data/voltage-omap.h which contain relevant
definitions used here.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/smartreflex-class3.c | 16 +---
arch/arm/mach-omap2/sr_device.c |5 +
drivers/power/avs/smartreflex.c |2 ++
include/linux/power/smartreflex.h| 18 ++
4 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c
b/arch/arm/mach-omap2/smartreflex-class3.c
index 1da8f03..201e219 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -12,7 +12,6 @@
*/
#include linux/power/smartreflex.h
-#include voltage.h
static int sr_class3_enable(struct omap_sr *sr)
{
@@ -23,15 +22,26 @@ static int sr_class3_enable(struct omap_sr *sr)
__func__, sr-name);
return -ENODATA;
}
+ if (!sr-soc_ops.vp_enable) {
+ pr_warn(%s: no VP enable available.Cannot enable %s!!\n,
+ __func__, sr-name);
+ return -EINVAL;
+ }
- omap_vp_enable(sr-voltdm);
+ sr-soc_ops.vp_enable(sr-voltdm);
return sr_enable(sr-voltdm, volt);
}
static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
{
+ if (!sr-soc_ops.vp_enable) {
This should be ' if (!sr-soc_ops.vp_disbable) {'.
+ pr_warn(%s: no VP disable available.Cannot disable %s!!\n,
+ __func__, sr-name);
+ return -EINVAL;
+ }
sr_disable_errgen(sr-voltdm);
- omap_vp_disable(sr-voltdm);
+
+ sr-soc_ops.vp_disable(sr-voltdm);
sr_disable(sr-voltdm);
if (is_volt_reset)
voltdm_reset(sr-voltdm);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index f8217a5..6aac2c7 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -139,6 +139,11 @@ static int __init sr_dev_init(struct omap_hwmod *oh,
void *user)
sr_data-enable_on_init = sr_enable_on_init;
+ if (sr_data-voltdm-vp) {
+ sr_data-soc_ops.vp_enable = omap_vp_enable;
+ sr_data-soc_ops.vp_disable = omap_vp_disable;
+ }
+
pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
NULL, 0, 0);
if (IS_ERR(pdev))
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 24768a2..32a9e3e 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -920,6 +920,8 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-pdev = pdev;
sr_info-srid = pdev-id;
sr_info-voltdm = pdata-voltdm;
+ sr_info-soc_ops.vp_enable = pdata-soc_ops.vp_enable;
+ sr_info-soc_ops.vp_disable = pdata-soc_ops.vp_disable;
sr_info-nvalue_table = pdata-nvalue_table;
sr_info-nvalue_count = pdata-nvalue_count;
sr_info-senn_mod = pdata-senn_mod;
diff --git a/include/linux/power/smartreflex.h
b/include/linux/power/smartreflex.h
index 4a496eb..203fc64 100644
--- a/include/linux/power/smartreflex.h
+++ b/include/linux/power/smartreflex.h
@@ -143,6 +143,21 @@
#define OMAP3430_SR_ERRWEIGHT 0x04
#define OMAP3430_SR_ERRMAXLIMIT0x02
+/**
+ * struct omap_sr_soc_ops - SoC specific APIs
+ * @vp_enable: Voltage Processor enable
+ * @vp_disable:Voltage Processor disable
+ *
+ * SmartReflex AVS module integration tends to be SoC
+ * variant. some are integrated with modules like
+ * Voltage Processor (VP), while, some SoC integration
+ * donot use VP. Provide that variance here.
+ */
+struct omap_sr_soc_ops {
+ void (*vp_enable)(struct voltagedomain *voltdm);
+ void (*vp_disable)(struct voltagedomain *voltdm);
+};
+
struct omap_sr {
char*name;
struct list_headnode;
@@ -165,6 +180,7 @@ struct omap_sr {
u32 senp_mod;
u32 senn_mod;
void __iomem*base;
+
Re: OMAP baseline test results for v3.7-rc1
On Tue, Oct 23, 2012 at 9:19 PM, Paul Walmsley p...@pwsan.com wrote: On Mon, 22 Oct 2012, Jean Pihet wrote: On Mon, Oct 22, 2012 at 6:12 PM, Jean Pihet jean.pi...@newoldbits.com wrote: Do you have CPU_IDLE enabled? FYI the issue is not present with CPU_IDLE enabled. Hmm, how can you tell? I thought you weren't able to reproduce it with CPU_IDLE disabled either? I could not reproduce the issue, with and without CPU_IDLE enabled. What puzzles me is that the PM QoS code only has influence on the states chosen by cpuidle, so the change should not have any impact with CPU_IDLE enabled. I reallt need to reproduce the issue. Let me try with the same setup as yours (bootloader images, omap2pus_defconfig, angstrom roots). Regards, Jean - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.7-rc1
Hi, On Sat, Oct 20, 2012 at 8:14 AM, Paul Walmsley p...@pwsan.com wrote: Hi Jean On Fri, 19 Oct 2012, Paul Walmsley wrote: On Thu, 18 Oct 2012, Paul Walmsley wrote: Here are some basic OMAP test results for Linux v3.7-rc1. Logs and other details at http://www.pwsan.com/omap/testlogs/test_v3.7-rc1/ ... Failing tests: needing investigation Boot tests: * 3530ES3 Beagle: I2C timeouts during userspace init - May be related to the threaded IRQ conversion of the I2C driver - Unknown cause This one turned out to be caused by: commit 3db11feffc1ad2ab9dea27789e6b5b3032827adc Author: Jean Pihet jean.pi...@newoldbits.com Date: Thu Sep 20 18:08:03 2012 +0200 ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints Reverting this commit causes the problem to go away, but since the OMAP PM constraint code was removed as well, it's unlikely that a simple revert is the right thing to do. Jean could you please investigate and fix this? I tried the latest l-o with omap2plus defconfig on my Beagleboard B5 (ES2.1) and could not reproduce the problem. I do not have the I2C error messages at boot, nor at user space start up. I tried to read/write the TWL RTC, successfully. Another difference is the bootloader images. I have the following: - Texas Instruments X-Loader 1.4.2 (Feb 3 2009 - 15:34:17) - U-Boot 2009.01-dirty (Feb 19 2009 - 12:22:31) Could you send your bootloader images? I noticed you have I2C error messages in U-Boot, could that be the cause of the I2C lock-up? On the PM QoS side the commit 3db11fef moves the I2C code from the OMAP PM no-op layer to the PM QoS for CPU and DMA latency, which influences the cpuidle states. However CPU_IDLE is not set in omap2plus_defconfig so there should not be any effect. Do you have CPU_IDLE enabled? - Paul Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.7-rc1
On Mon, Oct 22, 2012 at 6:12 PM, Jean Pihet jean.pi...@newoldbits.com wrote: Hi, On Sat, Oct 20, 2012 at 8:14 AM, Paul Walmsley p...@pwsan.com wrote: Hi Jean On Fri, 19 Oct 2012, Paul Walmsley wrote: On Thu, 18 Oct 2012, Paul Walmsley wrote: Here are some basic OMAP test results for Linux v3.7-rc1. Logs and other details at http://www.pwsan.com/omap/testlogs/test_v3.7-rc1/ ... Failing tests: needing investigation Boot tests: * 3530ES3 Beagle: I2C timeouts during userspace init - May be related to the threaded IRQ conversion of the I2C driver - Unknown cause This one turned out to be caused by: commit 3db11feffc1ad2ab9dea27789e6b5b3032827adc Author: Jean Pihet jean.pi...@newoldbits.com Date: Thu Sep 20 18:08:03 2012 +0200 ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints Reverting this commit causes the problem to go away, but since the OMAP PM constraint code was removed as well, it's unlikely that a simple revert is the right thing to do. Jean could you please investigate and fix this? I tried the latest l-o with omap2plus defconfig on my Beagleboard B5 (ES2.1) and could not reproduce the problem. I do not have the I2C error messages at boot, nor at user space start up. I tried to read/write the TWL RTC, successfully. Another difference is the bootloader images. I have the following: - Texas Instruments X-Loader 1.4.2 (Feb 3 2009 - 15:34:17) - U-Boot 2009.01-dirty (Feb 19 2009 - 12:22:31) Could you send your bootloader images? I noticed you have I2C error messages in U-Boot, could that be the cause of the I2C lock-up? On the PM QoS side the commit 3db11fef moves the I2C code from the OMAP PM no-op layer to the PM QoS for CPU and DMA latency, which influences the cpuidle states. However CPU_IDLE is not set in omap2plus_defconfig so there should not be any effect. Do you have CPU_IDLE enabled? FYI the issue is not present with CPU_IDLE enabled. Regards, Jean - Paul Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints
On Sat, Oct 6, 2012 at 1:46 PM, Wolfram Sang w.s...@pengutronix.de wrote: On Thu, Sep 20, 2012 at 06:08:03PM +0200, Jean Pihet wrote: Convert the driver from the outdated omap_pm_set_max_mpu_wakeup_lat API to the new PM QoS API. Since the constraint is on the MPU subsystem, use the PM_QOS_CPU_DMA_LATENCY class of PM QoS. The resulting MPU constraints are used by cpuidle to decide the next power state of the MPU subsystem. The I2C device latency timing is derived from the FIFO size and the clock speed and so is applicable to all OMAP SoCs. Signed-off-by: Jean Pihet j-pi...@ti.com Applied to -next, thanks! Thanks! Jean -- Pengutronix e.K. | Wolfram Sang| Industrial Linux Solutions | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
On Fri, Oct 5, 2012 at 1:40 AM, Kevin Hilman khil...@deeprootsystems.com wrote: jean.pi...@newoldbits.com writes: From: Jean Pihet j-pi...@ti.com Remove the device dependent code (ex. cpu_is_xxx()) and settings from the driver code and instead pass them via the platform data. This allows a clean separation of the driver code and the platform code, as required by the move of the platform header files to include/linux/platform_data. Note about the smartreflex functional clocks: the smartreflex fclks are derived from sys_clk and have the same name as the main_clk from the hwmod entry, in order for the SmartReflex driver to request the fclk (using clk_get(dev, fck)). Based on mainline 3.6.0. Boot tested on OMAP34 platforms. Thanks, queuing this version for v3.8 (branch: for_3.8/pm/sr) Thanks! Jean Kevin P.S. in the future, It helps reviewers and maintainers if there's some versioning in the patches (e.g. PATCH v3 0/2]), especially when updated versions come in quick succession. Thanks. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
From: Jean Pihet j-pi...@ti.com Remove the device dependent code (ex. cpu_is_xxx()) and settings from the driver code and instead pass them via the platform data. This allows a clean separation of the driver code and the platform code, as required by the move of the platform header files to include/linux/platform_data. Note about the smartreflex functional clocks: the smartreflex fclks are derived from sys_clk and have the same name as the main_clk from the hwmod entry, in order for the SmartReflex driver to request the fclk (using clk_get(dev, fck)). Based on mainline 3.6.0. Boot tested on OMAP34 platforms. Jean Pihet (2): ARM: OMAP: hwmod: align the SmartReflex fck names ARM: OMAP: SmartReflex: pass device dependent data via platform data arch/arm/mach-omap2/clock33xx_data.c | 12 +++ arch/arm/mach-omap2/clock3xxx_data.c | 12 +++ arch/arm/mach-omap2/clock44xx_data.c |6 ++-- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |8 ++--- arch/arm/mach-omap2/sr_device.c| 13 +++ drivers/power/avs/smartreflex.c| 54 +--- include/linux/power/smartreflex.h | 14 ++-- 7 files changed, 61 insertions(+), 58 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: OMAP: hwmod: align the SmartReflex fck names
From: Jean Pihet j-pi...@ti.com
Rename the smartreflex fck names for consistency and better readability;
rename the clock aliases so that they match the hwmod main_clk names.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/clock33xx_data.c | 12 ++--
arch/arm/mach-omap2/clock3xxx_data.c | 12 ++--
arch/arm/mach-omap2/clock44xx_data.c |6 +++---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |8
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index 2026311..4fa2dd9 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -548,16 +548,16 @@ static struct clk mcasp1_fck = {
.recalc = followparent_recalc,
};
-static struct clk smartreflex0_fck = {
- .name = smartreflex0_fck,
+static struct clk smartreflex_mpu_fck = {
+ .name = smartreflex_mpu_fck,
.clkdm_name = l4_wkup_clkdm,
.parent = sys_clkin_ck,
.ops= clkops_null,
.recalc = followparent_recalc,
};
-static struct clk smartreflex1_fck = {
- .name = smartreflex1_fck,
+static struct clk smartreflex_core_fck = {
+ .name = smartreflex_core_fck,
.clkdm_name = l4_wkup_clkdm,
.parent = sys_clkin_ck,
.ops= clkops_null,
@@ -1036,8 +1036,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(davinci-mcasp.1, NULL, mcasp1_fck,CK_AM33XX),
CLK(NULL, mmc2_fck, mmc2_fck, CK_AM33XX),
CLK(NULL, mmu_fck, mmu_fck, CK_AM33XX),
- CLK(NULL, smartreflex0_fck, smartreflex0_fck,
CK_AM33XX),
- CLK(NULL, smartreflex1_fck, smartreflex1_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex_mpu_fck, smartreflex_mpu_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex_core_fck, smartreflex_core_fck,
CK_AM33XX),
CLK(NULL, timer1_fck, timer1_fck,CK_AM33XX),
CLK(NULL, timer2_fck, timer2_fck,CK_AM33XX),
CLK(NULL, timer3_fck, timer3_fck,CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index 700317a..81f6a15 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3050,8 +3050,8 @@ static struct clk traceclk_fck = {
/* SR clocks */
/* SmartReflex fclk (VDD1) */
-static struct clk sr1_fck = {
- .name = sr1_fck,
+static struct clk smartreflex_mpu_iva_fck = {
+ .name = smartreflex_mpu_iva_fck,
.ops= clkops_omap2_dflt_wait,
.parent = sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3061,8 +3061,8 @@ static struct clk sr1_fck = {
};
/* SmartReflex fclk (VDD2) */
-static struct clk sr2_fck = {
- .name = sr2_fck,
+static struct clk smartreflex_core_fck = {
+ .name = smartreflex_core_fck,
.ops= clkops_omap2_dflt_wait,
.parent = sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3448,8 +3448,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, atclk_fck,atclk_fck, CK_3XXX),
CLK(NULL, traceclk_src_fck, traceclk_src_fck, CK_3XXX),
CLK(NULL, traceclk_fck, traceclk_fck, CK_3XXX),
- CLK(NULL, sr1_fck, sr1_fck, CK_34XX | CK_36XX),
- CLK(NULL, sr2_fck, sr2_fck, CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex_mpu_iva_fck,
smartreflex_mpu_iva_fck, CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex_core_fck, smartreflex_core_fck, CK_34XX
| CK_36XX),
CLK(NULL, sr_l4_ick,sr_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, secure_32k_fck, secure_32k_fck, CK_3XXX),
CLK(NULL, gpt12_fck,gpt12_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index 500682c..9852ecb 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3224,9 +3224,9 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, slimbus2_fclk_0, slimbus2_fclk_0,
CK_443X),
CLK(NULL, slimbus2_slimbus_clk, slimbus2_slimbus_clk,
CK_443X),
CLK(NULL, slimbus2_fck, slimbus2_fck,
CK_443X),
- CLK(NULL, smartreflex_core_fck, smartreflex_core_fck,
CK_443X),
- CLK(NULL, smartreflex_iva_fck, smartreflex_iva_fck,
CK_443X),
- CLK(NULL, smartreflex_mpu_fck, smartreflex_mpu_fck,
CK_443X),
+ CLK(NULL, smartreflex_core_fck, smartreflex_core_fck,
CK_443X
[PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
From: Jean Pihet j-pi...@ti.com
Remove the device dependent code (ex. cpu_is_xxx()) and settings
from the driver code and instead pass them via the platform
data. This allows a clean separation of the driver code and the platform
code, as required by the move of the platform header files to
include/linux/platform_data.
Note about the smartreflex functional clocks: the smartreflex fclks
are derived from sys_clk and have the same name as the main_clk from
the hwmod entry, in order for the SmartReflex driver to request the
fclk (using clk_get(dev, fck)).
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/sr_device.c | 13 +
drivers/power/avs/smartreflex.c | 54 -
include/linux/power/smartreflex.h | 14 --
3 files changed, 42 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index cbeae56..06de443 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -121,6 +121,19 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void
*user)
sr_data-senn_mod = 0x1;
sr_data-senp_mod = 0x1;
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ sr_data-err_weight = OMAP3430_SR_ERRWEIGHT;
+ sr_data-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+ sr_data-accum_data = OMAP3430_SR_ACCUMDATA;
+ if (!(strcmp(sr_data-name, smartreflex_mpu))) {
+ sr_data-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+ } else {
+ sr_data-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+ }
+ }
+
sr_data-voltdm = voltdm_lookup(sr_dev_attr-sensor_voltdm_name);
if (IS_ERR(sr_data-voltdm)) {
pr_err(%s: Unable to get voltage domain pointer for VDD %s\n,
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 24768a2..4c4519e 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -130,24 +130,21 @@ static irqreturn_t sr_interrupt(int irq, void *data)
static void sr_set_clk_length(struct omap_sr *sr)
{
- struct clk *sys_ck;
- u32 sys_clk_speed;
+ struct clk *fck;
+ u32 fclk_speed;
- if (cpu_is_omap34xx())
- sys_ck = clk_get(NULL, sys_ck);
- else
- sys_ck = clk_get(NULL, sys_clkin_ck);
+ fck = clk_get(sr-pdev-dev, fck);
- if (IS_ERR(sys_ck)) {
- dev_err(sr-pdev-dev, %s: unable to get sys clk\n,
- __func__);
+ if (IS_ERR(fck)) {
+ dev_err(sr-pdev-dev, %s: unable to get fck for device %s\n,
+ __func__, dev_name(sr-pdev-dev));
return;
}
- sys_clk_speed = clk_get_rate(sys_ck);
- clk_put(sys_ck);
+ fclk_speed = clk_get_rate(fck);
+ clk_put(fck);
- switch (sys_clk_speed) {
+ switch (fclk_speed) {
case 1200:
sr-clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
break;
@@ -164,34 +161,12 @@ static void sr_set_clk_length(struct omap_sr *sr)
sr-clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
break;
default:
- dev_err(sr-pdev-dev, %s: Invalid sysclk value: %d\n,
- __func__, sys_clk_speed);
+ dev_err(sr-pdev-dev, %s: Invalid fclk rate: %d\n,
+ __func__, fclk_speed);
break;
}
}
-static void sr_set_regfields(struct omap_sr *sr)
-{
- /*
-* For time being these values are defined in smartreflex.h
-* and populated during init. May be they can be moved to board
-* file or pmic specific data structure. In that case these structure
-* fields will have to be populated using the pdata or pmic structure.
-*/
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- sr-err_weight = OMAP3430_SR_ERRWEIGHT;
- sr-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
- sr-accum_data = OMAP3430_SR_ACCUMDATA;
- if (!(strcmp(sr-name, smartreflex_mpu_iva))) {
- sr-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
- } else {
- sr-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
- }
- }
-}
-
static void sr_start_vddautocomp(struct omap_sr *sr)
{
if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
@@ -924,8 +899,14 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-nvalue_count = pdata-nvalue_count
Re: [PATCH 1/2] ARM: OMAP: hwmod: align the SmartReflex fck names
Hi Kevin,
On Thu, Oct 4, 2012 at 2:33 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Tony Lindgren t...@atomide.com writes:
* jean.pi...@newoldbits.com jean.pi...@newoldbits.com [121003 08:48]:
@@ -1036,8 +1036,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(davinci-mcasp.1, NULL, mcasp1_fck,CK_AM33XX),
CLK(NULL, mmc2_fck, mmc2_fck, CK_AM33XX),
CLK(NULL, mmu_fck, mmu_fck, CK_AM33XX),
-CLK(NULL, smartreflex0_fck, smartreflex0_fck,
CK_AM33XX),
-CLK(NULL, smartreflex1_fck, smartreflex1_fck,
CK_AM33XX),
+CLK(NULL, smartreflex.0,smartreflex_mpu_fck,
CK_AM33XX),
+CLK(NULL, smartreflex.1,smartreflex_core_fck,
CK_AM33XX),
CLK(NULL, timer1_fck, timer1_fck,CK_AM33XX),
CLK(NULL, timer2_fck, timer2_fck,CK_AM33XX),
CLK(NULL, timer3_fck, timer3_fck,CK_AM33XX),
I think this should be something like this instead:
CLK(smartreflex.0,fck, smartreflex_mpu_fck, CK_AM33XX),
CLK(smartreflex.1,fck, smartreflex_core_fck, CK_AM33XX),
Where the first one is the dev name, the second one is the
alias you want to use in the client driver?
Actually, the omap_device creation will create this kind of alias for
you, with the device name populated etc, so adding device names here
isn't necessary.
For omap_devices where drivers are always using clk_get(dev, ...),
the name in the initial clkdev table here really doesn't matter.
However, for core code that needs to do a clk_get(NULL, name), then
this name matters. In chatting with Paul offline, he mentioned part of
the CCF conversion will be using clk_get(NULL, ...) on the main_clk
listed in each hwmod. For that reason, it's important that this string
match the name in the hwmod.
That makes it clear. Thanks for looking at it!
I belive the patch below should make this compatible with any future
use.
Sure. The driver uses clk_get(dev, fck) to request the fcuntional
clock of the device.
Jean, can you fold this into $SUBJECT patch?
Sure!
I just re-sent a new version of the 2 patches.
Thanks,
Kevin
Thanks,
Jean
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index 6de3dc7..8a16504 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1034,8 +1034,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(davinci-mcasp.1, NULL, mcasp1_fck,CK_AM33XX),
CLK(NULL, mmc2_fck, mmc2_fck, CK_AM33XX),
CLK(NULL, mmu_fck, mmu_fck, CK_AM33XX),
- CLK(NULL, smartreflex.0,smartreflex_mpu_fck,
CK_AM33XX),
- CLK(NULL, smartreflex.1,smartreflex_core_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex_mpu_fck, smartreflex_mpu_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex_core_fck, smartreflex_core_fck,
CK_AM33XX),
CLK(NULL, timer1_fck, timer1_fck,CK_AM33XX),
CLK(NULL, timer2_fck, timer2_fck,CK_AM33XX),
CLK(NULL, timer3_fck, timer3_fck,CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index a197cf2..191d261 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3447,8 +3447,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, atclk_fck,atclk_fck, CK_3XXX),
CLK(NULL, traceclk_src_fck, traceclk_src_fck, CK_3XXX),
CLK(NULL, traceclk_fck, traceclk_fck, CK_3XXX),
- CLK(NULL, smartreflex.0,smartreflex_mpu_iva_fck,
CK_34XX | CK_36XX),
- CLK(NULL, smartreflex.1,smartreflex_core_fck,
CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex_mpu_iva_fck, smartreflex_mpu_iva_fck,
CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex_core_fck, smartreflex_core_fck,
CK_34XX | CK_36XX),
CLK(NULL, sr_l4_ick,sr_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, secure_32k_fck, secure_32k_fck, CK_3XXX),
CLK(NULL, gpt12_fck,gpt12_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index 9cc1112..19e0c1e 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3224,8 +3224,8 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, slimbus2_fclk_0, slimbus2_fclk_0,
CK_443X),
CLK(NULL, slimbus2_slimbus_clk,
slimbus2_slimbus_clk, CK_443X),
CLK(NULL, slimbus2_fck, slimbus2_fck,
CK_443X),
- CLK(NULL, smartreflex.0,
Re: [PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
Hi Kevin,
On Wed, Oct 3, 2012 at 12:21 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Hi Jean,
Jean Pihet jean.pi...@newoldbits.com writes:
Remove the device dependent settings (cpu_is_xxx(), IP fck etc.)
from the driver code and pass them instead via the platform
data.
This allows a clean separation of the driver code and the platform
code, as required by the move of the platform header files to
include/linux/platform_data.
Signed-off-by: Jean Pihet j-pi...@ti.com
Could you make pdata change and the clock change should be two different
patches? Also, your previous patch to align SR clock names should be
combined with the changes made here.
Some comments on the clock change below...
---
arch/arm/mach-omap2/sr_device.c | 13
drivers/power/avs/smartreflex.c | 40
++--
include/linux/power/smartreflex.h | 14 +++-
3 files changed, 36 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-omap2/sr_device.c
b/arch/arm/mach-omap2/sr_device.c
index d033a65..2885a77 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -122,6 +122,19 @@ static int __init sr_dev_init(struct omap_hwmod *oh,
void *user)
sr_data-senn_mod = 0x1;
sr_data-senp_mod = 0x1;
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ sr_data-err_weight = OMAP3430_SR_ERRWEIGHT;
+ sr_data-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+ sr_data-accum_data = OMAP3430_SR_ACCUMDATA;
+ if (!(strcmp(sr_data-name, smartreflex_mpu))) {
+ sr_data-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+ } else {
+ sr_data-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+ }
+ }
+
sr_data-voltdm = voltdm_lookup(sr_dev_attr-sensor_voltdm_name);
if (IS_ERR(sr_data-voltdm)) {
pr_err(%s: Unable to get voltage domain pointer for VDD %s\n,
diff --git a/drivers/power/avs/smartreflex.c
b/drivers/power/avs/smartreflex.c
index 92f6728..7c03c90 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -128,17 +128,16 @@ static irqreturn_t sr_interrupt(int irq, void *data)
static void sr_set_clk_length(struct omap_sr *sr)
{
+ char fck_name[16]; /* smartreflex.0 fits in 16 chars */
struct clk *sys_ck;
u32 sys_clk_speed;
- if (cpu_is_omap34xx())
- sys_ck = clk_get(NULL, sys_ck);
- else
- sys_ck = clk_get(NULL, sys_clkin_ck);
+ sprintf(fck_name, smartreflex.%d, sr-srid);
hmm, isn't this the same as dev_name(sr-pdev.dev) ?
Yes. Atfer the previous patch ARM: OMAP: hwmod: align the SmartReflex
fck names there is a direct mapping between the device name and the
IP functional clock. Note: the mapping is based on the order of the
hwmod entries and so it is important not to move them around.
Combined with your earlier patch to align clock names, this should just
be:
sys_ck = clk_get(sr-pdev.dev, fck);
Great! That works great and the code is much more elegant.
Also note that you've changed this from sys_clk to the SR functional
clock, which seems to be the same clock on 34xx and 44xx, but that change
should be clearly documented in the changelog.
Ok.
Updated patch in a bit.
Kevin
Thanks for reviewing,
Jean
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[PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
From: Jean Pihet j-pi...@ti.com
Remove the device dependent code (ex. cpu_is_xxx()) and settings
from the driver code and instead pass them via the platform
data. This allows a clean separation of the driver code and the platform
code, as required by the move of the platform header files to
include/linux/platform_data.
Note about the smartreflex functional clocks: the smartreflex fclks
are derived from sys_clk and are named smartreflex.%d. Since the
smartreflex device names and the functional clock names are identical
the device driver code uses them to control the functional clocks.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/sr_device.c | 13 +
drivers/power/avs/smartreflex.c | 38 +
include/linux/power/smartreflex.h | 14 --
3 files changed, 34 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index cbeae56..06de443 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -121,6 +121,19 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void
*user)
sr_data-senn_mod = 0x1;
sr_data-senp_mod = 0x1;
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ sr_data-err_weight = OMAP3430_SR_ERRWEIGHT;
+ sr_data-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+ sr_data-accum_data = OMAP3430_SR_ACCUMDATA;
+ if (!(strcmp(sr_data-name, smartreflex_mpu))) {
+ sr_data-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+ } else {
+ sr_data-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+ }
+ }
+
sr_data-voltdm = voltdm_lookup(sr_dev_attr-sensor_voltdm_name);
if (IS_ERR(sr_data-voltdm)) {
pr_err(%s: Unable to get voltage domain pointer for VDD %s\n,
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 24768a2..829467f 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -133,14 +133,11 @@ static void sr_set_clk_length(struct omap_sr *sr)
struct clk *sys_ck;
u32 sys_clk_speed;
- if (cpu_is_omap34xx())
- sys_ck = clk_get(NULL, sys_ck);
- else
- sys_ck = clk_get(NULL, sys_clkin_ck);
+ sys_ck = clk_get(sr-pdev-dev, fck);
if (IS_ERR(sys_ck)) {
- dev_err(sr-pdev-dev, %s: unable to get sys clk\n,
- __func__);
+ dev_err(sr-pdev-dev, %s: unable to get smartreflex fck
%s\n,
+ __func__, dev_name(sr-pdev-dev));
return;
}
@@ -170,28 +167,6 @@ static void sr_set_clk_length(struct omap_sr *sr)
}
}
-static void sr_set_regfields(struct omap_sr *sr)
-{
- /*
-* For time being these values are defined in smartreflex.h
-* and populated during init. May be they can be moved to board
-* file or pmic specific data structure. In that case these structure
-* fields will have to be populated using the pdata or pmic structure.
-*/
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- sr-err_weight = OMAP3430_SR_ERRWEIGHT;
- sr-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
- sr-accum_data = OMAP3430_SR_ACCUMDATA;
- if (!(strcmp(sr-name, smartreflex_mpu_iva))) {
- sr-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
- } else {
- sr-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
- }
- }
-}
-
static void sr_start_vddautocomp(struct omap_sr *sr)
{
if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
@@ -924,8 +899,14 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-nvalue_count = pdata-nvalue_count;
sr_info-senn_mod = pdata-senn_mod;
sr_info-senp_mod = pdata-senp_mod;
+ sr_info-err_weight = pdata-err_weight;
+ sr_info-err_maxlimit = pdata-err_maxlimit;
+ sr_info-accum_data = pdata-accum_data;
+ sr_info-senn_avgweight = pdata-senn_avgweight;
+ sr_info-senp_avgweight = pdata-senp_avgweight;
sr_info-autocomp_active = false;
sr_info-ip_type = pdata-ip_type;
+
sr_info-base = ioremap(mem-start, resource_size(mem));
if (!sr_info-base) {
dev_err(pdev-dev, %s: ioremap fail\n, __func__);
@@ -937,7 +918,6 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-irq = irq-start;
sr_set_clk_length(sr_info
[PATCH 0/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
From: Jean Pihet j-pi...@ti.com Remove the device dependent code (ex. cpu_is_xxx()) and settings from the driver code and instead pass them via the platform data. This allows a clean separation of the driver code and the platform code, as required by the move of the platform header files to include/linux/platform_data. Note about the smartreflex functional clocks: the smartreflex fclks are derived from sys_clk and are renamed smartreflex.%d. Since the smartreflex device names and the functional clock names are identical the device driver code uses them to control the functional clocks. Based on mainline 3.6.0. Boot tested on OMAP34 platforms. Jean Pihet (2): ARM: OMAP: hwmod: align the SmartReflex fck names ARM: OMAP: SmartReflex: pass device dependent data via platform data arch/arm/mach-omap2/clock33xx_data.c | 12 +++ arch/arm/mach-omap2/clock3xxx_data.c | 12 +++ arch/arm/mach-omap2/clock44xx_data.c |6 ++-- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |8 ++--- arch/arm/mach-omap2/sr_device.c| 13 +++ drivers/power/avs/smartreflex.c| 54 +--- include/linux/power/smartreflex.h | 14 ++-- 7 files changed, 61 insertions(+), 58 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: OMAP: hwmod: align the SmartReflex fck names
From: Jean Pihet j-pi...@ti.com
Rename the smartreflex fck names for consistency and better readability;
rename the clock aliases for use by the SmartReflex driver, with the
smartreflex.%d format.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/clock33xx_data.c | 12 ++--
arch/arm/mach-omap2/clock3xxx_data.c | 12 ++--
arch/arm/mach-omap2/clock44xx_data.c |6 +++---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |8
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index 2026311..851fc54 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -548,16 +548,16 @@ static struct clk mcasp1_fck = {
.recalc = followparent_recalc,
};
-static struct clk smartreflex0_fck = {
- .name = smartreflex0_fck,
+static struct clk smartreflex_mpu_fck = {
+ .name = smartreflex_mpu_fck,
.clkdm_name = l4_wkup_clkdm,
.parent = sys_clkin_ck,
.ops= clkops_null,
.recalc = followparent_recalc,
};
-static struct clk smartreflex1_fck = {
- .name = smartreflex1_fck,
+static struct clk smartreflex_core_fck = {
+ .name = smartreflex_core_fck,
.clkdm_name = l4_wkup_clkdm,
.parent = sys_clkin_ck,
.ops= clkops_null,
@@ -1036,8 +1036,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(davinci-mcasp.1, NULL, mcasp1_fck,CK_AM33XX),
CLK(NULL, mmc2_fck, mmc2_fck, CK_AM33XX),
CLK(NULL, mmu_fck, mmu_fck, CK_AM33XX),
- CLK(NULL, smartreflex0_fck, smartreflex0_fck,
CK_AM33XX),
- CLK(NULL, smartreflex1_fck, smartreflex1_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex.0,smartreflex_mpu_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex.1,smartreflex_core_fck,
CK_AM33XX),
CLK(NULL, timer1_fck, timer1_fck,CK_AM33XX),
CLK(NULL, timer2_fck, timer2_fck,CK_AM33XX),
CLK(NULL, timer3_fck, timer3_fck,CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index 700317a..796a1dc 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3050,8 +3050,8 @@ static struct clk traceclk_fck = {
/* SR clocks */
/* SmartReflex fclk (VDD1) */
-static struct clk sr1_fck = {
- .name = sr1_fck,
+static struct clk smartreflex_mpu_iva_fck = {
+ .name = smartreflex_mpu_iva_fck,
.ops= clkops_omap2_dflt_wait,
.parent = sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3061,8 +3061,8 @@ static struct clk sr1_fck = {
};
/* SmartReflex fclk (VDD2) */
-static struct clk sr2_fck = {
- .name = sr2_fck,
+static struct clk smartreflex_core_fck = {
+ .name = smartreflex_core_fck,
.ops= clkops_omap2_dflt_wait,
.parent = sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3448,8 +3448,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, atclk_fck,atclk_fck, CK_3XXX),
CLK(NULL, traceclk_src_fck, traceclk_src_fck, CK_3XXX),
CLK(NULL, traceclk_fck, traceclk_fck, CK_3XXX),
- CLK(NULL, sr1_fck, sr1_fck, CK_34XX | CK_36XX),
- CLK(NULL, sr2_fck, sr2_fck, CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex.0,smartreflex_mpu_iva_fck,
CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex.1,smartreflex_core_fck, CK_34XX
| CK_36XX),
CLK(NULL, sr_l4_ick,sr_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, secure_32k_fck, secure_32k_fck, CK_3XXX),
CLK(NULL, gpt12_fck,gpt12_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index 500682c..b9b988a 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3224,9 +3224,9 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, slimbus2_fclk_0, slimbus2_fclk_0,
CK_443X),
CLK(NULL, slimbus2_slimbus_clk, slimbus2_slimbus_clk,
CK_443X),
CLK(NULL, slimbus2_fck, slimbus2_fck,
CK_443X),
- CLK(NULL, smartreflex_core_fck, smartreflex_core_fck,
CK_443X),
- CLK(NULL, smartreflex_iva_fck, smartreflex_iva_fck,
CK_443X),
- CLK(NULL, smartreflex_mpu_fck, smartreflex_mpu_fck,
CK_443X),
+ CLK(NULL, smartreflex.0
[PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
From: Jean Pihet j-pi...@ti.com
Remove the device dependent code (ex. cpu_is_xxx()) and settings
from the driver code and instead pass them via the platform
data. This allows a clean separation of the driver code and the platform
code, as required by the move of the platform header files to
include/linux/platform_data.
Note about the smartreflex functional clocks: the smartreflex fclks
are derived from sys_clk and are named smartreflex.%d. Since the
smartreflex device names and the functional clock names are identical
the device driver code uses them to control the functional clocks.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/sr_device.c | 13 +
drivers/power/avs/smartreflex.c | 54 -
include/linux/power/smartreflex.h | 14 --
3 files changed, 42 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index cbeae56..06de443 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -121,6 +121,19 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void
*user)
sr_data-senn_mod = 0x1;
sr_data-senp_mod = 0x1;
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ sr_data-err_weight = OMAP3430_SR_ERRWEIGHT;
+ sr_data-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+ sr_data-accum_data = OMAP3430_SR_ACCUMDATA;
+ if (!(strcmp(sr_data-name, smartreflex_mpu))) {
+ sr_data-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+ } else {
+ sr_data-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+ }
+ }
+
sr_data-voltdm = voltdm_lookup(sr_dev_attr-sensor_voltdm_name);
if (IS_ERR(sr_data-voltdm)) {
pr_err(%s: Unable to get voltage domain pointer for VDD %s\n,
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 24768a2..c983e85 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -130,24 +130,21 @@ static irqreturn_t sr_interrupt(int irq, void *data)
static void sr_set_clk_length(struct omap_sr *sr)
{
- struct clk *sys_ck;
- u32 sys_clk_speed;
+ struct clk *fck;
+ u32 fclk_speed;
- if (cpu_is_omap34xx())
- sys_ck = clk_get(NULL, sys_ck);
- else
- sys_ck = clk_get(NULL, sys_clkin_ck);
+ fck = clk_get(sr-pdev-dev, fck);
- if (IS_ERR(sys_ck)) {
- dev_err(sr-pdev-dev, %s: unable to get sys clk\n,
- __func__);
+ if (IS_ERR(fck)) {
+ dev_err(sr-pdev-dev, %s: unable to get smartreflex fck
%s\n,
+ __func__, dev_name(sr-pdev-dev));
return;
}
- sys_clk_speed = clk_get_rate(sys_ck);
- clk_put(sys_ck);
+ fclk_speed = clk_get_rate(fck);
+ clk_put(fck);
- switch (sys_clk_speed) {
+ switch (fclk_speed) {
case 1200:
sr-clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
break;
@@ -164,34 +161,12 @@ static void sr_set_clk_length(struct omap_sr *sr)
sr-clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
break;
default:
- dev_err(sr-pdev-dev, %s: Invalid sysclk value: %d\n,
- __func__, sys_clk_speed);
+ dev_err(sr-pdev-dev, %s: Invalid fclk rate: %d\n,
+ __func__, fclk_speed);
break;
}
}
-static void sr_set_regfields(struct omap_sr *sr)
-{
- /*
-* For time being these values are defined in smartreflex.h
-* and populated during init. May be they can be moved to board
-* file or pmic specific data structure. In that case these structure
-* fields will have to be populated using the pdata or pmic structure.
-*/
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- sr-err_weight = OMAP3430_SR_ERRWEIGHT;
- sr-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
- sr-accum_data = OMAP3430_SR_ACCUMDATA;
- if (!(strcmp(sr-name, smartreflex_mpu_iva))) {
- sr-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
- } else {
- sr-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
- }
- }
-}
-
static void sr_start_vddautocomp(struct omap_sr *sr)
{
if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
@@ -924,8 +899,14 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info
Re: [PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
Kevin, On Wed, Oct 3, 2012 at 4:29 PM, Kevin Hilman khil...@deeprootsystems.com wrote: jean.pi...@newoldbits.com writes: From: Jean Pihet j-pi...@ti.com Remove the device dependent code (ex. cpu_is_xxx()) and settings from the driver code and instead pass them via the platform data. This allows a clean separation of the driver code and the platform code, as required by the move of the platform header files to include/linux/platform_data. Note about the smartreflex functional clocks: the smartreflex fclks are derived from sys_clk and are named smartreflex.%d. Since the smartreflex device names and the functional clock names are identical the device driver code uses them to control the functional clocks. Thanks for adding this part. One more nit below, then please resend this patch as a combined series with the align fclk names patch. Just re-sent the new series. (note: The previous patch 1 from this series I've queued separately as a fix for v3.7-rc. ) Thanks! The new series is based on mainline 3.6.0 with this patch applied. ... diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c index 24768a2..829467f 100644 --- a/drivers/power/avs/smartreflex.c +++ b/drivers/power/avs/smartreflex.c @@ -133,14 +133,11 @@ static void sr_set_clk_length(struct omap_sr *sr) struct clk *sys_ck; u32 sys_clk_speed; - if (cpu_is_omap34xx()) - sys_ck = clk_get(NULL, sys_ck); - else - sys_ck = clk_get(NULL, sys_clkin_ck); + sys_ck = clk_get(sr-pdev-dev, fck); nit: since this isn't the sys_clk anymore, could you s/sys_ck/fck/ ? Done! Thanks, Kevin Thanks, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: OMAP: hwmod: align the SmartReflex fck names
Hi Tony,
On Wed, Oct 3, 2012 at 7:00 PM, Tony Lindgren t...@atomide.com wrote:
* jean.pi...@newoldbits.com jean.pi...@newoldbits.com [121003 08:48]:
@@ -1036,8 +1036,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(davinci-mcasp.1, NULL, mcasp1_fck,CK_AM33XX),
CLK(NULL, mmc2_fck, mmc2_fck, CK_AM33XX),
CLK(NULL, mmu_fck, mmu_fck, CK_AM33XX),
- CLK(NULL, smartreflex0_fck, smartreflex0_fck,
CK_AM33XX),
- CLK(NULL, smartreflex1_fck, smartreflex1_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex.0,smartreflex_mpu_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex.1,smartreflex_core_fck,
CK_AM33XX),
CLK(NULL, timer1_fck, timer1_fck,CK_AM33XX),
CLK(NULL, timer2_fck, timer2_fck,CK_AM33XX),
CLK(NULL, timer3_fck, timer3_fck,CK_AM33XX),
I think this should be something like this instead:
CLK(smartreflex.0,fck, smartreflex_mpu_fck, CK_AM33XX),
CLK(smartreflex.1,fck, smartreflex_core_fck, CK_AM33XX),
Where the first one is the dev name, the second one is the
alias you want to use in the client driver?
Ok, thanks for the suggestion.
It works however I get a ' smartreflex.0: alias fck already exists'
warning at boot, coming from _add_hwmod_clocks_clkdev (called from
omap_device_alloc).
Since an fck is implicitly added for every device (in
_add_hwmod_clocks_clkdev) I replaced fck in the alias definition by
NULL but the warning is still present.
What do you think? /me dives into the omap_device code for details...
Regards,
Tony
Thanks,
Jean
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Re: [PATCH] ARM: OMAP2+: SmartReflex: fix return value check in sr_dev_init()
Hello,
On Thu, Sep 27, 2012 at 7:54 AM, Wei Yongjun weiyj...@gmail.com wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
In case of error, the function voltdm_lookup() returns NULL
not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.
dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
arch/arm/mach-omap2/sr_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d033a65..c248b30 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -123,7 +123,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void
*user)
sr_data-senp_mod = 0x1;
sr_data-voltdm = voltdm_lookup(sr_dev_attr-sensor_voltdm_name);
- if (IS_ERR(sr_data-voltdm)) {
+ if (!sr_data-voltdm) {
pr_err(%s: Unable to get voltage domain pointer for VDD
%s\n,
__func__, sr_dev_attr-sensor_voltdm_name);
goto exit;
This looks good, so here is the ack:
Acked-by: Jean Pihet j-pi...@ti.com
Thanks,
Jean
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Re: [PATCH] ARM: OMAP2+: PM: fix return value check in omap2_set_init_voltage()
On Thu, Sep 27, 2012 at 7:54 AM, Wei Yongjun weiyj...@gmail.com wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
In case of error, the function voltdm_lookup() returns NULL
not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.
dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
arch/arm/mach-omap2/pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5ced..ab15e5c 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -176,7 +176,7 @@ static int __init omap2_set_init_voltage(char *vdd_name,
char *clk_name,
}
voltdm = voltdm_lookup(vdd_name);
- if (IS_ERR(voltdm)) {
+ if (!voltdm) {
pr_err(%s: unable to get vdd pointer for vdd_%s\n,
__func__, vdd_name);
goto exit;
This looks good, so here is the ack:
Acked-by: Jean Pihet j-pi...@ti.com
Thanks,
Jean
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Re: [PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
Hi Tony, On Fri, Sep 21, 2012 at 9:07 PM, Tony Lindgren t...@atomide.com wrote: * Jean Pihet jean.pi...@newoldbits.com [120920 23:31]: On Fri, Sep 21, 2012 at 12:15 AM, Tony Lindgren t...@atomide.com wrote: You should be able to make this even simpler and not have to pass the clock name around at all. Just do: syc_ck = clk_get(NULL, fck); ... The problem is that the system has multiple instances of the smartreflex module, each having its own fck. On OMAP3/4 the fck's are derived from sys_clk via muxes and latches. The proposed code uses the fck's as defined in the .main_clk field of the hwmod entries, so that it takes the muxes and latches into account and also has a consistent clock naming. If the same system has multiple clocks, then you could have them matched by the smartreflex driver instance number. Or if you mean different source clocks for various omaps, then you just need to set multiple aliases for those clocks. In the driver, and add the necessary entries to the clock alias table. That way it's up to the SoC to set up the necessary clocks and the driver stays generic. Got it. The only solution would be to use an unique fck for all smartreflex modules in all configurations. Is that acceptable? Hmm maybe I don't follow you, but sounds like you just need to use the driver instance like we do for timers: $ grep omap_timer arch/arm/mach-omap2/clock*data*.c arch/arm/mach-omap2/clock44xx_data.c: CLK(omap_timer.1, timer_sys_ck, sys_clkin_ck, CK_443X), arch/arm/mach-omap2/clock44xx_data.c: CLK(omap_timer.2, timer_sys_ck, sys_clkin_ck, CK_443X), arch/arm/mach-omap2/clock44xx_data.c: CLK(omap_timer.3, timer_sys_ck, sys_clkin_ck, CK_443X), ... Ok. I have a new version that implements this, re-submitting in a bit. If you need multiple clocks for a driver instance, then they typically are just fck and ick. Regards, Tony Thanks, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
Remove the device dependent settings (cpu_is_xxx(), IP fck etc.) from the driver code and pass them instead via the platform data. This allows a clean separation of the driver code and the platform code, as required by the move of the platform header files to include/linux/platform_data. The patch also includes a fix of the error handling path in omap_sr_probe to correctly de-allocate resources in case of problems. $SUBJECT requires this change. Jean Pihet (2): ARM: OMAP: SmartReflex: fix error path in init function ARM: OMAP: SmartReflex: pass device dependent data via platform data arch/arm/mach-omap2/sr_device.c | 13 ++ drivers/power/avs/smartreflex.c | 48 +++- include/linux/power/smartreflex.h | 14 +- 3 files changed, 40 insertions(+), 35 deletions(-) -- 1.7.7.6 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: OMAP: SmartReflex: fix error path in init function
Fix the error handling path in omap_sr_probe to correctly
de-allocate resources in case of problems.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
drivers/power/avs/smartreflex.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 44efc6e..92f6728 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -928,7 +928,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
if (!sr_info-base) {
dev_err(pdev-dev, %s: ioremap fail\n, __func__);
ret = -ENOMEM;
- goto err_release_region;
+ goto err_free_name;
}
if (irq)
@@ -967,7 +967,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
dev_err(pdev-dev, %s: Unable to create debugfs directory\n,
__func__);
ret = PTR_ERR(sr_info-dbg_dir);
- goto err_free_name;
+ goto err_debugfs;
}
(void) debugfs_create_file(autocomp, S_IRUGO | S_IWUSR,
@@ -1011,11 +1011,11 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
err_debugfs:
debugfs_remove_recursive(sr_info-dbg_dir);
-err_free_name:
- kfree(sr_info-name);
err_iounmap:
list_del(sr_info-node);
iounmap(sr_info-base);
+err_free_name:
+ kfree(sr_info-name);
err_release_region:
release_mem_region(mem-start, resource_size(mem));
err_free_devinfo:
--
1.7.7.6
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[PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
Remove the device dependent settings (cpu_is_xxx(), IP fck etc.)
from the driver code and pass them instead via the platform
data.
This allows a clean separation of the driver code and the platform
code, as required by the move of the platform header files to
include/linux/platform_data.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/sr_device.c | 13
drivers/power/avs/smartreflex.c | 40 ++--
include/linux/power/smartreflex.h | 14 +++-
3 files changed, 36 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d033a65..2885a77 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -122,6 +122,19 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void
*user)
sr_data-senn_mod = 0x1;
sr_data-senp_mod = 0x1;
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ sr_data-err_weight = OMAP3430_SR_ERRWEIGHT;
+ sr_data-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+ sr_data-accum_data = OMAP3430_SR_ACCUMDATA;
+ if (!(strcmp(sr_data-name, smartreflex_mpu))) {
+ sr_data-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+ } else {
+ sr_data-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+ }
+ }
+
sr_data-voltdm = voltdm_lookup(sr_dev_attr-sensor_voltdm_name);
if (IS_ERR(sr_data-voltdm)) {
pr_err(%s: Unable to get voltage domain pointer for VDD %s\n,
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 92f6728..7c03c90 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -128,17 +128,16 @@ static irqreturn_t sr_interrupt(int irq, void *data)
static void sr_set_clk_length(struct omap_sr *sr)
{
+ char fck_name[16]; /* smartreflex.0 fits in 16 chars */
struct clk *sys_ck;
u32 sys_clk_speed;
- if (cpu_is_omap34xx())
- sys_ck = clk_get(NULL, sys_ck);
- else
- sys_ck = clk_get(NULL, sys_clkin_ck);
+ sprintf(fck_name, smartreflex.%d, sr-srid);
+ sys_ck = clk_get(NULL, fck_name);
if (IS_ERR(sys_ck)) {
- dev_err(sr-pdev-dev, %s: unable to get sys clk\n,
- __func__);
+ dev_err(sr-pdev-dev, %s: unable to get smartreflex fck
%s\n,
+ __func__, fck_name);
return;
}
@@ -168,28 +167,6 @@ static void sr_set_clk_length(struct omap_sr *sr)
}
}
-static void sr_set_regfields(struct omap_sr *sr)
-{
- /*
-* For time being these values are defined in smartreflex.h
-* and populated during init. May be they can be moved to board
-* file or pmic specific data structure. In that case these structure
-* fields will have to be populated using the pdata or pmic structure.
-*/
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- sr-err_weight = OMAP3430_SR_ERRWEIGHT;
- sr-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
- sr-accum_data = OMAP3430_SR_ACCUMDATA;
- if (!(strcmp(sr-name, smartreflex_mpu_iva))) {
- sr-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
- } else {
- sr-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
- }
- }
-}
-
static void sr_start_vddautocomp(struct omap_sr *sr)
{
if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
@@ -922,8 +899,14 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-nvalue_count = pdata-nvalue_count;
sr_info-senn_mod = pdata-senn_mod;
sr_info-senp_mod = pdata-senp_mod;
+ sr_info-err_weight = pdata-err_weight;
+ sr_info-err_maxlimit = pdata-err_maxlimit;
+ sr_info-accum_data = pdata-accum_data;
+ sr_info-senn_avgweight = pdata-senn_avgweight;
+ sr_info-senp_avgweight = pdata-senp_avgweight;
sr_info-autocomp_active = false;
sr_info-ip_type = pdata-ip_type;
+
sr_info-base = ioremap(mem-start, resource_size(mem));
if (!sr_info-base) {
dev_err(pdev-dev, %s: ioremap fail\n, __func__);
@@ -935,7 +918,6 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-irq = irq-start;
sr_set_clk_length(sr_info);
- sr_set_regfields(sr_info);
list_add(sr_info-node, sr_list);
diff --git a/include/linux/power/smartreflex.h
b/include/linux/power
Re: [PATCH] ARM: OMAP: hwmod: align the SmartReflex fck names
Hi Paul, Kevin, On Thu, Sep 20, 2012 at 11:48 AM, Jean Pihet jean.pi...@newoldbits.com wrote: Rename the smartreflex fck names: - for consistency and better readability, - for use by the SmartReflex driver, through the hwmod .main_clk field. Signed-off-by: Jean Pihet j-pi...@ti.com Please discard this version. I have a new version ready after Tony's comments on the SmartReflex patches [1] [1] http://marc.info/?l=linux-omapm=134825443710207w=2 Re-submitting in a bit. --- arch/arm/mach-omap2/clock3xxx_data.c | 12 ++-- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |8 2 files changed, 10 insertions(+), 10 deletions(-) Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP: hwmod: align the SmartReflex fck names
Rename the smartreflex fck names for consistency and better readability;
rename the clock aliases for use by the SmartReflex driver, with the
smartreflex.%d format.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/clock33xx_data.c | 12 ++--
arch/arm/mach-omap2/clock3xxx_data.c | 12 ++--
arch/arm/mach-omap2/clock44xx_data.c |6 +++---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |8
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-omap2/clock33xx_data.c
b/arch/arm/mach-omap2/clock33xx_data.c
index 25bbcc7..a328f12 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -548,16 +548,16 @@ static struct clk mcasp1_fck = {
.recalc = followparent_recalc,
};
-static struct clk smartreflex0_fck = {
- .name = smartreflex0_fck,
+static struct clk smartreflex_mpu_fck = {
+ .name = smartreflex_mpu_fck,
.clkdm_name = l4_wkup_clkdm,
.parent = sys_clkin_ck,
.ops= clkops_null,
.recalc = followparent_recalc,
};
-static struct clk smartreflex1_fck = {
- .name = smartreflex1_fck,
+static struct clk smartreflex_core_fck = {
+ .name = smartreflex_core_fck,
.clkdm_name = l4_wkup_clkdm,
.parent = sys_clkin_ck,
.ops= clkops_null,
@@ -1034,8 +1034,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(davinci-mcasp.1, NULL, mcasp1_fck,CK_AM33XX),
CLK(NULL, mmc2_fck, mmc2_fck, CK_AM33XX),
CLK(NULL, mmu_fck, mmu_fck, CK_AM33XX),
- CLK(NULL, smartreflex0_fck, smartreflex0_fck,
CK_AM33XX),
- CLK(NULL, smartreflex1_fck, smartreflex1_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex.0,smartreflex_mpu_fck,
CK_AM33XX),
+ CLK(NULL, smartreflex.1,smartreflex_core_fck,
CK_AM33XX),
CLK(NULL, gpt1_fck, timer1_fck,CK_AM33XX),
CLK(NULL, gpt2_fck, timer2_fck,CK_AM33XX),
CLK(NULL, gpt3_fck, timer3_fck,CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index 83bed9a..a197cf2 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3050,8 +3050,8 @@ static struct clk traceclk_fck = {
/* SR clocks */
/* SmartReflex fclk (VDD1) */
-static struct clk sr1_fck = {
- .name = sr1_fck,
+static struct clk smartreflex_mpu_iva_fck = {
+ .name = smartreflex_mpu_iva_fck,
.ops= clkops_omap2_dflt_wait,
.parent = sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3061,8 +3061,8 @@ static struct clk sr1_fck = {
};
/* SmartReflex fclk (VDD2) */
-static struct clk sr2_fck = {
- .name = sr2_fck,
+static struct clk smartreflex_core_fck = {
+ .name = smartreflex_core_fck,
.ops= clkops_omap2_dflt_wait,
.parent = sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3447,8 +3447,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, atclk_fck,atclk_fck, CK_3XXX),
CLK(NULL, traceclk_src_fck, traceclk_src_fck, CK_3XXX),
CLK(NULL, traceclk_fck, traceclk_fck, CK_3XXX),
- CLK(NULL, sr1_fck, sr1_fck, CK_34XX | CK_36XX),
- CLK(NULL, sr2_fck, sr2_fck, CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex.0,smartreflex_mpu_iva_fck,
CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex.1,smartreflex_core_fck, CK_34XX
| CK_36XX),
CLK(NULL, sr_l4_ick,sr_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, secure_32k_fck, secure_32k_fck, CK_3XXX),
CLK(NULL, gpt12_fck,gpt12_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index d7f55e4..9cc1112 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3224,9 +3224,9 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, slimbus2_fclk_0, slimbus2_fclk_0,
CK_443X),
CLK(NULL, slimbus2_slimbus_clk, slimbus2_slimbus_clk,
CK_443X),
CLK(NULL, slimbus2_fck, slimbus2_fck,
CK_443X),
- CLK(NULL, smartreflex_core_fck, smartreflex_core_fck,
CK_443X),
- CLK(NULL, smartreflex_iva_fck, smartreflex_iva_fck,
CK_443X),
- CLK(NULL, smartreflex_mpu_fck, smartreflex_mpu_fck,
CK_443X),
+ CLK(NULL, smartreflex.0,smartreflex_core_fck,
CK_443X
Re: [PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
Hi Tony,
On Fri, Sep 21, 2012 at 12:15 AM, Tony Lindgren t...@atomide.com wrote:
Hi,
* Jean Pihet jean.pi...@newoldbits.com [120920 07:48]:
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -131,14 +131,11 @@ static void sr_set_clk_length(struct omap_sr *sr)
struct clk *sys_ck;
u32 sys_clk_speed;
- if (cpu_is_omap34xx())
- sys_ck = clk_get(NULL, sys_ck);
- else
- sys_ck = clk_get(NULL, sys_clkin_ck);
+ sys_ck = clk_get(NULL, sr-fck_name);
if (IS_ERR(sys_ck)) {
- dev_err(sr-pdev-dev, %s: unable to get sys clk\n,
- __func__);
+ dev_err(sr-pdev-dev, %s: unable to get smartreflex fck
%s\n,
+ __func__, sr-fck_name);
return;
}
You should be able to make this even simpler and not have to pass
the clock name around at all. Just do:
syc_ck = clk_get(NULL, fck);
...
The problem is that the system has multiple instances of the
smartreflex module, each having its own fck. On OMAP3/4 the fck's are
derived from sys_clk via muxes and latches.
The proposed code uses the fck's as defined in the .main_clk field of
the hwmod entries, so that it takes the muxes and latches into account
and also has a consistent clock naming.
In the driver, and add the necessary entries to the clock alias
table. That way it's up to the SoC to set up the necessary clocks
and the driver stays generic.
Got it. The only solution would be to use an unique fck for all
smartreflex modules in all configurations. Is that acceptable?
@@ -1049,6 +1039,7 @@ static int __devexit omap_sr_remove(struct
platform_device *pdev)
list_del(sr_info-node);
iounmap(sr_info-base);
+ kfree(sr_info-fck_name);
kfree(sr_info-name);
kfree(sr_info);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Then there's no need for the kfree of the fck_name
either.
There's an example of a similar patch done for twl-core.c as commit
defa6be1 (mfd: Fix compile for twl-core.c by removing cpu_is_omap usage)
in current linux next, except with smartreflex you probably don't
need to do any of the platform_device_alloc trickery like twl-core.c
neded to get around using the i2c numbers as names.
Thanks!
Regards,
Jean
Regards,
Tony
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[PATCH] ARM: OMAP: hwmod: align the SmartReflex fck names
Rename the smartreflex fck names:
- for consistency and better readability,
- for use by the SmartReflex driver, through the hwmod .main_clk
field.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/clock3xxx_data.c | 12 ++--
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |8
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index 83bed9a..6c1bdee 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3050,8 +3050,8 @@ static struct clk traceclk_fck = {
/* SR clocks */
/* SmartReflex fclk (VDD1) */
-static struct clk sr1_fck = {
- .name = sr1_fck,
+static struct clk smartreflex_mpu_iva_fck = {
+ .name = smartreflex_mpu_iva_fck,
.ops= clkops_omap2_dflt_wait,
.parent = sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3061,8 +3061,8 @@ static struct clk sr1_fck = {
};
/* SmartReflex fclk (VDD2) */
-static struct clk sr2_fck = {
- .name = sr2_fck,
+static struct clk smartreflex_core_fck = {
+ .name = smartreflex_core_fck,
.ops= clkops_omap2_dflt_wait,
.parent = sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@@ -3447,8 +3447,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, atclk_fck,atclk_fck, CK_3XXX),
CLK(NULL, traceclk_src_fck, traceclk_src_fck, CK_3XXX),
CLK(NULL, traceclk_fck, traceclk_fck, CK_3XXX),
- CLK(NULL, sr1_fck, sr1_fck, CK_34XX | CK_36XX),
- CLK(NULL, sr2_fck, sr2_fck, CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex_mpu_iva_fck,
smartreflex_mpu_iva_fck, CK_34XX | CK_36XX),
+ CLK(NULL, smartreflex_core_fck, smartreflex_core_fck, CK_34XX
| CK_36XX),
CLK(NULL, sr_l4_ick,sr_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, secure_32k_fck, secure_32k_fck, CK_3XXX),
CLK(NULL, gpt12_fck,gpt12_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index c9e3820..2b2b8fc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1359,7 +1359,7 @@ static struct omap_hwmod_irq_info
omap3_smartreflex_mpu_irqs[] = {
static struct omap_hwmod omap34xx_sr1_hwmod = {
.name = smartreflex_mpu_iva,
.class = omap34xx_smartreflex_hwmod_class,
- .main_clk = sr1_fck,
+ .main_clk = smartreflex_mpu_iva_fck,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1377,7 +1377,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
static struct omap_hwmod omap36xx_sr1_hwmod = {
.name = smartreflex_mpu_iva,
.class = omap36xx_smartreflex_hwmod_class,
- .main_clk = sr1_fck,
+ .main_clk = smartreflex_mpu_iva_fck,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1404,7 +1404,7 @@ static struct omap_hwmod_irq_info
omap3_smartreflex_core_irqs[] = {
static struct omap_hwmod omap34xx_sr2_hwmod = {
.name = smartreflex_core,
.class = omap34xx_smartreflex_hwmod_class,
- .main_clk = sr2_fck,
+ .main_clk = smartreflex_core_fck,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1422,7 +1422,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
static struct omap_hwmod omap36xx_sr2_hwmod = {
.name = smartreflex_core,
.class = omap36xx_smartreflex_hwmod_class,
- .main_clk = sr2_fck,
+ .main_clk = smartreflex_core_fck,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
--
1.7.7.6
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[PATCH] ARM: OMAP: SmartReflex: select CONFIG_POWER_SUPPLY in Kconfig
From: Jean Pihet j-pi...@ti.com Select POWER_SUPPLY from POWER_AVS_OMAP entry in Kconfig. This avoids the following build problems using a randconfig that has CONFIG_POWER_SUPPLY not set: LD init/built-in.o arch/arm/mach-omap2/built-in.o: In function `sr_class3_configure': arch/arm/mach-omap2/smartreflex-class3.c:44: undefined reference to `sr_configure_errgen' arch/arm/mach-omap2/built-in.o: In function `sr_class3_disable': arch/arm/mach-omap2/smartreflex-class3.c:33: undefined reference to `sr_disable_errgen' arch/arm/mach-omap2/smartreflex-class3.c:35: undefined reference to `sr_disable' arch/arm/mach-omap2/built-in.o: In function `sr_class3_enable': arch/arm/mach-omap2/smartreflex-class3.c:28: undefined reference to `sr_enable' arch/arm/mach-omap2/built-in.o: In function `sr_class3_init': arch/arm/mach-omap2/smartreflex-class3.c:59: undefined reference to `sr_register_class' make: *** [vmlinux] Error 1 Signed-off-by: Jean Pihet j-pi...@ti.com --- arch/arm/plat-omap/Kconfig |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index dd36eba..001a795 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -48,6 +48,7 @@ config OMAP_DEBUG_LEDS config POWER_AVS_OMAP bool AVS(Adaptive Voltage Scaling) support for OMAP IP versions 12 depends on POWER_AVS (ARCH_OMAP3 || ARCH_OMAP4) PM + select POWER_SUPPLY help Say Y to enable AVS(Adaptive Voltage Scaling) support on OMAP containing the version 1 or -- 1.7.7.6 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
Remove the device dependent settings (cpu_is_xxx(), IP fck etc.) from the driver code and pass them instead via the platform data. This allows a clean separation of the driver code and the platform code, as required by the recent re-org of the platform data header files. The patch also includes a fix of the error handling path in omap_sr_probe to correctly de-allocate resources in case of problems. $SUBJECT requires this change. Jean Pihet (2): ARM: OMAP: SmartReflex: fix error path in init function ARM: OMAP: SmartReflex: pass device dependent data via platform data arch/arm/mach-omap2/sr_device.c | 14 + drivers/power/avs/smartreflex.c | 57 +++- include/linux/power/smartreflex.h | 17 ++- 3 files changed, 53 insertions(+), 35 deletions(-) -- 1.7.7.6 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: OMAP: SmartReflex: pass device dependent data via platform data
Remove the device dependent settings (cpu_is_xxx(), IP fck etc.)
from the driver code and pass them instead via the platform
data.
This allows a clean separation of the driver code and the platform
code.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/sr_device.c | 14 ++
drivers/power/avs/smartreflex.c | 51 +++-
include/linux/power/smartreflex.h | 17 +++-
3 files changed, 50 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d033a65..12d95c8 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -118,10 +118,24 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void
*user)
}
sr_data-name = oh-name;
+ sr_data-fck_name = oh-main_clk;
sr_data-ip_type = oh-class-rev;
sr_data-senn_mod = 0x1;
sr_data-senp_mod = 0x1;
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ sr_data-err_weight = OMAP3430_SR_ERRWEIGHT;
+ sr_data-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+ sr_data-accum_data = OMAP3430_SR_ACCUMDATA;
+ if (!(strcmp(sr_data-name, smartreflex_mpu_iva))) {
+ sr_data-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+ } else {
+ sr_data-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+ }
+ }
+
sr_data-voltdm = voltdm_lookup(sr_dev_attr-sensor_voltdm_name);
if (IS_ERR(sr_data-voltdm)) {
pr_err(%s: Unable to get voltage domain pointer for VDD %s\n,
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 92f6728..f09e8df 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -131,14 +131,11 @@ static void sr_set_clk_length(struct omap_sr *sr)
struct clk *sys_ck;
u32 sys_clk_speed;
- if (cpu_is_omap34xx())
- sys_ck = clk_get(NULL, sys_ck);
- else
- sys_ck = clk_get(NULL, sys_clkin_ck);
+ sys_ck = clk_get(NULL, sr-fck_name);
if (IS_ERR(sys_ck)) {
- dev_err(sr-pdev-dev, %s: unable to get sys clk\n,
- __func__);
+ dev_err(sr-pdev-dev, %s: unable to get smartreflex fck
%s\n,
+ __func__, sr-fck_name);
return;
}
@@ -168,28 +165,6 @@ static void sr_set_clk_length(struct omap_sr *sr)
}
}
-static void sr_set_regfields(struct omap_sr *sr)
-{
- /*
-* For time being these values are defined in smartreflex.h
-* and populated during init. May be they can be moved to board
-* file or pmic specific data structure. In that case these structure
-* fields will have to be populated using the pdata or pmic structure.
-*/
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- sr-err_weight = OMAP3430_SR_ERRWEIGHT;
- sr-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
- sr-accum_data = OMAP3430_SR_ACCUMDATA;
- if (!(strcmp(sr-name, smartreflex_mpu_iva))) {
- sr-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
- } else {
- sr-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
- }
- }
-}
-
static void sr_start_vddautocomp(struct omap_sr *sr)
{
if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
@@ -915,6 +890,14 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
goto err_release_region;
}
+ sr_info-fck_name = kasprintf(GFP_KERNEL, %s, pdata-fck_name);
+ if (!sr_info-fck_name) {
+ dev_err(pdev-dev, %s: Unable to alloc SR instance fck
name\n,
+ __func__);
+ ret = -ENOMEM;
+ goto err_free_name;
+ }
+
sr_info-pdev = pdev;
sr_info-srid = pdev-id;
sr_info-voltdm = pdata-voltdm;
@@ -922,20 +905,25 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-nvalue_count = pdata-nvalue_count;
sr_info-senn_mod = pdata-senn_mod;
sr_info-senp_mod = pdata-senp_mod;
+ sr_info-err_weight = pdata-err_weight;
+ sr_info-err_maxlimit = pdata-err_maxlimit;
+ sr_info-accum_data = pdata-accum_data;
+ sr_info-senn_avgweight = pdata-senn_avgweight;
+ sr_info-senp_avgweight = pdata-senp_avgweight;
sr_info-autocomp_active = false;
sr_info-ip_type = pdata-ip_type;
+
sr_info-base = ioremap(mem-start, resource_size(mem
[PATCH 1/2] ARM: OMAP: SmartReflex: fix error path in init function
Fix the error handling path in omap_sr_probe to correctly
de-allocate resources in case of problems.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
drivers/power/avs/smartreflex.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 44efc6e..92f6728 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -928,7 +928,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
if (!sr_info-base) {
dev_err(pdev-dev, %s: ioremap fail\n, __func__);
ret = -ENOMEM;
- goto err_release_region;
+ goto err_free_name;
}
if (irq)
@@ -967,7 +967,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
dev_err(pdev-dev, %s: Unable to create debugfs directory\n,
__func__);
ret = PTR_ERR(sr_info-dbg_dir);
- goto err_free_name;
+ goto err_debugfs;
}
(void) debugfs_create_file(autocomp, S_IRUGO | S_IWUSR,
@@ -1011,11 +1011,11 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
err_debugfs:
debugfs_remove_recursive(sr_info-dbg_dir);
-err_free_name:
- kfree(sr_info-name);
err_iounmap:
list_del(sr_info-node);
iounmap(sr_info-base);
+err_free_name:
+ kfree(sr_info-name);
err_release_region:
release_mem_region(mem-start, resource_size(mem));
err_free_devinfo:
--
1.7.7.6
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[PATCH] ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints
Convert the driver from the outdated omap_pm_set_max_mpu_wakeup_lat
API to the new PM QoS API.
Since the constraint is on the MPU subsystem, use the PM_QOS_CPU_DMA_LATENCY
class of PM QoS. The resulting MPU constraints are used by cpuidle to
decide the next power state of the MPU subsystem.
The I2C device latency timing is derived from the FIFO size and the
clock speed and so is applicable to all OMAP SoCs.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
Rebased on git://git.pengutronix.de/git/wsa/linux.git, branch
i2c-embedded/for-next
---
arch/arm/plat-omap/i2c.c | 21 -
drivers/i2c/busses/i2c-omap.c | 32 ++--
include/linux/i2c-omap.h |1 -
3 files changed, 18 insertions(+), 36 deletions(-)
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 40bc06a..d29a2cc 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,7 +26,6 @@
#include linux/kernel.h
#include linux/platform_device.h
#include linux/i2c.h
-#include linux/i2c-omap.h
#include linux/slab.h
#include linux/err.h
#include linux/clk.h
@@ -34,7 +33,6 @@
#include mach/irqs.h
#include plat/mux.h
#include plat/i2c.h
-#include plat/omap-pm.h
#include plat/omap_device.h
#define OMAP_I2C_SIZE 0x3f
@@ -130,16 +128,6 @@ static inline int omap1_i2c_add_bus(int bus_id)
#ifdef CONFIG_ARCH_OMAP2PLUS
-/*
- * XXX This function is a temporary compatibility wrapper - only
- * needed until the I2C driver can be converted to call
- * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
- */
-static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
-{
- omap_pm_set_max_mpu_wakeup_lat(dev, t);
-}
-
static inline int omap2_i2c_add_bus(int bus_id)
{
int l;
@@ -171,15 +159,6 @@ static inline int omap2_i2c_add_bus(int bus_id)
dev_attr = (struct omap_i2c_dev_attr *)oh-dev_attr;
pdata-flags = dev_attr-flags;
- /*
-* When waiting for completion of a i2c transfer, we need to
-* set a wake up latency constraint for the MPU. This is to
-* ensure quick enough wakeup from idle, when transfer
-* completes.
-* Only omap3 has support for constraints
-*/
- if (cpu_is_omap34xx())
- pdata-set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
pdev = omap_device_build(name, bus_id, oh, pdata,
sizeof(struct omap_i2c_bus_platform_data),
NULL, 0, 0);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0b02543..db31eae 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -43,6 +43,7 @@
#include linux/slab.h
#include linux/i2c-omap.h
#include linux/pm_runtime.h
+#include linux/pm_qos.h
/* I2C controller revisions */
#define OMAP_I2C_OMAP1_REV_2 0x20
@@ -186,9 +187,8 @@ struct omap_i2c_dev {
int reg_shift; /* bit shift for I2C register
addresses */
struct completion cmd_complete;
struct resource *ioarea;
- u32 latency;/* maximum mpu wkup latency */
- void(*set_mpu_wkup_lat)(struct device *dev,
- long latency);
+ u32 latency;/* maximum MPU wkup latency */
+ struct pm_qos_request pm_qos_request;
u32 speed; /* Speed of bus in kHz */
u32 dtrev; /* extra revision from DT */
u32 flags;
@@ -494,9 +494,7 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev,
u8 size, bool is_rx)
dev-b_hw = 1; /* Enable hardware fixes */
/* calculate wakeup latency constraint for MPU */
- if (dev-set_mpu_wkup_lat != NULL)
- dev-latency = (100 * dev-threshold) /
- (1000 * dev-speed / 8);
+ dev-latency = (100 * dev-threshold) / (1000 * dev-speed / 8);
}
/*
@@ -631,8 +629,16 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
if (r 0)
goto out;
- if (dev-set_mpu_wkup_lat != NULL)
- dev-set_mpu_wkup_lat(dev-dev, dev-latency);
+ /*
+* When waiting for completion of a i2c transfer, we need to
+* set a wake up latency constraint for the MPU. This is to
+* ensure quick enough wakeup from idle, when transfer
+* completes.
+*/
+ if (dev-latency)
+ pm_qos_add_request(dev-pm_qos_request,
+ PM_QOS_CPU_DMA_LATENCY,
+ dev-latency);
for (i = 0; i num; i++) {
r = omap_i2c_xfer_msg(adap, msgs[i], (i == (num - 1)));
@@ -640,8 +646,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num
Re: [PATCH 7/8] ARM: OMAP: convert I2C driver to PM QoS for latency constraints
Hi!
On Wed, Sep 19, 2012 at 8:11 PM, Shubhrajyoti shubhrajy...@ti.com wrote:
On Tuesday 18 September 2012 02:22 PM, Jean Pihet wrote:
Convert the driver from the outdated omap_pm_set_max_mpu_wakeup_lat
API to the new PM QoS API.
Since the constraint is on the MPU subsystem, use the PM_QOS_CPU_DMA_LATENCY
class of PM QoS. The resulting MPU constraints are used by cpuidle to
decide the next power state of the MPU subsystem.
The I2C device latency timing is derived from the FIFO size and the
clock speed and so is applicable to all OMAP SoCs.
agree
thanks,
The I2C patch will be rebased and submitted separately.
Thanks!
Jean
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/plat-omap/i2c.c | 21 -
drivers/i2c/busses/i2c-omap.c | 28 +---
include/linux/i2c-omap.h |1 -
3 files changed, 17 insertions(+), 33 deletions(-)
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index db071bc..dba8338 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,7 +26,6 @@
#include linux/kernel.h
#include linux/platform_device.h
#include linux/i2c.h
-#include linux/i2c-omap.h
#include linux/slab.h
#include linux/err.h
#include linux/clk.h
@@ -34,7 +33,6 @@
#include mach/irqs.h
#include plat/mux.h
#include plat/i2c.h
-#include plat/omap-pm.h
#include plat/omap_device.h
#define OMAP_I2C_SIZE0x3f
@@ -129,16 +127,6 @@ static inline int omap1_i2c_add_bus(int bus_id)
#ifdef CONFIG_ARCH_OMAP2PLUS
-/*
- * XXX This function is a temporary compatibility wrapper - only
- * needed until the I2C driver can be converted to call
- * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
- */
-static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long
t)
-{
- omap_pm_set_max_mpu_wakeup_lat(dev, t);
-}
-
static inline int omap2_i2c_add_bus(int bus_id)
{
int l;
@@ -170,15 +158,6 @@ static inline int omap2_i2c_add_bus(int bus_id)
dev_attr = (struct omap_i2c_dev_attr *)oh-dev_attr;
pdata-flags = dev_attr-flags;
- /*
- * When waiting for completion of a i2c transfer, we need to
- * set a wake up latency constraint for the MPU. This is to
- * ensure quick enough wakeup from idle, when transfer
- * completes.
- * Only omap3 has support for constraints
- */
- if (cpu_is_omap34xx())
- pdata-set_mpu_wkup_lat =
omap_pm_set_max_mpu_wakeup_lat_compat;
pdev = omap_device_build(name, bus_id, oh, pdata,
sizeof(struct omap_i2c_bus_platform_data),
NULL, 0, 0);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 5d19a49..bd45cee 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -43,6 +43,7 @@
#include linux/slab.h
#include linux/i2c-omap.h
#include linux/pm_runtime.h
+#include linux/pm_qos.h
/* I2C controller revisions */
#define OMAP_I2C_OMAP1_REV_2 0x20
@@ -183,8 +184,7 @@ struct omap_i2c_dev {
struct completion cmd_complete;
struct resource *ioarea;
u32 latency;/* maximum mpu wkup latency */
- void(*set_mpu_wkup_lat)(struct device *dev,
- long latency);
+ struct pm_qos_request pm_qos_request;
u32 speed; /* Speed of bus in kHz */
u32 dtrev; /* extra revision from DT */
u32 flags;
@@ -590,8 +590,16 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
if (r 0)
goto out;
- if (dev-set_mpu_wkup_lat != NULL)
- dev-set_mpu_wkup_lat(dev-dev, dev-latency);
+ /*
+ * When waiting for completion of a i2c transfer, we need to
+ * set a wake up latency constraint for the MPU. This is to
+ * ensure quick enough wakeup from idle, when transfer
+ * completes.
+ */
+ if (dev-latency)
+ pm_qos_add_request(dev-pm_qos_request,
+PM_QOS_CPU_DMA_LATENCY,
+dev-latency);
for (i = 0; i num; i++) {
r = omap_i2c_xfer_msg(adap, msgs[i], (i == (num - 1)));
@@ -599,8 +607,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
break;
}
- if (dev-set_mpu_wkup_lat != NULL)
- dev-set_mpu_wkup_lat(dev-dev, -1);
+ if (dev-latency)
+ pm_qos_remove_request(dev-pm_qos_request);
if (r == 0)
r = num;
@@ -989,7 +997,6 @@ omap_i2c_probe(struct platform_device *pdev)
} else if (pdata != NULL) {
dev-speed = pdata-clkrate;
dev-flags = pdata-flags;
- dev
[PATCH 1/8] ARM: OMAP2+: PM QoS: control the power domains next state from the constraints
When a PM QoS device latency constraint is requested or removed the
constraint is stored in the constraints list of the corresponding power
domain, then the aggregated constraint value is applied by programming
the next functional power state using pwrdm_set_fpwrst.
The per-device PM QoS locking requires a spinlock to be used. The reasons
is that some drivers need to use the per-device PM QoS functionality from
interrupt context or spinlock protected context, as reported by Djamil.
An example of such a driver is the OMAP HSI (high-speed synchronous serial
interface) driver which needs to control the IP block idle state from
the FIFO empty state, from interrupt context.
Tested on OMAP3 Beagleboard and OMAP4 Pandaboard in RET/OFF using
wake-up latency constraints on MPU, CORE and PER.
Signed-off-by: Jean Pihet j-pi...@ti.com
Cc: Djamil Elaidi d-ela...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 212 +
arch/arm/mach-omap2/powerdomain.h | 18 +++-
2 files changed, 229 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 37dfabf..3d81ac7 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -17,8 +17,10 @@
#include linux/kernel.h
#include linux/types.h
#include linux/list.h
+#include linux/slab.h
#include linux/errno.h
#include linux/string.h
+#include linux/pm_qos.h
#include linux/ratelimit.h
#include trace/events/power.h
@@ -114,6 +116,12 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
for (i = 0; i pwrdm-banks; i++)
pwrdm-ret_mem_off_counter[i] = 0;
+ /* Initialize the per-device wake-up constraints framework data */
+ spin_lock_init(pwrdm-wkup_lat_plist_lock);
+ plist_head_init(pwrdm-wkup_lat_plist_head);
+ pwrdm-wkup_lat_next_state = PWRDM_FUNC_PWRST_OFF;
+
+ /* Initialize the pwrdm state */
pwrdm_wait_transition(pwrdm);
pwrdm-state = pwrdm_read_fpwrst(pwrdm);
pwrdm-state_counter[pwrdm-state] = 1;
@@ -418,6 +426,60 @@ static int _pwrdm_read_next_fpwrst(struct powerdomain
*pwrdm)
return _pwrdm_pwrst_to_fpwrst(pwrdm, next_pwrst, next_logic);
}
+/**
+ * _pwrdm_wakeuplat_update_pwrst - Update power domain power state if needed
+ * @pwrdm: struct powerdomain * to which requesting device belongs to.
+ * @min_latency: the allowed wake-up latency for the given power domain. A
+ * value of PM_QOS_DEV_LAT_DEFAULT_VALUE means 'no constraint' on the pwrdm.
+ *
+ * Finds the power domain next power state that fulfills the constraint.
+ * Programs a new target state if it is different from current power state.
+ * The power domains get the next power state programmed directly in the
+ * registers.
+ *
+ * Must be called with the wkup_lat_plist_lock lock held.
+ *
+ * Returns 0 in case of success, -EINVAL in case of invalid parameters,
+ * or the return value from pwrdm_set_fpwrst.
+ */
+static int _pwrdm_wakeuplat_update_pwrst(struct powerdomain *pwrdm,
+long min_latency)
+{
+ int ret = 0, state, new_state = PWRDM_FUNC_PWRST_ON;
+
+ if (!pwrdm) {
+ WARN(1, powerdomain: %s: invalid parameter(s), __func__);
+ return -EINVAL;
+ }
+
+ /*
+* Find the next supported power state with
+* wakeup latency = min_latency.
+* Pick the lower state if no constraint on the pwrdm
+* (min_latency == PM_QOS_DEV_LAT_DEFAULT_VALUE).
+* Skip the states marked as unsupported (UNSUP_STATE).
+* If no power state found, fall back to PWRDM_FUNC_PWRST_ON.
+*/
+ for (state = 0x0; state PWRDM_MAX_FUNC_PWRSTS; state++) {
+ if ((min_latency == PM_QOS_DEV_LAT_DEFAULT_VALUE) ||
+ ((pwrdm-wakeup_lat[state] != UNSUP_STATE)
+(pwrdm-wakeup_lat[state] = min_latency))) {
+ new_state = state;
+ break;
+ }
+ }
+
+ pwrdm-wkup_lat_next_state = new_state;
+ ret = pwrdm_set_fpwrst(pwrdm, new_state);
+
+ pr_debug(%s: func pwrst for %s: curr=%d, next=%d, min_latency=%ld,
new_state=%d\n,
+__func__, pwrdm-name, pwrdm_read_fpwrst(pwrdm),
+pwrdm_read_next_fpwrst(pwrdm), min_latency, new_state);
+
+ return ret;
+}
+
+
/* Public functions */
/**
@@ -1484,6 +1546,156 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
}
/**
+ * pwrdm_wakeuplat_update_constraint - Set or update a powerdomain wakeup
+ * latency constraint and apply it
+ * @pwrdm: struct powerdomain * which the constraint applies to
+ * @cookie: constraint identifier, used for tracking
+ * @min_latency: minimum wakeup latency constraint (in microseconds) for
+ * the given pwrdm
+ *
+ * Tracks the constraints by @cookie.
+ * Constraint set/update: Adds a new entry to powerdomain's wake-up latency
+ * constraint list
[PATCH v9 0/8] PM QoS: implement the OMAP low level constraints management code
. Implement the devices wake-up latency constraints using the global device PM QoS notification handler which applies the constraints to the underlying layer, . Implement the low level code which controls the power domains next functional power states, through the hwmod and pwrdm layers, . Add cpuidle and power domains wake-up latency figures for OMAP3, cf. comments in the code and [1] for the details on where the numbers are magically coming from, . Implement the relation between the cpuidle and per-device PM QoS frameworks in the OMAP3 specific idle callbacks. The chosen C-state shall satisfy the following conditions: . it satisfies the enable_off_mode flag, . the next state for MPU and CORE power domains is not lower than the state programmed by the per-device PM QoS. . convert I2C driver to PM QoS for latency constraints, . remove the latency related functions from the API (omap_pm_set_*) and update the kernel Documentation accordingly. ToDo: 1. Re-visit the OMAP power domains states initialization procedure. Currently the power states that have been changed from the constraints API which were applied before the initialization of the power domains are lost 2. Further clean-up the OMAP PM layer, use the generic frameworks instead (OPP, PM QoS for throughput constraints ...) Based on mainline kernel 3.6.0-rc4 with the functional power states changes v6 [2] applied. Tested cpuidle and suspend on OMAP3 Beagleboard (ES2.x) with constraints on MPU, CORE, PER in RETention and OFF modes. [1] http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement [2] http://marc.info/?l=linux-omapm=134744375320874w=2 History: v9: . ported to latest functional power states code, . changed the locking from mutex to spinlock, as reported by Djamil Elaidi d-ela...@ti.com, . simplified the memory allocation code, using GFP_ATOMIC since the code can be used under spinlock v8: . reworked the code after internal review and testing with OMAP34 device OFF v7: . rebased on top of the functional power state changes v6: . minor change in the commits description after Kevin's review . added Kevin's Reviewed-by v5: . rebased on latest linux-omap . rework after Kevin's comments on the MLs v4: . split up the patches which remove the omap_pm_ code from the patch set. Those patches are to be submitted later, on top of this patch set. . latency numbers: provide the measurements setup and conditions in the code comments, added the link to the details on wiki [1]. . improved kerneldoc . split big functions into smaller ones, in order to improve the readability v3: reworked the error return path and improved the kerneldoc v2: reworked the OMAP specific cpuidle code to demote the initial C-state to a valid C-state which fulfills the per-device constraints v1: initial version Jean Pihet (8): ARM: OMAP2+: PM QoS: control the power domains next state from the constraints ARM: OMAP2+: hwmod: manage the wake-up latency constraints ARM: OMAP: omap_device: register to the per-device PM QoS framework ARM: OMAP3: cpuidle: next C-state decision depends on the PM QoS MPU and CORE constraints ARM: OMAP3: update cpuidle latency and threshold figures ARM: OMAP3: powerdomain data: add wake-up latency figures ARM: OMAP: convert I2C driver to PM QoS for latency constraints ARM: OMAP: PM: remove the latency related functions from the API Documentation/arm/OMAP/omap_pm | 68 +++-- arch/arm/mach-omap2/cpuidle34xx.c| 103 + arch/arm/mach-omap2/omap_hwmod.c | 44 +- arch/arm/mach-omap2/powerdomain.c| 212 ++ arch/arm/mach-omap2/powerdomain.h| 18 ++- arch/arm/mach-omap2/powerdomains3xxx_data.c | 83 ++ arch/arm/plat-omap/i2c.c | 21 --- arch/arm/plat-omap/include/plat/omap-pm.h| 99 arch/arm/plat-omap/include/plat/omap_hwmod.h |5 + arch/arm/plat-omap/omap-pm-noop.c| 88 --- arch/arm/plat-omap/omap_device.c | 81 ++- drivers/i2c/busses/i2c-omap.c| 28 ++-- include/linux/i2c-omap.h |1 - 13 files changed, 550 insertions(+), 301 deletions(-) -- 1.7.7.6 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/8] ARM: OMAP3: update cpuidle latency and threshold figures
Update the data from the measurements performed at HW and SW levels.
Cf. http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement
for a detailed explanation on where are the numbers coming from.
ToDo:
- Measure the wake-up latencies for all power domains for OMAP3
- Correct some numbers when sys_clkreq and sys_offmode are supported
Signed-off-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 54 ++--
1 files changed, 39 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index ca6cb71..c086374 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -280,63 +280,87 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
*
* - target_residency: required amount of time in the C state
* to break even on energy cost
+ *
+ * The MPU latency and threshold values for the C-states are the worst case
+ * values from the HW and SW, as described in details at
+ *
http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement#cpuidle_results
+ *
+ * Measurements conditions and remarks:
+ * . the measurements have been performed at OPP50
+ * . the sys_offmode signal is not supported and so not used for the
+ *measurements. Instead the latency and threshold values for C9 are
+ *corrected with the value for Triton 2, which is 11.5ms
+ * . the sys_clkreq signal is not used and so a correction is needed - TBD
+ * . the sys_clkoff signal is supported, this value need to be corrected with
+ *the correct value of SYSCLK on/off timings (1ms for sysclk on, 2.5ms
+ *for sysclk off)
+ * . the setup time of DPLLs is included in the measured values. However
+ *this is only valid for DPLLs that are enabled to auto-idle at
+ *measurement time. There currently is no provision for the dynamic
+ *nature of the auto-idle setting
+ * . in order to force the cpuidle algorithm to chose the power efficient
+ *C-states (C1, C3, C5, C7) in preference, the other C-states have a
+ *threshold value equal to the next power efficient C-state
+ *
+ * The latency and threshold values can be overriden by data from the board
+ * files, using omap3_pm_init_cpuidle.
*/
struct cpuidle_driver omap3_idle_driver = {
.name = omap3_idle,
.owner =THIS_MODULE,
.states = {
{
- .enter= omap3_enter_idle_bm,
- .exit_latency = 2 + 2,
- .target_residency = 5,
+ .enter= omap3_enter_idle,
+ .exit_latency = 73 + 78,
+ .target_residency = 152,
.flags= CPUIDLE_FLAG_TIME_VALID,
.name = C1,
.desc = MPU ON + CORE ON,
},
{
.enter= omap3_enter_idle_bm,
- .exit_latency = 10 + 10,
- .target_residency = 30,
+ .exit_latency = 165 + 88,
+ .target_residency = 345,
.flags= CPUIDLE_FLAG_TIME_VALID,
.name = C2,
.desc = MPU ON + CORE ON,
},
{
.enter= omap3_enter_idle_bm,
- .exit_latency = 50 + 50,
- .target_residency = 300,
+ .exit_latency = 163 + 182,
+ .target_residency = 345,
.flags= CPUIDLE_FLAG_TIME_VALID,
.name = C3,
.desc = MPU RET + CORE ON,
},
{
.enter= omap3_enter_idle_bm,
- .exit_latency = 1500 + 1800,
- .target_residency = 4000,
+ .exit_latency = 2852 + 605,
+ .target_residency = 15,
.flags= CPUIDLE_FLAG_TIME_VALID,
.name = C4,
.desc = MPU OFF + CORE ON,
},
{
.enter= omap3_enter_idle_bm,
- .exit_latency = 2500 + 7500,
- .target_residency = 12000,
+ .exit_latency = 800 + 366,
+ .target_residency = 2120,
.flags= CPUIDLE_FLAG_TIME_VALID,
.name = C5,
.desc = MPU RET + CORE RET
[PATCH 6/8] ARM: OMAP3: powerdomain data: add wake-up latency figures
Figures are added to the power domains structs for RET and OFF modes.
Note: the latency figures for MPU, PER, CORE, NEON have been obtained
from actual measurements.
The latency figures for the other power domains are preliminary and
shall be added.
Cf. http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement
for a detailed explanation on where are the numbers coming from.
Tested on OMAP3 Beagleboard in RET/OFF using wake-up latency constraints
on MPU, CORE and PER.
Signed-off-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/powerdomains3xxx_data.c | 83 +++
1 files changed, 83 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c
b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index bb883e4..2195518 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -32,6 +32,19 @@
/*
* Powerdomains
+ *
+ * The wakeup_lat values are derived from HW and SW measurements on
+ * the actual target. For more details cf.
+ *
http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement#Results_for_individual_power_domains
+ *
+ * Note: the latency figures for MPU, PER, CORE, NEON have been obtained
+ * from actual measurements.
+ * The latency figures for the other power domains are preliminary and
+ * shall be added.
+ *
+ * Note: only the SW restore timing values are taken into account.
+ * The HW impact of the sys_clkreq and sys_offmode signals is not taken
+ * into account - TDB
*/
static struct powerdomain iva2_pwrdm = {
@@ -52,6 +65,13 @@ static struct powerdomain iva2_pwrdm = {
[2] = PWRSTS_OFF_ON,
[3] = PWRSTS_ON,
},
+ .wakeup_lat = {
+ [PWRDM_FUNC_PWRST_OFF] = 1100,
+ [PWRDM_FUNC_PWRST_OSWR] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_CSWR] = 350,
+ [PWRDM_FUNC_PWRST_INACTIVE] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_ON] = 0,
+ },
.voltdm = { .name = mpu_iva },
};
@@ -68,6 +88,13 @@ static struct powerdomain mpu_3xxx_pwrdm = {
.pwrsts_mem_on= {
[0] = PWRSTS_OFF_ON,
},
+ .wakeup_lat = {
+ [PWRDM_FUNC_PWRST_OFF] = 1830,
+ [PWRDM_FUNC_PWRST_OSWR] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_CSWR] = 121,
+ [PWRDM_FUNC_PWRST_INACTIVE] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_ON] = 0,
+ },
.voltdm = { .name = mpu_iva },
};
@@ -111,6 +138,13 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
},
+ .wakeup_lat = {
+ [PWRDM_FUNC_PWRST_OFF] = 3082,
+ [PWRDM_FUNC_PWRST_OSWR] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_CSWR] = 153,
+ [PWRDM_FUNC_PWRST_INACTIVE] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_ON] = 0,
+ },
.voltdm = { .name = core },
};
@@ -133,6 +167,13 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
},
+ .wakeup_lat = {
+ [PWRDM_FUNC_PWRST_OFF] = 3082,
+ [PWRDM_FUNC_PWRST_OSWR] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_CSWR] = 153,
+ [PWRDM_FUNC_PWRST_INACTIVE] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_ON] = 0,
+ },
.voltdm = { .name = core },
};
@@ -165,6 +206,13 @@ static struct powerdomain dss_pwrdm = {
.pwrsts_mem_on= {
[0] = PWRSTS_ON, /* MEMONSTATE */
},
+ .wakeup_lat = {
+ [PWRDM_FUNC_PWRST_OFF] = 70,
+ [PWRDM_FUNC_PWRST_OSWR] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_CSWR] = 20,
+ [PWRDM_FUNC_PWRST_INACTIVE] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_ON] = 0,
+ },
.voltdm = { .name = core },
};
@@ -180,6 +228,13 @@ static struct powerdomain dss_am35x_pwrdm = {
.pwrsts_mem_on= {
[0] = PWRSTS_ON, /* MEMONSTATE */
},
+ .wakeup_lat = {
+ [PWRDM_FUNC_PWRST_OFF] = 1000,
+ [PWRDM_FUNC_PWRST_OSWR] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_CSWR] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_INACTIVE] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_ON] = 0,
+ },
.voltdm = { .name = core },
};
@@ -201,6 +256,13 @@ static struct powerdomain sgx_pwrdm = {
.pwrsts_mem_on= {
[0] = PWRSTS_ON, /* MEMONSTATE */
},
+ .wakeup_lat = {
+ [PWRDM_FUNC_PWRST_OFF] = 850,
+ [PWRDM_FUNC_PWRST_OSWR] = UNSUP_STATE,
+ [PWRDM_FUNC_PWRST_CSWR
[PATCH 3/8] ARM: OMAP: omap_device: register to the per-device PM QoS framework
Implement the devices wake-up latency constraints using the global
device PM QoS notification handler which applies the constraints to the
underlying layer by calling the corresponding function at hwmod level.
Reworked after Paul's suggestions.
Tested on OMAP3 Beagleboard and OMAP4 Pandaboard in RET/OFF using wake-up
latency constraints on MPU, CORE and PER.
Signed-off-by: Jean Pihet j-pi...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/plat-omap/omap_device.c | 81 +-
1 files changed, 80 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..011825f 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -3,6 +3,7 @@
* omap_device implementation
*
* Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley, Kevin Hilman
*
* Developed in collaboration with (alphabetical order): Benoit
@@ -89,6 +90,7 @@
#include linux/pm_runtime.h
#include linux/of.h
#include linux/notifier.h
+#include linux/pm_qos.h
#include plat/omap_device.h
#include plat/omap_hwmod.h
@@ -401,6 +403,72 @@ static int _omap_device_notifier_call(struct
notifier_block *nb,
return NOTIFY_DONE;
}
+/**
+ * _omap_device_pm_qos_handler - interface to the per-device PM QoS framework
+ * @nb: pointer to omap_device_pm_qos_nb (not used)
+ * @new_value: new maximum wakeup latency constraint for @req-dev (in us)
+ * @req: struct dev_pm_qos_request * passed by the Linux PM QoS code
+ *
+ * Called by the Linux core device PM QoS code to alter the maximum
+ * wakeup latency constraint on a device. If the underlying device is
+ * an omap_device, then this code will pass the constraint on to the
+ * underlying hwmods. Returns -EINVAL if this code can't handle the
+ * constraint for some reason, or passes along the return code from the
+ * hwmod wakeup latency constraint functions.
+ */
+static int _omap_device_pm_qos_handler(struct notifier_block *nb,
+ unsigned long new_value,
+ void *req)
+{
+ struct omap_device *od;
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
+ struct dev_pm_qos_request *dev_pm_qos_req = req;
+ int ret = NOTIFY_OK;
+ int r, i;
+
+ pr_debug(OMAP PM constraints: req@0x%p, new_value=%lu\n,
+req, new_value);
+
+ /* Look for the platform device for the constraint target device */
+ pdev = to_platform_device(dev_pm_qos_req-dev);
+
+ /* Try to catch non platform devices */
+ if (pdev-name == NULL) {
+ pr_err(%s: Error: platform device for device %s not valid\n,
+ __func__, dev_name(dev_pm_qos_req-dev));
+ return NOTIFY_DONE;
+ }
+
+ /* Find the associated omap_device for dev */
+ od = to_omap_device(pdev);
+ if (od == NULL) {
+ pr_err(%s: Error: no omap_device for device %s\n,
+ __func__, dev_name(dev_pm_qos_req-dev));
+ return NOTIFY_DONE;
+ }
+
+ pr_debug(OMAP PM constraints: req@0x%p, dev=0x%p, new_value=%lu\n,
+req, dev_pm_qos_req-dev, new_value);
+
+ for (i = 0; i od-hwmods_cnt; i++) {
+ oh = od-hwmods[i];
+ if (new_value == PM_QOS_DEV_LAT_DEFAULT_VALUE)
+ r = omap_hwmod_remove_wakeuplat_constraint(
+ oh,
+ dev_pm_qos_req);
+ else
+ r = omap_hwmod_set_wakeuplat_constraint(
+ oh,
+ dev_pm_qos_req,
+ new_value);
+
+ if (!r)
+ ret = NOTIFY_BAD;
+ }
+
+ return ret;
+}
/* Public functions for use by core code */
@@ -1115,13 +1183,24 @@ int omap_device_enable_clocks(struct omap_device *od)
return 0;
}
+static struct notifier_block omap_device_pm_qos_nb = {
+ .notifier_call = _omap_device_pm_qos_handler,
+};
+
static struct notifier_block platform_nb = {
.notifier_call = _omap_device_notifier_call,
};
static int __init omap_device_init(void)
{
+ int ret;
+
bus_register_notifier(platform_bus_type, platform_nb);
- return 0;
+
+ ret = dev_pm_qos_add_global_notifier(omap_device_pm_qos_nb);
+ if (ret)
+ pr_err(omap_device: cannot add global notifier for dev PM
QoS\n);
+
+ return ret;
}
core_initcall(omap_device_init);
--
1.7.7.6
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[PATCH 7/8] ARM: OMAP: convert I2C driver to PM QoS for latency constraints
Convert the driver from the outdated omap_pm_set_max_mpu_wakeup_lat
API to the new PM QoS API.
Since the constraint is on the MPU subsystem, use the PM_QOS_CPU_DMA_LATENCY
class of PM QoS. The resulting MPU constraints are used by cpuidle to
decide the next power state of the MPU subsystem.
The I2C device latency timing is derived from the FIFO size and the
clock speed and so is applicable to all OMAP SoCs.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/plat-omap/i2c.c | 21 -
drivers/i2c/busses/i2c-omap.c | 28 +---
include/linux/i2c-omap.h |1 -
3 files changed, 17 insertions(+), 33 deletions(-)
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index db071bc..dba8338 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,7 +26,6 @@
#include linux/kernel.h
#include linux/platform_device.h
#include linux/i2c.h
-#include linux/i2c-omap.h
#include linux/slab.h
#include linux/err.h
#include linux/clk.h
@@ -34,7 +33,6 @@
#include mach/irqs.h
#include plat/mux.h
#include plat/i2c.h
-#include plat/omap-pm.h
#include plat/omap_device.h
#define OMAP_I2C_SIZE 0x3f
@@ -129,16 +127,6 @@ static inline int omap1_i2c_add_bus(int bus_id)
#ifdef CONFIG_ARCH_OMAP2PLUS
-/*
- * XXX This function is a temporary compatibility wrapper - only
- * needed until the I2C driver can be converted to call
- * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
- */
-static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
-{
- omap_pm_set_max_mpu_wakeup_lat(dev, t);
-}
-
static inline int omap2_i2c_add_bus(int bus_id)
{
int l;
@@ -170,15 +158,6 @@ static inline int omap2_i2c_add_bus(int bus_id)
dev_attr = (struct omap_i2c_dev_attr *)oh-dev_attr;
pdata-flags = dev_attr-flags;
- /*
-* When waiting for completion of a i2c transfer, we need to
-* set a wake up latency constraint for the MPU. This is to
-* ensure quick enough wakeup from idle, when transfer
-* completes.
-* Only omap3 has support for constraints
-*/
- if (cpu_is_omap34xx())
- pdata-set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
pdev = omap_device_build(name, bus_id, oh, pdata,
sizeof(struct omap_i2c_bus_platform_data),
NULL, 0, 0);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 5d19a49..bd45cee 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -43,6 +43,7 @@
#include linux/slab.h
#include linux/i2c-omap.h
#include linux/pm_runtime.h
+#include linux/pm_qos.h
/* I2C controller revisions */
#define OMAP_I2C_OMAP1_REV_2 0x20
@@ -183,8 +184,7 @@ struct omap_i2c_dev {
struct completion cmd_complete;
struct resource *ioarea;
u32 latency;/* maximum mpu wkup latency */
- void(*set_mpu_wkup_lat)(struct device *dev,
- long latency);
+ struct pm_qos_request pm_qos_request;
u32 speed; /* Speed of bus in kHz */
u32 dtrev; /* extra revision from DT */
u32 flags;
@@ -590,8 +590,16 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
if (r 0)
goto out;
- if (dev-set_mpu_wkup_lat != NULL)
- dev-set_mpu_wkup_lat(dev-dev, dev-latency);
+ /*
+* When waiting for completion of a i2c transfer, we need to
+* set a wake up latency constraint for the MPU. This is to
+* ensure quick enough wakeup from idle, when transfer
+* completes.
+*/
+ if (dev-latency)
+ pm_qos_add_request(dev-pm_qos_request,
+ PM_QOS_CPU_DMA_LATENCY,
+ dev-latency);
for (i = 0; i num; i++) {
r = omap_i2c_xfer_msg(adap, msgs[i], (i == (num - 1)));
@@ -599,8 +607,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
break;
}
- if (dev-set_mpu_wkup_lat != NULL)
- dev-set_mpu_wkup_lat(dev-dev, -1);
+ if (dev-latency)
+ pm_qos_remove_request(dev-pm_qos_request);
if (r == 0)
r = num;
@@ -989,7 +997,6 @@ omap_i2c_probe(struct platform_device *pdev)
} else if (pdata != NULL) {
dev-speed = pdata-clkrate;
dev-flags = pdata-flags;
- dev-set_mpu_wkup_lat = pdata-set_mpu_wkup_lat;
dev-dtrev = pdata-rev;
}
@@ -1046,10 +1053,9 @@ omap_i2c_probe(struct platform_device *pdev)
else
dev-b_hw = 1; /* Enable hardware fixes
[PATCH 8/8] ARM: OMAP: PM: remove the latency related functions from the API
Remove the following functions from the OMAP PM API: omap_pm_set_max_mpu_wakeup_lat omap_pm_set_max_dev_wakeup_lat omap_pm_set_max_sdma_lat and updated the kernel Documentation accordingly. The generic per-device PM QoS functions shall be used instead of the OMAP PM API, cf. include/linux/pm_qos.h and Documentation/power/pm_qos_interface.txt. Signed-off-by: Jean Pihet j-pi...@ti.com --- Documentation/arm/OMAP/omap_pm| 68 ++-- arch/arm/plat-omap/include/plat/omap-pm.h | 99 - arch/arm/plat-omap/omap-pm-noop.c | 88 - 3 files changed, 21 insertions(+), 234 deletions(-) diff --git a/Documentation/arm/OMAP/omap_pm b/Documentation/arm/OMAP/omap_pm index 9012bb0..90f67a3 100644 --- a/Documentation/arm/OMAP/omap_pm +++ b/Documentation/arm/OMAP/omap_pm @@ -5,8 +5,19 @@ The OMAP PM interface This document describes the temporary OMAP PM interface. Driver authors use these functions to communicate minimum latency or throughput constraints to the kernel power management code. + Over time, the intention is to merge features from the OMAP PM interface into the Linux PM QoS code. +The following PM QoS features already migrated to the PM QoS framework: +- PM QoS CPU and DMA latency: used to specify the maximum allowed wake-up + latency for the CPU, +- per device PM QoS latency: used to specifiy the maximum allowed wake-up + latency for a given device. + +Please refer to the corresponding header file and kernel documentation +for the PM QoS framework, respectively at include/linux/pm_qos.h and +Documentation/power/pm_qos_interface.txt. + Drivers need to express PM parameters which: @@ -29,21 +40,12 @@ Drivers need to express PM parameters which: This document proposes the OMAP PM interface, including the following -five power management functions for driver code: - -1. Set the maximum MPU wakeup latency: - (*pdata-set_max_mpu_wakeup_lat)(struct device *dev, unsigned long t) +power management functions for driver code: -2. Set the maximum device wakeup latency: - (*pdata-set_max_dev_wakeup_lat)(struct device *dev, unsigned long t) - -3. Set the maximum system DMA transfer start latency (CORE pwrdm): - (*pdata-set_max_sdma_lat)(struct device *dev, long t) - -4. Set the minimum bus throughput needed by a device: +1. Set the minimum bus throughput needed by a device: (*pdata-set_min_bus_tput)(struct device *dev, u8 agent_id, unsigned long r) -5. Return the number of times the device has lost context +2. Return the number of times the device has lost context (*pdata-get_dev_context_loss_count)(struct device *dev) @@ -55,10 +57,12 @@ The OMAP PM layer is intended to be temporary - The intention is that eventually the Linux PM QoS layer should support -the range of power management features present in OMAP3. As this -happens, existing drivers using the OMAP PM interface can be modified +the range of power management features present in OMAP3. As this +happens, existing drivers using the OMAP PM interface shall be modified to use the Linux PM QoS code; and the OMAP PM interface can disappear. +The set_min_bus_tput function shall be converted to a throughput PM QoS +framework. Driver usage of the OMAP PM functions - @@ -66,39 +70,9 @@ Driver usage of the OMAP PM functions As the 'pdata' in the above examples indicates, these functions are exposed to drivers through function pointers in driver .platform_data structures. The function pointers are initialized by the board-*.c -files to point to the corresponding OMAP PM functions: -.set_max_dev_wakeup_lat will point to -omap_pm_set_max_dev_wakeup_lat(), etc. Other architectures which do -not support these functions should leave these function pointers set -to NULL. Drivers should use the following idiom: - -if (pdata-set_max_dev_wakeup_lat) -(*pdata-set_max_dev_wakeup_lat)(dev, t); - -The most common usage of these functions will probably be to specify -the maximum time from when an interrupt occurs, to when the device -becomes accessible. To accomplish this, driver writers should use the -set_max_mpu_wakeup_lat() function to to constrain the MPU wakeup -latency, and the set_max_dev_wakeup_lat() function to constrain the -device wakeup latency (from clk_enable() to accessibility). For -example, - -/* Limit MPU wakeup latency */ -if (pdata-set_max_mpu_wakeup_lat) -(*pdata-set_max_mpu_wakeup_lat)(dev, tc); - -/* Limit device powerdomain wakeup latency */ -if (pdata-set_max_dev_wakeup_lat) -(*pdata-set_max_dev_wakeup_lat)(dev, td); - -/* total wakeup latency in this example: (tc + td) */ - -The PM parameters can be overwritten by calling the function again -with the new value. The settings can be removed by calling the -function with a t argument of -1 (except
[PATCH 2/8] ARM: OMAP2+: hwmod: manage the wake-up latency constraints
The OMAP PM code implements a handler for the per-device PM QoS framework.
The handler queries the omap_hwmod layer in order to manage the power domains
wake-up latency constraints. Hwmod retrieves the correct power domain
and if it exists it calls the corresponding power domain function.
Tested on OMAP3 Beagleboard and OMAP4 Pandaboard in RET/OFF using wake-up
latency constraints on MPU, CORE and PER.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 44 +-
arch/arm/plat-omap/include/plat/omap_hwmod.h |5 +++
2 files changed, 48 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..5990835 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -145,6 +145,7 @@
#include powerdomain.h
#include plat/clock.h
#include plat/omap_hwmod.h
+#include plat/omap_device.h
#include plat/prcm.h
#include cm2xxx_3xxx.h
@@ -3554,10 +3555,51 @@ ohsps_unlock:
}
/**
+ * omap_hwmod_set_wakeuplat_constraint - Set or update a wake-up latency
+ * constraint
+ * @oh: struct omap_hwmod* to which the target device belongs to.
+ * @cookie: identifier of the constraints list for @oh.
+ * @min_latency: the minimum allowed wake-up latency for @oh.
+ *
+ * Returns the return value from pwrdm_wakeuplat_update_constraint(),
+ * or -EINVAL in case of invalid parameters.
+ */
+int omap_hwmod_set_wakeuplat_constraint(struct omap_hwmod *oh, void *cookie,
+ long min_latency)
+{
+ struct powerdomain *pwrdm = omap_hwmod_get_pwrdm(oh);
+
+ if (!pwrdm)
+ return -EINVAL;
+
+ return pwrdm_wakeuplat_update_constraint(pwrdm, cookie, min_latency);
+}
+
+/**
+ * omap_hwmod_remove_wakeuplat_constraint - Release a wake-up latency
+ * constraint
+ * @oh: struct omap_hwmod* to which the target device belongs to.
+ * @cookie: identifier of the constraints list for @oh.
+ *
+ * Removes a wakeup latency contraint. Returns the return value from
+ * pwrdm_wakeuplat_remove_constraint(), or -EINVAL in case of invalid
+ * parameters.
+ */
+int omap_hwmod_remove_wakeuplat_constraint(struct omap_hwmod *oh, void *cookie)
+{
+ struct powerdomain *pwrdm = omap_hwmod_get_pwrdm(oh);
+
+ if (!pwrdm)
+ return -EINVAL;
+
+ return pwrdm_wakeuplat_remove_constraint(pwrdm, cookie);
+}
+
+/**
* omap_hwmod_get_context_loss_count - get lost context count
* @oh: struct omap_hwmod *
*
- * Query the powerdomain of of @oh to get the context loss
+ * Query the powerdomain of @oh to get the context loss
* count for this device.
*
* Returns the context loss count of the powerdomain assocated with @oh
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h
b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972..fa0b350 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -640,6 +640,11 @@ int omap_hwmod_for_each_by_class(const char *classname,
void *user);
int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
+
+int omap_hwmod_set_wakeuplat_constraint(struct omap_hwmod *oh, void *cookie,
+ long min_latency);
+int omap_hwmod_remove_wakeuplat_constraint(struct omap_hwmod *oh, void
*cookie);
+
int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
--
1.7.7.6
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Re: [PATCH v6 0/7] ARM: OMAP2+: PM: introduce the power domains functional states
Hi Paul, On Thu, Sep 13, 2012 at 9:04 AM, Jean Pihet jean.pi...@newoldbits.com wrote: On Thu, Sep 13, 2012 at 2:34 AM, Kevin Hilman khil...@deeprootsystems.com wrote: Jean Pihet jean.pi...@newoldbits.com writes: Here is a re-spin after some comments and suggestions after review and discussions. Did you have a chance to look at the series? Regards, Jean Implement the functional states for the power domains: - unify the API to use the functional states. The new API consists of the pwrdm_set*_fpwrst and pwrdm_read*_fpwrst functions and is the API to use to control the power domains power and logic states, - reorganize the powerdomain API in internal and external parts, in powerdomain.h [1] - protect the power domain state change by a lock in the functions that read and set the powerdomains next functional state, - introduce the functional states for power domains power states and logic power states [2], and the conversion functions between the functional and internal states. The conversion functions are lightweight and generic. The power domains allowed states [3] are defined in the pwrsts and pwrsts_logic_ret fields of the struct powerdomain, - program the logic power state of power domains from the functional states, in pwrdm_set*_fpwrst - convert the OMAP2/3/4 PM code to use the updated API, - provide the power domains statistics by functional states, - provide ftrace tracepoints with the functional state, - provide error logs in critical code, which makes the development easier. I just gave this series a round of PM testing. I tested retention and off in idle suspend, with and without CPUidle on 3430/n900, 3530/Overo, 3730/OveroSTORM, 3730/Beagle-xM and 4430/Panda (though only MPU/CPU ret/off is supported for OMAP4 in mainline.) All PM tests passed with flying colors. Nice! Great! Thanks a lot Kevin for testing Jean Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP: SmartReflex: pass device dependent data via platform data
From: Jean Pihet j-pi...@ti.com
Remove the device dependent settings (cpu_is_xxx(), IP clock name)
from the driver code and pass them instead via the platform
data.
This allows a clean separation of the driver code and the platform
code.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/sr_device.c | 20
drivers/power/avs/smartreflex.c | 36 +---
include/linux/power/smartreflex.h | 19 +--
3 files changed, 46 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d033a65..549e008 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -122,6 +122,26 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void
*user)
sr_data-senn_mod = 0x1;
sr_data-senp_mod = 0x1;
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ sr_data-err_weight = OMAP3430_SR_ERRWEIGHT;
+ sr_data-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+ sr_data-accum_data = OMAP3430_SR_ACCUMDATA;
+ if (!(strcmp(sr_data-name, smartreflex_mpu_iva))) {
+ sr_data-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+ } else {
+ sr_data-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+ sr_data-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+ }
+ }
+
+ if (cpu_is_omap34xx())
+ strncpy(sr_data-sys_clk_name, sys_ck,
+ sizeof(sr_data-sys_clk_name));
+ else
+ strncpy(sr_data-sys_clk_name, sys_clkin_ck,
+ sizeof(sr_data-sys_clk_name));
+
sr_data-voltdm = voltdm_lookup(sr_dev_attr-sensor_voltdm_name);
if (IS_ERR(sr_data-voltdm)) {
pr_err(%s: Unable to get voltage domain pointer for VDD %s\n,
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 44efc6e..734493d 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -131,10 +131,7 @@ static void sr_set_clk_length(struct omap_sr *sr)
struct clk *sys_ck;
u32 sys_clk_speed;
- if (cpu_is_omap34xx())
- sys_ck = clk_get(NULL, sys_ck);
- else
- sys_ck = clk_get(NULL, sys_clkin_ck);
+ sys_ck = clk_get(NULL, sr-sys_clk_name);
if (IS_ERR(sys_ck)) {
dev_err(sr-pdev-dev, %s: unable to get sys clk\n,
@@ -168,28 +165,6 @@ static void sr_set_clk_length(struct omap_sr *sr)
}
}
-static void sr_set_regfields(struct omap_sr *sr)
-{
- /*
-* For time being these values are defined in smartreflex.h
-* and populated during init. May be they can be moved to board
-* file or pmic specific data structure. In that case these structure
-* fields will have to be populated using the pdata or pmic structure.
-*/
- if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- sr-err_weight = OMAP3430_SR_ERRWEIGHT;
- sr-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
- sr-accum_data = OMAP3430_SR_ACCUMDATA;
- if (!(strcmp(sr-name, smartreflex_mpu_iva))) {
- sr-senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
- } else {
- sr-senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
- sr-senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
- }
- }
-}
-
static void sr_start_vddautocomp(struct omap_sr *sr)
{
if (!sr_class || !(sr_class-enable) || !(sr_class-configure)) {
@@ -922,8 +897,16 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-nvalue_count = pdata-nvalue_count;
sr_info-senn_mod = pdata-senn_mod;
sr_info-senp_mod = pdata-senp_mod;
+ sr_info-err_weight = pdata-err_weight;
+ sr_info-err_maxlimit = pdata-err_maxlimit;
+ sr_info-accum_data = pdata-accum_data;
+ sr_info-senn_avgweight = pdata-senn_avgweight;
+ sr_info-senp_avgweight = pdata-senp_avgweight;
+ strncpy(sr_info-sys_clk_name, pdata-sys_clk_name,
+ sizeof(sr_info-sys_clk_name));
sr_info-autocomp_active = false;
sr_info-ip_type = pdata-ip_type;
+
sr_info-base = ioremap(mem-start, resource_size(mem));
if (!sr_info-base) {
dev_err(pdev-dev, %s: ioremap fail\n, __func__);
@@ -935,7 +918,6 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
sr_info-irq = irq-start;
sr_set_clk_length(sr_info);
- sr_set_regfields(sr_info);
list_add(sr_info-node, sr_list);
diff --git a/include/linux/power/smartreflex.h
b/include/linux/power/smartreflex.h
index 3101e62
[PATCH] ARM: OMAP: SmartReflex: fix error path in init function
From: Jean Pihet j-pi...@ti.com
Fix the error handling path in omap_sr_probe to correctly
de-allocate resources in case of problems.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
drivers/power/avs/smartreflex.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 734493d..a802f4c 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -911,7 +911,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
if (!sr_info-base) {
dev_err(pdev-dev, %s: ioremap fail\n, __func__);
ret = -ENOMEM;
- goto err_release_region;
+ goto err_free_name;
}
if (irq)
@@ -949,7 +949,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
dev_err(pdev-dev, %s: Unable to create debugfs directory\n,
__func__);
ret = PTR_ERR(sr_info-dbg_dir);
- goto err_free_name;
+ goto err_debugfs;
}
(void) debugfs_create_file(autocomp, S_IRUGO | S_IWUSR,
@@ -993,11 +993,11 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
err_debugfs:
debugfs_remove_recursive(sr_info-dbg_dir);
-err_free_name:
- kfree(sr_info-name);
err_iounmap:
list_del(sr_info-node);
iounmap(sr_info-base);
+err_free_name:
+ kfree(sr_info-name);
err_release_region:
release_mem_region(mem-start, resource_size(mem));
err_free_devinfo:
--
1.7.7.6
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Re: [PATCH] ARM: OMAP: SmartReflex: fix error path in init function
Hi!
On Fri, Sep 14, 2012 at 12:14 PM, jean.pi...@newoldbits.com wrote:
From: Jean Pihet j-pi...@ti.com
Fix the error handling path in omap_sr_probe to correctly
de-allocate resources in case of problems.
Please note that this patch applies on top of 'ARM: OMAP: SmartReflex:
pass device dependent data via platform data' [1].
[1] http://marc.info/?l=linux-omapm=134761557609931w=2
Regards,
Jean
Signed-off-by: Jean Pihet j-pi...@ti.com
---
drivers/power/avs/smartreflex.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 734493d..a802f4c 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -911,7 +911,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
if (!sr_info-base) {
dev_err(pdev-dev, %s: ioremap fail\n, __func__);
ret = -ENOMEM;
- goto err_release_region;
+ goto err_free_name;
}
if (irq)
@@ -949,7 +949,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
dev_err(pdev-dev, %s: Unable to create debugfs
directory\n,
__func__);
ret = PTR_ERR(sr_info-dbg_dir);
- goto err_free_name;
+ goto err_debugfs;
}
(void) debugfs_create_file(autocomp, S_IRUGO | S_IWUSR,
@@ -993,11 +993,11 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
err_debugfs:
debugfs_remove_recursive(sr_info-dbg_dir);
-err_free_name:
- kfree(sr_info-name);
err_iounmap:
list_del(sr_info-node);
iounmap(sr_info-base);
+err_free_name:
+ kfree(sr_info-name);
err_release_region:
release_mem_region(mem-start, resource_size(mem));
err_free_devinfo:
--
1.7.7.6
--
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Re: [PATCH v6 0/7] ARM: OMAP2+: PM: introduce the power domains functional states
On Thu, Sep 13, 2012 at 2:34 AM, Kevin Hilman khil...@deeprootsystems.com wrote: Jean Pihet jean.pi...@newoldbits.com writes: Here is a re-spin after some comments and suggestions after review and discussions. Implement the functional states for the power domains: - unify the API to use the functional states. The new API consists of the pwrdm_set*_fpwrst and pwrdm_read*_fpwrst functions and is the API to use to control the power domains power and logic states, - reorganize the powerdomain API in internal and external parts, in powerdomain.h [1] - protect the power domain state change by a lock in the functions that read and set the powerdomains next functional state, - introduce the functional states for power domains power states and logic power states [2], and the conversion functions between the functional and internal states. The conversion functions are lightweight and generic. The power domains allowed states [3] are defined in the pwrsts and pwrsts_logic_ret fields of the struct powerdomain, - program the logic power state of power domains from the functional states, in pwrdm_set*_fpwrst - convert the OMAP2/3/4 PM code to use the updated API, - provide the power domains statistics by functional states, - provide ftrace tracepoints with the functional state, - provide error logs in critical code, which makes the development easier. I just gave this series a round of PM testing. I tested retention and off in idle suspend, with and without CPUidle on 3430/n900, 3530/Overo, 3730/OveroSTORM, 3730/Beagle-xM and 4430/Panda (though only MPU/CPU ret/off is supported for OMAP4 in mainline.) All PM tests passed with flying colors. Nice! Great! Thanks a lot Kevin for testing Jean Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/7] ARM: OMAP2+: PM debug: trace the functional power domains states
HI Kevin,
On Thu, Sep 13, 2012 at 1:47 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Jean Pihet jean.pi...@newoldbits.com writes:
Trace the power domain transitions using the functional power states,
which include the power and logic states.
Just to be clear, this means that a trace will only contain functional
power state changes, not logical ones, correct?
Correct! The trace reports functional states, while pr_err and
pr_debug statements (added by patch 6/7) are present for hardcore
debugging on the functional and internal states.
While at it, fix the trace in the case a power domain did not hit
the desired state, as reported by Paul Walmsley.
What was broken here? needs a bit more description.
Ok will do
To me it sounds
like a fix that should be a separate patch.
I kept the fix in this patch since it matches $SUBJECT. Can be split
if needed though.
Thanks for reviewing!
Jean
Reported-by: Paul Walmsley p...@pwsan.com
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 23 +--
1 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 267241f..2277ad3 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -144,7 +144,7 @@ static void _update_logic_membank_counters(struct
powerdomain *pwrdm)
static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
{
- int prev, state, trace_state = 0;
+ int prev, next, state, trace_state;
if (pwrdm == NULL)
return -EINVAL;
@@ -165,10 +165,10 @@ static int _pwrdm_state_switch(struct powerdomain
*pwrdm, int flag)
* If the power domain did not hit the desired state,
* generate a trace event with both the desired and hit states
*/
- if (state != prev) {
+ next = pwrdm_read_next_fpwrst(pwrdm);
+ if (next != prev) {
trace_state = (PWRDM_TRACE_STATES_FLAG |
-((state OMAP_POWERSTATE_MASK) 8) |
-((prev OMAP_POWERSTATE_MASK) 0));
+(next 8) | (prev 0));
trace_power_domain_target(pwrdm-name, trace_state,
smp_processor_id());
}
@@ -723,6 +723,10 @@ int pwrdm_set_fpwrst(struct powerdomain *pwrdm, enum
pwrdm_func_state fpwrst)
}
}
+ /* Trace the pwrdm desired target state */
+ trace_power_domain_target(pwrdm-name, next_fpwrst,
+ smp_processor_id());
Use of smp_processor_id() here will require the same care as pointed out
by Roger Quadros in [PATCH] perf: Use raw_smp_processor_id insted of
smp_processor_id.
Kevin
if (logic != pwrdm_read_logic_retst(pwrdm))
pwrdm_set_logic_retst(pwrdm, logic);
@@ -776,6 +780,10 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
spin_lock_irqsave(pwrdm-lock, flags);
+ /* Trace the pwrdm desired target state */
+ trace_power_domain_target(pwrdm-name, fpwrst,
+ smp_processor_id());
+
ret = pwrdm_set_logic_retst(pwrdm, logic);
if (ret)
pr_err(%s: unable to set logic state %0x of powerdomain:
%s\n,
@@ -821,13 +829,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8
pwrst)
pr_debug(powerdomain: setting next powerstate for %s to %0x\n,
pwrdm-name, pwrst);
- if (arch_pwrdm arch_pwrdm-pwrdm_set_next_pwrst) {
- /* Trace the pwrdm desired target state */
- trace_power_domain_target(pwrdm-name, pwrst,
- smp_processor_id());
- /* Program the pwrdm desired target state */
+ if (arch_pwrdm arch_pwrdm-pwrdm_set_next_pwrst)
ret = arch_pwrdm-pwrdm_set_next_pwrst(pwrdm, pwrst);
- }
return ret;
}
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Re: [PATCH 7/7] ARM: OMAP2+: PM: reorganize the powerdomain API in public and private parts
On Thu, Sep 13, 2012 at 2:11 AM, Kevin Hilman khil...@deeprootsystems.com wrote: Jean Pihet jean.pi...@newoldbits.com writes: The newly added code for functional power states re-defines the API to query and control the power domains settings. The API is now split in the following parts in powerdomain.h: - the public or external API, to be used by external PM components: cpuidle, suspend, pm, clock* etc. - the private or internal API, to be used by the low level PM code only: powerdomain*, pm-debug, hwmod, voltage, clockdomain. The function omap_set_pwrdm_state is not used anymore and so is removed. No functional change is introduced by this patch. Note: the API reorganization in a public and private header files is not part of this patch, this comes as a subsequent clean-up patch series. Signed-off-by: Jean Pihet j-pi...@ti.com In addition to reorganizing the API, I suspect there are a handful of out-of-tree hacks, er, users, that will are using the internal state names, as well as the functions that should now only be internal. The API clean-up series (planned after this one is in the queue) will sort out the public vs private APIs using different header files and static functions. As part of the subsequent cleanup series, it would it make sense to add a '_' prefix to the internal names as well to catch unintentional use of internal APIs? Sure. Kevin Thanks, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/7] ARM: OMAP2+: PM debug: trace the functional power domains states
On Thu, Sep 13, 2012 at 1:47 AM, Kevin Hilman khil...@deeprootsystems.com wrote: Use of smp_processor_id() here will require the same care as pointed out by Roger Quadros in [PATCH] perf: Use raw_smp_processor_id insted of smp_processor_id. BTW it looks like get_cpu and put_cpu is the way to go, as pointed out by Russell. Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 0/7] ARM: OMAP2+: PM: introduce the power domains functional states
Here is a re-spin after some comments and suggestions after review and discussions. Implement the functional states for the power domains: - unify the API to use the functional states. The new API consists of the pwrdm_set*_fpwrst and pwrdm_read*_fpwrst functions and is the API to use to control the power domains power and logic states, - reorganize the powerdomain API in internal and external parts, in powerdomain.h [1] - protect the power domain state change by a lock in the functions that read and set the powerdomains next functional state, - introduce the functional states for power domains power states and logic power states [2], and the conversion functions between the functional and internal states. The conversion functions are lightweight and generic. The power domains allowed states [3] are defined in the pwrsts and pwrsts_logic_ret fields of the struct powerdomain, - program the logic power state of power domains from the functional states, in pwrdm_set*_fpwrst - convert the OMAP2/3/4 PM code to use the updated API, - provide the power domains statistics by functional states, - provide ftrace tracepoints with the functional state, - provide error logs in critical code, which makes the development easier. Notes: [1] the physical split of internal and external APIs into different header files is not part of this series, it comes as a separate patch set. [2] the abstraction for functional power states provides a generic way of controlling the power domains states across all OMAP chipsets and revisions. The users of the functional power states are (1) the OMAP PM components: cpuidle, suspend, pm, clock* and (2) the per-device PM QoS constraints and the generic power domain frameworks. All those users require a generic abstraction of the power domain states while the low level power domain code has the knowledge of the internal settings (power, logic... states). [3] About the power domains allowed states: Power domains have varied capabilities, as defined by the value of the pwrsts and pwrsts_logic_ret fields of the powerdomain struct. When reading or setting a low power state such as OFF/RET, a specific requested state may not be supported on the given power domain. In the states conversion functions a power or logic state is first looked for in the lower power states in order to maximize the power savings, then if not found in the higher power states. An iteration function is used, as suggested by Rajendra Nayak rna...@ti.com This functionality brings consistency in the functional power states core code and acts as a guard against hardware implementations discrepancies, e.g. some power domains only support the RET logic state although reading the logic state registers (previous, current and next) always returns OFF. The DSS power domain on OMAP3 is an example. Based on mainline kernel 3.6.0-rc4. Tested on OMAP3 Beagleboard, with suspend and cpuidle in RET and OFF modes. History: v6: - rework to a lighter and generic conversion mechanism between the functional and the internal states (static internal functions are defined instead of using the pwrdm fops function pointers), - the functional power states API now has a function to set the next power state (pwrdm_set_next_fpwrst) and a function to program (i.e. set, apply the state and wait for completion) the power state (pwrdm_set_fpwrst), - When attempting a low power state such as OFF/RET, a specific requested state may not be supported on the given power domain. In the states conversion functions a power state is first looked for in the lower power states in order to maximize the power savings, then if not found in the higher power states. Only allowed states are returned by the conversion functions, as defined by the value of the pwrsts and pwrsts_logic_ret fields of the powerdomain struct. - added more error logging: check for NULL in pwrdm, better error messages using pr_err_ratelimited etc. v5: - complete rework after review and suggestions, - improved locking on next state read/write; spinlock instead of mutex - added more error logging in critical code, v4: - reworked the code after internal review and testing with OMAP34 device OFF, - fixed the tracepoints generation code, - introduce a function that returns power domains achievable functional states, in order to return a valid state for power domains that only support some of the power states. Although it has been tested OK the code is in RFC state. v3: - fix a bug in OMAP3 cpuidle which prevented the IO wake-ups in PER v2: - add the logic power states, - provide the power domains statistics by functional states v1: - initial implementation, in RFC state Jean Pihet (6): ARM: OMAP2+: PM: introduce power domains functional states ARM: OMAP2+: PM: add a lock to protect the powerdomains next state ARM: OMAP2+: PM
[PATCH 1/7] ARM: OMAP2+: PM: introduce power domains functional states
Introduce the functional states for power domains, which include
the power states and the logic states.
This patch provides the API functions to set and read the power
domains functional state and internal functions to convert between
the functional (i.e. logical) and the internal (or registers) values.
In the new API only the functions pwrdm_set_next_fpwrst and
pwrdm_set_next_fpwrst shall be used to change a power domain
target state, along with the associated PWRDM_FUNC_* and
PWRDM_LOGIC_* macros as the state parameters.
Note about the power domains allowed states:
Power domains have varied capabilities, as defined by the value of
the pwrsts and pwrsts_logic_ret fields of the powerdomain struct.
When reading or setting a low power state such as OFF/RET, a specific
requested state may not be supported on the given power domain.
In the states conversion functions a power or logic state is first
looked for in the lower power states in order to maximize the power
savings, then if not found in the higher power states. An iteration
function is used, as suggested by Rajendra Nayak rna...@ti.com
This functionality brings consistency in the functional power states
core code and acts as a guard against hardware implementations
discrepancies, e.g. some power domains only support the RET logic
state although reading the logic state registers (previous, current
and next) always returns OFF. The DSS power domain on OMAP3 is an
example.
Signed-off-by: Jean Pihet j-pi...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 374 -
arch/arm/mach-omap2/powerdomain.h | 32 +++-
2 files changed, 396 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 69b36e1..18c21fa 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1,7 +1,7 @@
/*
* OMAP powerdomain control
*
- * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011-2012 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
@@ -128,14 +128,14 @@ static void _update_logic_membank_counters(struct
powerdomain *pwrdm)
prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm);
if ((pwrdm-pwrsts_logic_ret == PWRSTS_OFF_RET)
- (prev_logic_pwrst == PWRDM_POWER_OFF))
+ (prev_logic_pwrst == PWRDM_LOGIC_MEM_PWRST_OFF))
pwrdm-ret_logic_off_counter++;
for (i = 0; i pwrdm-banks; i++) {
prev_mem_pwrst = pwrdm_read_prev_mem_pwrst(pwrdm, i);
if ((pwrdm-pwrsts_mem_ret[i] == PWRSTS_OFF_RET)
- (prev_mem_pwrst == PWRDM_POWER_OFF))
+ (prev_mem_pwrst == PWRDM_LOGIC_MEM_PWRST_OFF))
pwrdm-ret_mem_off_counter[i]++;
}
}
@@ -199,6 +199,201 @@ static int _pwrdm_post_transition_cb(struct powerdomain
*pwrdm, void *unused)
return 0;
}
+/**
+ * Search down then up for a valid state from a list of allowed states.
+ * Used by states conversion functions (_pwrdm_fpwrst_to_*) to look for
+ * allowed power and logic states for a powerdomain.
+ *
+ * @pwrsts: list of allowed states, defined as a bitmask
+ * @pwrst: initial state to be used as a starting point
+ * @min: minimum (i.e. lowest consumption) allowed state
+ * @max: maximum (i.e. highest consumption) allowed state
+ *
+ * Returns the matching allowed state.
+ */
+static inline int _match_pwrst(u32 pwrsts, int pwrst, int min, int max)
+{
+ int found = 1, new_pwrst = pwrst;
+
+ /*
+* If the power domain does not allow any state programmation
+* return the max state which is always allowed
+*/
+ if (!pwrsts)
+ return max;
+
+ /*
+* Search lower: if the requested state is not supported
+* try the lower states, stopping at the minimum allowed
+* state
+*/
+ while (!(pwrsts (1 new_pwrst))) {
+ if (new_pwrst = min) {
+ found = 0;
+ break;
+ }
+ new_pwrst--;
+ }
+
+ /*
+* Search higher: if no lower state found fallback to the higher
+* states, stopping at the maximum allowed state
+*/
+ if (!found) {
+ new_pwrst = pwrst;
+ while (!(pwrsts (1 new_pwrst))) {
+ if (new_pwrst = max) {
+ new_pwrst = max;
+ break;
+ }
+ new_pwrst++;
+ }
+ }
+
+ return new_pwrst;
+}
+
+/**
+ * _pwrdm_fpwrst_to_pwrst - Convert functional (i.e. logical) to
+ * internal (i.e. registers) values for the power domains states.
+ * @struct powerdomain * to convert the values
[PATCH 2/7] ARM: OMAP2+: PM: add a lock to protect the powerdomains next state
pwrdm_set_fpwrst, pwrdm_set_next_fpwrst and pwrdm_read_next_fpwrst
are intented to be the only API to program and request the next
state of a power domain.
This patch protects the power domain next state settings and structs
from concurrent accesses by the use of a lock.
A spinlock is used since the API functions can be called from
atomic context (.i.e) either from cpuidle path or suspend path.
[ambr...@ti.com: reported the atomic context issue and suggested
to replace the initial mutex with a spinlock]
Signed-off-by: Jean Pihet j-pi...@ti.com
Reported-by: Ambresh K ambr...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 40
arch/arm/mach-omap2/powerdomain.h |3 ++
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 18c21fa..f4b219f 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
INIT_LIST_HEAD(pwrdm-voltdm_node);
voltdm_add_pwrdm(voltdm, pwrdm);
+ spin_lock_init(pwrdm-lock);
list_add(pwrdm-node, pwrdm_list);
/* Initialize the powerdomain's state counter */
@@ -394,6 +395,22 @@ static int _pwrdm_pwrst_to_fpwrst(struct powerdomain
*pwrdm, u8 pwrst, u8 logic)
}
+/**
+ * _pwrdm_read_next_fpwrst - get next powerdomain functional power state
+ * @pwrdm: struct powerdomain * to get power state
+ *
+ * Return the powerdomain @pwrdm's next functional power state.
+ * Returns -EINVAL if the powerdomain pointer is null or returns
+ * the next power state upon success.
+ */
+static int _pwrdm_read_next_fpwrst(struct powerdomain *pwrdm)
+{
+ int next_pwrst = pwrdm_read_next_pwrst(pwrdm);
+ int next_logic = pwrdm_read_logic_retst(pwrdm);
+
+ return _pwrdm_pwrst_to_fpwrst(pwrdm, next_pwrst, next_logic);
+}
+
/* Public functions */
/**
@@ -677,6 +694,7 @@ int pwrdm_set_fpwrst(struct powerdomain *pwrdm, enum
pwrdm_func_state fpwrst)
int pwrst = _pwrdm_fpwrst_to_pwrst(pwrdm, fpwrst);
int logic = _pwrdm_fpwrst_to_logic_pwrst(pwrdm, fpwrst);
int sleep_switch = -1, ret = 0, hwsup = 0;
+ unsigned long flags;
if (!pwrdm || IS_ERR(pwrdm) || (pwrst 0) || (logic 0)) {
pr_debug(%s: invalid params: pwrdm=%p, fpwrst=%0x\n,
@@ -687,9 +705,11 @@ int pwrdm_set_fpwrst(struct powerdomain *pwrdm, enum
pwrdm_func_state fpwrst)
pr_debug(%s: set fpwrst %0x to pwrdm %s\n,
__func__, fpwrst, pwrdm-name);
- next_fpwrst = pwrdm_read_next_fpwrst(pwrdm);
+ spin_lock_irqsave(pwrdm-lock, flags);
+
+ next_fpwrst = _pwrdm_read_next_fpwrst(pwrdm);
if (next_fpwrst == fpwrst)
- return ret;
+ goto out;
curr_pwrst = pwrdm_read_pwrst(pwrdm);
if (curr_pwrst PWRDM_POWER_ON) {
@@ -725,6 +745,8 @@ int pwrdm_set_fpwrst(struct powerdomain *pwrdm, enum
pwrdm_func_state fpwrst)
break;
}
+out:
+ spin_unlock_irqrestore(pwrdm-lock, flags);
return ret;
}
@@ -741,6 +763,7 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
int pwrst = _pwrdm_fpwrst_to_pwrst(pwrdm, fpwrst);
int logic = _pwrdm_fpwrst_to_logic_pwrst(pwrdm, fpwrst);
int ret = 0;
+ unsigned long flags;
if (!pwrdm || IS_ERR(pwrdm) || (pwrst 0) || (logic 0)) {
pr_debug(%s: invalid params: pwrdm=%p, fpwrst=%0x\n,
@@ -751,6 +774,8 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
pr_debug(%s: set fpwrst %0x to pwrdm %s\n,
__func__, fpwrst, pwrdm-name);
+ spin_lock_irqsave(pwrdm-lock, flags);
+
ret = pwrdm_set_logic_retst(pwrdm, logic);
if (ret)
pr_err(%s: unable to set logic state %0x of powerdomain: %s\n,
@@ -761,6 +786,7 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
pr_err(%s: unable to set power state %0x of powerdomain: %s\n,
__func__, pwrst, pwrdm-name);
+ spin_unlock_irqrestore(pwrdm-lock, flags);
return ret;
};
@@ -837,10 +863,14 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
*/
int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm)
{
- int next_pwrst = pwrdm_read_next_pwrst(pwrdm);
- int next_logic = pwrdm_read_logic_retst(pwrdm);
+ int ret;
+ unsigned long flags;
- return _pwrdm_pwrst_to_fpwrst(pwrdm, next_pwrst, next_logic);
+ spin_lock_irqsave(pwrdm-lock, flags);
+ ret = _pwrdm_read_next_fpwrst(pwrdm);
+ spin_unlock_irqrestore(pwrdm-lock, flags);
+
+ return ret;
}
/**
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index aa5de4f..c3dc363 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -17,6 +17,7 @@
#include linux/types.h
#include linux/list.h
[PATCH 4/7] ARM: OMAP2+: PM: use power domain functional state in stats counters
The PM code uses some counters to keep track of the power domains
transitions, in order to provide the information to drivers (in
pwrdm_get_context_loss_count) and to expose the information to
sysfs for debug purpose.
This patch provides the information for each functional state.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/pm-debug.c| 15 ---
arch/arm/mach-omap2/powerdomain.c | 12 ++--
arch/arm/mach-omap2/powerdomain.h |4 ++--
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 814bcd9..8eaa3f2 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -53,9 +53,10 @@ enum {
DEBUG_FILE_TIMERS,
};
-static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
+static const char pwrdm_state_names[][PWRDM_MAX_FUNC_PWRSTS] = {
OFF,
- RET,
+ OSWR,
+ CSWR,
INA,
ON
};
@@ -102,13 +103,13 @@ static int pwrdm_dbg_show_counter(struct powerdomain
*pwrdm, void *user)
strncmp(pwrdm-name, dpll, 4) == 0)
return 0;
- if (pwrdm-state != pwrdm_read_pwrst(pwrdm))
+ if (pwrdm-state != pwrdm_read_fpwrst(pwrdm))
printk(KERN_ERR pwrdm state mismatch(%s) %d != %d\n,
- pwrdm-name, pwrdm-state, pwrdm_read_pwrst(pwrdm));
+ pwrdm-name, pwrdm-state, pwrdm_read_fpwrst(pwrdm));
seq_printf(s, %s (%s), pwrdm-name,
pwrdm_state_names[pwrdm-state]);
- for (i = 0; i PWRDM_MAX_PWRSTS; i++)
+ for (i = 0; i PWRDM_MAX_FUNC_PWRSTS; i++)
seq_printf(s, ,%s:%d, pwrdm_state_names[i],
pwrdm-state_counter[i]);
@@ -137,7 +138,7 @@ static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm,
void *user)
seq_printf(s, %s (%s), pwrdm-name,
pwrdm_state_names[pwrdm-state]);
- for (i = 0; i 4; i++)
+ for (i = 0; i PWRDM_MAX_FUNC_PWRSTS; i++)
seq_printf(s, ,%s:%lld, pwrdm_state_names[i],
pwrdm-state_timer[i]);
@@ -211,7 +212,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm,
void *dir)
t = sched_clock();
- for (i = 0; i 4; i++)
+ for (i = 0; i PWRDM_MAX_FUNC_PWRSTS; i++)
pwrdm-state_timer[i] = 0;
pwrdm-timer = t;
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 82ae9e9..267241f 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -106,7 +106,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
list_add(pwrdm-node, pwrdm_list);
/* Initialize the powerdomain's state counter */
- for (i = 0; i PWRDM_MAX_PWRSTS; i++)
+ for (i = 0; i PWRDM_MAX_FUNC_PWRSTS; i++)
pwrdm-state_counter[i] = 0;
pwrdm-ret_logic_off_counter = 0;
@@ -114,7 +114,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
pwrdm-ret_mem_off_counter[i] = 0;
pwrdm_wait_transition(pwrdm);
- pwrdm-state = pwrdm_read_pwrst(pwrdm);
+ pwrdm-state = pwrdm_read_fpwrst(pwrdm);
pwrdm-state_counter[pwrdm-state] = 1;
pr_debug(powerdomain: registered %s\n, pwrdm-name);
@@ -149,17 +149,17 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
if (pwrdm == NULL)
return -EINVAL;
- state = pwrdm_read_pwrst(pwrdm);
+ state = pwrdm_read_fpwrst(pwrdm);
switch (flag) {
case PWRDM_STATE_NOW:
prev = pwrdm-state;
break;
case PWRDM_STATE_PREV:
- prev = pwrdm_read_prev_pwrst(pwrdm);
+ prev = pwrdm_read_prev_fpwrst(pwrdm);
if (pwrdm-state != prev)
pwrdm-state_counter[prev]++;
- if (prev == PWRDM_POWER_RET)
+ if (prev == PWRDM_FUNC_PWRST_OSWR)
_update_logic_membank_counters(pwrdm);
/*
* If the power domain did not hit the desired state,
@@ -1414,7 +1414,7 @@ int pwrdm_get_context_loss_count(struct powerdomain
*pwrdm)
return -ENODEV;
}
- count = pwrdm-state_counter[PWRDM_POWER_OFF];
+ count = pwrdm-state_counter[PWRDM_FUNC_PWRST_OFF];
count += pwrdm-ret_logic_off_counter;
for (i = 0; i pwrdm-banks; i++)
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index c3dc363..a29caec 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -146,7 +146,7 @@ struct powerdomain {
struct list_head voltdm_node;
spinlock_t lock;
int state;
- unsigned state_counter[PWRDM_MAX_PWRSTS];
+ unsigned state_counter[PWRDM_MAX_FUNC_PWRSTS];
unsigned ret_logic_off_counter
[PATCH 5/7] ARM: OMAP2+: PM debug: trace the functional power domains states
Trace the power domain transitions using the functional power states,
which include the power and logic states.
While at it, fix the trace in the case a power domain did not hit
the desired state, as reported by Paul Walmsley.
Reported-by: Paul Walmsley p...@pwsan.com
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 23 +--
1 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 267241f..2277ad3 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -144,7 +144,7 @@ static void _update_logic_membank_counters(struct
powerdomain *pwrdm)
static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
{
- int prev, state, trace_state = 0;
+ int prev, next, state, trace_state;
if (pwrdm == NULL)
return -EINVAL;
@@ -165,10 +165,10 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
* If the power domain did not hit the desired state,
* generate a trace event with both the desired and hit states
*/
- if (state != prev) {
+ next = pwrdm_read_next_fpwrst(pwrdm);
+ if (next != prev) {
trace_state = (PWRDM_TRACE_STATES_FLAG |
- ((state OMAP_POWERSTATE_MASK) 8) |
- ((prev OMAP_POWERSTATE_MASK) 0));
+ (next 8) | (prev 0));
trace_power_domain_target(pwrdm-name, trace_state,
smp_processor_id());
}
@@ -723,6 +723,10 @@ int pwrdm_set_fpwrst(struct powerdomain *pwrdm, enum
pwrdm_func_state fpwrst)
}
}
+ /* Trace the pwrdm desired target state */
+ trace_power_domain_target(pwrdm-name, next_fpwrst,
+ smp_processor_id());
+
if (logic != pwrdm_read_logic_retst(pwrdm))
pwrdm_set_logic_retst(pwrdm, logic);
@@ -776,6 +780,10 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
spin_lock_irqsave(pwrdm-lock, flags);
+ /* Trace the pwrdm desired target state */
+ trace_power_domain_target(pwrdm-name, fpwrst,
+ smp_processor_id());
+
ret = pwrdm_set_logic_retst(pwrdm, logic);
if (ret)
pr_err(%s: unable to set logic state %0x of powerdomain: %s\n,
@@ -821,13 +829,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8
pwrst)
pr_debug(powerdomain: setting next powerstate for %s to %0x\n,
pwrdm-name, pwrst);
- if (arch_pwrdm arch_pwrdm-pwrdm_set_next_pwrst) {
- /* Trace the pwrdm desired target state */
- trace_power_domain_target(pwrdm-name, pwrst,
- smp_processor_id());
- /* Program the pwrdm desired target state */
+ if (arch_pwrdm arch_pwrdm-pwrdm_set_next_pwrst)
ret = arch_pwrdm-pwrdm_set_next_pwrst(pwrdm, pwrst);
- }
return ret;
}
--
1.7.7.6
--
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[PATCH 3/7] ARM: OMAP2+: PM: use the functional power states API
Use the functional power states as the API to control power
domains:
- use the PWRDM_FUNC_PWRST_* and PWRDM_LOGIC_MEM_PWRST_*
macros for the power states and logic settings,
- the function pwrdm_set_next_fpwrst, which controls
the power domains next power and logic settings, shall
be used instead of pwrdm_set_next_pwrst to program the
power domains next states,
- the function pwrdm_set_fpwrst, which programs the power
domains power and logic settings, shall be used instead
of omap_set_pwrdm_state.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 58 +++---
arch/arm/mach-omap2/cpuidle44xx.c | 24 --
arch/arm/mach-omap2/omap-hotplug.c|2 +-
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 39 ---
arch/arm/mach-omap2/pm24xx.c | 14 ++---
arch/arm/mach-omap2/pm34xx.c | 75 +++--
arch/arm/mach-omap2/pm44xx.c | 24 --
arch/arm/mach-omap2/powerdomain.c |2 +-
8 files changed, 114 insertions(+), 124 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index f2a49a4..4ca37d2 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -44,32 +44,32 @@ struct omap3_idle_statedata {
static struct omap3_idle_statedata omap3_idle_data[] = {
{
- .mpu_state = PWRDM_POWER_ON,
- .core_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_FUNC_PWRST_ON,
+ .core_state = PWRDM_FUNC_PWRST_ON,
},
{
- .mpu_state = PWRDM_POWER_ON,
- .core_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_FUNC_PWRST_ON,
+ .core_state = PWRDM_FUNC_PWRST_ON,
},
{
- .mpu_state = PWRDM_POWER_RET,
- .core_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_FUNC_PWRST_CSWR,
+ .core_state = PWRDM_FUNC_PWRST_ON,
},
{
- .mpu_state = PWRDM_POWER_OFF,
- .core_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_FUNC_PWRST_OFF,
+ .core_state = PWRDM_FUNC_PWRST_ON,
},
{
- .mpu_state = PWRDM_POWER_RET,
- .core_state = PWRDM_POWER_RET,
+ .mpu_state = PWRDM_FUNC_PWRST_CSWR,
+ .core_state = PWRDM_FUNC_PWRST_CSWR,
},
{
- .mpu_state = PWRDM_POWER_OFF,
- .core_state = PWRDM_POWER_RET,
+ .mpu_state = PWRDM_FUNC_PWRST_OFF,
+ .core_state = PWRDM_FUNC_PWRST_CSWR,
},
{
- .mpu_state = PWRDM_POWER_OFF,
- .core_state = PWRDM_POWER_OFF,
+ .mpu_state = PWRDM_FUNC_PWRST_OFF,
+ .core_state = PWRDM_FUNC_PWRST_OFF,
},
};
@@ -84,8 +84,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
local_fiq_disable();
- pwrdm_set_next_pwrst(mpu_pd, mpu_state);
- pwrdm_set_next_pwrst(core_pd, core_state);
+ pwrdm_set_next_fpwrst(mpu_pd, mpu_state);
+ pwrdm_set_next_fpwrst(core_pd, core_state);
if (omap_irq_pending() || need_resched())
goto return_sleep_time;
@@ -100,7 +100,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
* Call idle CPU PM enter notifier chain so that
* VFP context is saved.
*/
- if (mpu_state == PWRDM_POWER_OFF)
+ if (mpu_state == PWRDM_FUNC_PWRST_OFF)
cpu_pm_enter();
/* Execute ARM wfi */
@@ -110,7 +110,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
* Call idle CPU PM enter notifier chain to restore
* VFP context.
*/
- if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
+ if (pwrdm_read_prev_fpwrst(mpu_pd) == PWRDM_FUNC_PWRST_OFF)
cpu_pm_exit();
/* Re-allow idle for C1 */
@@ -159,20 +159,20 @@ static int next_valid_state(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
struct omap3_idle_statedata *cx = omap3_idle_data[index];
- u32 mpu_deepest_state = PWRDM_POWER_RET;
- u32 core_deepest_state = PWRDM_POWER_RET;
+ u32 mpu_deepest_state = PWRDM_FUNC_PWRST_CSWR;
+ u32 core_deepest_state = PWRDM_FUNC_PWRST_CSWR;
int idx;
int next_index = 0; /* C1 is the default value */
if (enable_off_mode) {
- mpu_deepest_state = PWRDM_POWER_OFF;
+ mpu_deepest_state = PWRDM_FUNC_PWRST_OFF;
/*
* Erratum i583: valable for ES rev Es1.2 on 3630.
* CORE OFF mode is not supported in a stable form, restrict
* instead the CORE state to RET.
*/
if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583
[PATCH 6/7] ARM: OMAP2+: powerdomain: add error logs
From: Nishanth Menon n...@ti.com
Silent failure makes debug hard. So, provide rate limited error
messages in functional and oft-used code to prevent spam
when something goes wrong.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 177 +++--
1 files changed, 130 insertions(+), 47 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 2277ad3..37dfabf 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,6 +19,7 @@
#include linux/list.h
#include linux/errno.h
#include linux/string.h
+#include linux/ratelimit.h
#include trace/events/power.h
#include cm2xxx_3xxx.h
@@ -146,8 +147,10 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
int prev, next, state, trace_state;
- if (pwrdm == NULL)
+ if (!pwrdm) {
+ pr_err_ratelimited(%s: NULL pwrdm\n, __func__);
return -EINVAL;
+ }
state = pwrdm_read_fpwrst(pwrdm);
@@ -174,6 +177,8 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
}
break;
default:
+ pr_err_ratelimited(%s: powerdomain %s: bad flag %0x\n,
+ __func__, pwrdm-name, flag);
return -EINVAL;
}
@@ -385,6 +390,8 @@ static int _pwrdm_pwrst_to_fpwrst(struct powerdomain
*pwrdm, u8 pwrst, u8 logic)
ret = PWRDM_FUNC_PWRST_OFF;
break;
default:
+ pr_err_ratelimited(%s: powerdomain %s: bad pwrst %0x\n,
+ __func__, pwrdm-name, pwrst);
ret = -EINVAL;
}
@@ -697,8 +704,8 @@ int pwrdm_set_fpwrst(struct powerdomain *pwrdm, enum
pwrdm_func_state fpwrst)
unsigned long flags;
if (!pwrdm || IS_ERR(pwrdm) || (pwrst 0) || (logic 0)) {
- pr_debug(%s: invalid params: pwrdm=%p, fpwrst=%0x\n,
-__func__, pwrdm, fpwrst);
+ pr_err_ratelimited(%s: invalid params: pwrdm=%p, fpwrst=%0x\n,
+ __func__, pwrdm, fpwrst);
return -EINVAL;
}
@@ -727,13 +734,17 @@ int pwrdm_set_fpwrst(struct powerdomain *pwrdm, enum
pwrdm_func_state fpwrst)
trace_power_domain_target(pwrdm-name, next_fpwrst,
smp_processor_id());
- if (logic != pwrdm_read_logic_retst(pwrdm))
- pwrdm_set_logic_retst(pwrdm, logic);
+ if (logic != pwrdm_read_logic_retst(pwrdm)) {
+ ret = pwrdm_set_logic_retst(pwrdm, logic);
+ if (ret)
+ pr_err_ratelimited(%s: unable to set logic state %0x
of powerdomain %s, ret=%d\n,
+ __func__, logic, pwrdm-name, ret);
+ }
ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
if (ret)
- pr_err(%s: unable to set power state of powerdomain: %s\n,
- __func__, pwrdm-name);
+ pr_err_ratelimited(%s: unable to set power state %0x of
powerdomain %s, ret=%d\n,
+ __func__, pwrst, pwrdm-name, ret);
switch (sleep_switch) {
case FORCEWAKEUP_SWITCH:
@@ -770,8 +781,8 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
unsigned long flags;
if (!pwrdm || IS_ERR(pwrdm) || (pwrst 0) || (logic 0)) {
- pr_debug(%s: invalid params: pwrdm=%p, fpwrst=%0x\n,
-__func__, pwrdm, fpwrst);
+ pr_err_ratelimited(%s: invalid params: pwrdm=%p, fpwrst=%0x\n,
+ __func__, pwrdm, fpwrst);
return -EINVAL;
}
@@ -786,13 +797,13 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
ret = pwrdm_set_logic_retst(pwrdm, logic);
if (ret)
- pr_err(%s: unable to set logic state %0x of powerdomain: %s\n,
- __func__, logic, pwrdm-name);
+ pr_err_ratelimited(%s: unable to set logic state %0x of
powerdomain %s, ret=%d\n,
+ __func__, logic, pwrdm-name, ret);
ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
if (ret)
- pr_err(%s: unable to set power state %0x of powerdomain: %s\n,
- __func__, pwrst, pwrdm-name);
+ pr_err_ratelimited(%s: unable to set power state %0x of
powerdomain %s, ret=%d\n,
+ __func__, pwrst, pwrdm-name, ret);
spin_unlock_irqrestore(pwrdm-lock, flags);
return ret;
@@ -813,8 +824,10 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8
pwrst)
{
int ret = -EINVAL;
- if (!pwrdm)
+ if (!pwrdm) {
+ pr_err_ratelimited(%s: NULL pwrdm\n, __func__);
return -EINVAL;
+ }
/*
*
[PATCH 7/7] ARM: OMAP2+: PM: reorganize the powerdomain API in public and private parts
The newly added code for functional power states re-defines the
API to query and control the power domains settings.
The API is now split in the following parts in powerdomain.h:
- the public or external API, to be used by external PM components:
cpuidle, suspend, pm, clock* etc.
- the private or internal API, to be used by the low level PM code
only: powerdomain*, pm-debug, hwmod, voltage, clockdomain.
The function omap_set_pwrdm_state is not used anymore and so is
removed.
No functional change is introduced by this patch.
Note: the API reorganization in a public and private header files
is not part of this patch, this comes as a subsequent clean-up
patch series.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/pm.c | 62
arch/arm/mach-omap2/pm.h |1 -
arch/arm/mach-omap2/powerdomain.h | 112 +
3 files changed, 63 insertions(+), 112 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5ced..dfe702b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -74,10 +74,6 @@ static void __init omap2_init_processor_devices(void)
}
}
-/* Types of sleep_switch used in omap_set_pwrdm_state */
-#define FORCEWAKEUP_SWITCH 0
-#define LOWPOWERSTATE_SWITCH 1
-
int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
{
if (clkdm-flags CLKDM_CAN_ENABLE_AUTO)
@@ -89,64 +85,6 @@ int __init omap_pm_clkdms_setup(struct clockdomain *clkdm,
void *unused)
}
/*
- * This sets pwrdm state (other than mpu core. Currently only ON
- * RET are supported.
- */
-int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst)
-{
- u8 curr_pwrst, next_pwrst;
- int sleep_switch = -1, ret = 0, hwsup = 0;
-
- if (!pwrdm || IS_ERR(pwrdm))
- return -EINVAL;
-
- while (!(pwrdm-pwrsts (1 pwrst))) {
- if (pwrst == PWRDM_POWER_OFF)
- return ret;
- pwrst--;
- }
-
- next_pwrst = pwrdm_read_next_pwrst(pwrdm);
- if (next_pwrst == pwrst)
- return ret;
-
- curr_pwrst = pwrdm_read_pwrst(pwrdm);
- if (curr_pwrst PWRDM_POWER_ON) {
- if ((curr_pwrst pwrst)
- (pwrdm-flags PWRDM_HAS_LOWPOWERSTATECHANGE)) {
- sleep_switch = LOWPOWERSTATE_SWITCH;
- } else {
- hwsup = clkdm_in_hwsup(pwrdm-pwrdm_clkdms[0]);
- clkdm_wakeup(pwrdm-pwrdm_clkdms[0]);
- sleep_switch = FORCEWAKEUP_SWITCH;
- }
- }
-
- ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
- if (ret)
- pr_err(%s: unable to set power state of powerdomain: %s\n,
- __func__, pwrdm-name);
-
- switch (sleep_switch) {
- case FORCEWAKEUP_SWITCH:
- if (hwsup)
- clkdm_allow_idle(pwrdm-pwrdm_clkdms[0]);
- else
- clkdm_sleep(pwrdm-pwrdm_clkdms[0]);
- break;
- case LOWPOWERSTATE_SWITCH:
- pwrdm_set_lowpwrstchange(pwrdm);
- pwrdm_wait_transition(pwrdm);
- pwrdm_state_switch(pwrdm);
- break;
- }
-
- return ret;
-}
-
-
-
-/*
* This API is to be called during init to set the various voltage
* domains to the voltage as per the opp table. Typically we boot up
* at the nominal voltage. So this function finds out the rate of
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 686137d..707e9cb 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -33,7 +33,6 @@ static inline int omap4_idle_init(void)
extern void *omap3_secure_ram_storage;
extern void omap3_pm_off_mode_enable(int);
extern void omap_sram_idle(void);
-extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
extern int (*omap_pm_suspend)(void);
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index a29caec..dcd2315 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -24,6 +24,11 @@
#include voltage.h
+/***
+ * External API, to be used by external PM components: cpuidle,
+ * suspend, pm, clock* etc.
+ ***/
+
/* Powerdomain functional power states, used by the external API functions */
enum pwrdm_func_state {
PWRDM_FUNC_PWRST_OFF= 0x0,
@@ -44,6 +49,64 @@ enum pwrdm_logic_mem_state {
PWRDM_MAX_LOGIC_MEM_PWRST /* Last value, used as the max value */
};
+struct clockdomain;
+struct powerdomain;
+
+struct powerdomain *pwrdm_lookup(const char *name);
+
+int pwrdm_for_each(int (*fn)(struct
Re: [PATCH] perf: Use pre-empt safe cpu_get/put insted of smp_processor_id
Hi Roger,
On Fri, Aug 10, 2012 at 4:05 PM, Roger Quadros rog...@ti.com wrote:
gets rid of below messages with CONFIG_DEBUG_PREEMPT enabled
[ 28.832916] debug_smp_processor_id: 18 callbacks suppressed
[ 28.832946] BUG: using smp_processor_id() in preemptible [] code:
modprobe/1763
[ 28.841491] caller is pwrdm_set_next_pwrst+0x54/0x120
Signed-off-by: Roger Quadros rog...@ti.com
What his the status of the patch? Has it been reviewed and taken in an
integration tree? I cannot find anything about it in l-o and
linux-next.
I have some changes on-going in the OMAP PM code and I would like to
know if $SUBJECT is applicable.
Regards,
Jean
---
arch/arm/mach-omap2/clock.c |9 ++---
arch/arm/mach-omap2/pm34xx.c | 12
arch/arm/mach-omap2/powerdomain.c |6 --
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565..06747b6 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -285,7 +285,8 @@ void omap2_clk_disable(struct clk *clk)
pr_debug(clock: %s: disabling in hardware\n, clk-name);
if (clk-ops clk-ops-disable) {
- trace_clock_disable(clk-name, 0, smp_processor_id());
+ trace_clock_disable(clk-name, 0, get_cpu());
+ put_cpu();
clk-ops-disable(clk);
}
@@ -339,7 +340,8 @@ int omap2_clk_enable(struct clk *clk)
}
if (clk-ops clk-ops-enable) {
- trace_clock_enable(clk-name, 1, smp_processor_id());
+ trace_clock_enable(clk-name, 1, get_cpu());
+ put_cpu();
ret = clk-ops-enable(clk);
if (ret) {
WARN(1, clock: %s: could not enable: %d\n,
@@ -380,7 +382,8 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long
rate)
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
if (clk-set_rate) {
- trace_clock_set_rate(clk-name, rate, smp_processor_id());
+ trace_clock_set_rate(clk-name, rate, get_cpu());
+ put_cpu();
ret = clk-set_rate(clk, rate);
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..81fec2e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -357,18 +357,22 @@ void omap_sram_idle(void)
static void omap3_pm_idle(void)
{
+ unsigned cpu;
+
local_fiq_disable();
if (omap_irq_pending())
goto out;
- trace_power_start(POWER_CSTATE, 1, smp_processor_id());
- trace_cpu_idle(1, smp_processor_id());
+ cpu = get_cpu();
+ trace_power_start(POWER_CSTATE, 1, cpu);
+ trace_cpu_idle(1, cpu);
omap_sram_idle();
- trace_power_end(smp_processor_id());
- trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
+ trace_power_end(cpu);
+ trace_cpu_idle(PWR_EVENT_EXIT, cpu);
+ put_cpu();
out:
local_fiq_enable();
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 69b36e1..138bf86 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -169,7 +169,8 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
((state OMAP_POWERSTATE_MASK) 8) |
((prev OMAP_POWERSTATE_MASK) 0));
trace_power_domain_target(pwrdm-name, trace_state,
- smp_processor_id());
+ get_cpu());
+ put_cpu();
}
break;
default:
@@ -491,7 +492,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8
pwrst)
if (arch_pwrdm arch_pwrdm-pwrdm_set_next_pwrst) {
/* Trace the pwrdm desired target state */
trace_power_domain_target(pwrdm-name, pwrst,
- smp_processor_id());
+ get_cpu());
+ put_cpu();
/* Program the pwrdm desired target state */
ret = arch_pwrdm-pwrdm_set_next_pwrst(pwrdm, pwrst);
}
--
1.7.4.1
--
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Re: [PATCH] perf: Use pre-empt safe cpu_get/put insted of smp_processor_id
Fixed Paul's email address
On Thu, Sep 6, 2012 at 8:56 PM, Jean Pihet jean.pi...@newoldbits.com wrote:
Hi Roger,
On Fri, Aug 10, 2012 at 4:05 PM, Roger Quadros rog...@ti.com wrote:
gets rid of below messages with CONFIG_DEBUG_PREEMPT enabled
[ 28.832916] debug_smp_processor_id: 18 callbacks suppressed
[ 28.832946] BUG: using smp_processor_id() in preemptible [] code:
modprobe/1763
[ 28.841491] caller is pwrdm_set_next_pwrst+0x54/0x120
Signed-off-by: Roger Quadros rog...@ti.com
What his the status of the patch? Has it been reviewed and taken in an
integration tree? I cannot find anything about it in l-o and
linux-next.
I have some changes on-going in the OMAP PM code and I would like to
know if $SUBJECT is applicable.
Regards,
Jean
---
arch/arm/mach-omap2/clock.c |9 ++---
arch/arm/mach-omap2/pm34xx.c | 12
arch/arm/mach-omap2/powerdomain.c |6 --
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565..06747b6 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -285,7 +285,8 @@ void omap2_clk_disable(struct clk *clk)
pr_debug(clock: %s: disabling in hardware\n, clk-name);
if (clk-ops clk-ops-disable) {
- trace_clock_disable(clk-name, 0, smp_processor_id());
+ trace_clock_disable(clk-name, 0, get_cpu());
+ put_cpu();
clk-ops-disable(clk);
}
@@ -339,7 +340,8 @@ int omap2_clk_enable(struct clk *clk)
}
if (clk-ops clk-ops-enable) {
- trace_clock_enable(clk-name, 1, smp_processor_id());
+ trace_clock_enable(clk-name, 1, get_cpu());
+ put_cpu();
ret = clk-ops-enable(clk);
if (ret) {
WARN(1, clock: %s: could not enable: %d\n,
@@ -380,7 +382,8 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long
rate)
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
if (clk-set_rate) {
- trace_clock_set_rate(clk-name, rate, smp_processor_id());
+ trace_clock_set_rate(clk-name, rate, get_cpu());
+ put_cpu();
ret = clk-set_rate(clk, rate);
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..81fec2e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -357,18 +357,22 @@ void omap_sram_idle(void)
static void omap3_pm_idle(void)
{
+ unsigned cpu;
+
local_fiq_disable();
if (omap_irq_pending())
goto out;
- trace_power_start(POWER_CSTATE, 1, smp_processor_id());
- trace_cpu_idle(1, smp_processor_id());
+ cpu = get_cpu();
+ trace_power_start(POWER_CSTATE, 1, cpu);
+ trace_cpu_idle(1, cpu);
omap_sram_idle();
- trace_power_end(smp_processor_id());
- trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
+ trace_power_end(cpu);
+ trace_cpu_idle(PWR_EVENT_EXIT, cpu);
+ put_cpu();
out:
local_fiq_enable();
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 69b36e1..138bf86 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -169,7 +169,8 @@ static int _pwrdm_state_switch(struct powerdomain
*pwrdm, int flag)
((state OMAP_POWERSTATE_MASK) 8)
|
((prev OMAP_POWERSTATE_MASK) 0));
trace_power_domain_target(pwrdm-name, trace_state,
- smp_processor_id());
+ get_cpu());
+ put_cpu();
}
break;
default:
@@ -491,7 +492,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8
pwrst)
if (arch_pwrdm arch_pwrdm-pwrdm_set_next_pwrst) {
/* Trace the pwrdm desired target state */
trace_power_domain_target(pwrdm-name, pwrst,
- smp_processor_id());
+ get_cpu());
+ put_cpu();
/* Program the pwrdm desired target state */
ret = arch_pwrdm-pwrdm_set_next_pwrst(pwrdm, pwrst);
}
--
1.7.4.1
--
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Re: [PATCHv2 7/8] ir-rx51: Convert latency constraints to PM QoS API
Hi Timo, On Fri, Aug 24, 2012 at 10:39 PM, Tony Lindgren t...@atomide.com wrote: * Timo Kokkonen timo.t.kokko...@iki.fi [120824 08:11]: Convert the driver from the obsolete omap_pm_set_max_mpu_wakeup_lat API to the new PM QoS API. This allows the callback to be removed from the platform data structure. The latency requirements are also adjusted to prevent the MPU from going into sleep mode. This is needed as the GP timers have no means to wake up the MPU once it has gone into sleep. The side effect is that from now on the driver actually works even if there is no background load keeping the MPU awake. Signed-off-by: Timo Kokkonen timo.t.kokko...@iki.fi This should get acked by Kevin ideally. Other than that: Acked-by: Tony Lindgren t...@atomide.com ... @@ -268,10 +270,14 @@ static ssize_t lirc_rx51_write(struct file *file, const char *buf, lirc_rx51-wbuf[count] = -1; /* Insert termination mark */ /* -* Adjust latency requirements so the device doesn't go in too -* deep sleep states +* If the MPU is going into too deep sleep state while we are +* transmitting the IR code, timers will not be able to wake +* up the MPU. Thus, we need to set a strict enough latency +* requirement in order to ensure the interrupts come though +* properly. */ - lirc_rx51-pdata-set_max_mpu_wakeup_lat(lirc_rx51-dev, 50); + pm_qos_add_request(lirc_rx51-pm_qos_request, + PM_QOS_CPU_DMA_LATENCY, 10); Minor remark: it would be nice to have more detail on where the latency number 10 comes from. Is it fixed, is it linked to the baud rate etc? Here is my ack for the PM QoS API part: Acked-by: Jean Pihet j-pi...@ti.com Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 7/8] ir-rx51: Remove MPU wakeup latency adjustments
Hi Timo, On Fri, Aug 24, 2012 at 10:14 AM, Timo Kokkonen timo.t.kokko...@iki.fi wrote: Hi Jean, On 08/23/12 14:58, Jean Pihet wrote: Hi Timo, On Wed, Aug 22, 2012 at 9:50 PM, Timo Kokkonen timo.t.kokko...@iki.fi wrote: That is correct. The API to use is the PM QoS API which cpuidle uses to determine the next MPU state based on the allowed latency. A more appropriate fix for the problem would be to modify the idle layer so that it does not allow MPU going to too deep sleep modes when it is expected that the timers need to wake up MPU. The idle layer already uses the PM QoS framework to decide the next MPU state. I think the right solution is to convert from omap_pm_set_max_mpu_wakeup_lat to the PM QoS API. Cf. http://marc.info/?l=linux-omapm=133968658305580w=2 for an example of the conversion. Thanks. It looks like really easy and straightforward conversion. However, I couldn't find the patch you were referring to from any trees Correct, this patch is not applied to the mainline code yet, it is provided as an example of the conversion. I could find. So, I take that this API does not really have omap2 support in it yet? I tried git grepping through the source and to me it appears there is nothing in place yet that actually restricts the MPU sleep states on omap2 when requested. The MPU state is controlled from the cpuidle framework, which retrieves the MPU allowed latency from the PM QoS framework. This is supported on OMAP2. Cf. the table of states and the associated latency in arch/arm/mach-omap2/cpuidle34xx.c. Which puzzles me.. The patch you are referring to transfers the omap I2C from the old omap PM API to the new QOS API is not applied yet in mainline. The I2C is definitely working with the old API too, I'm just wondering why I can't make it working with either of the APIs.. Am I missing something here? AFAIK the old API is a noop in mainline. Using the PM QoS API defnitely is supported, that is why I think the conversion needs to be performed. Therefore, it makes sense to actually remove this call entirely from the ir-rx51 driver as it is both wrong and does nothing useful at the moment. Signed-off-by: Timo Kokkonen timo.t.kokko...@iki.fi Regards, Jean Thanks, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 7/8] ir-rx51: Remove MPU wakeup latency adjustments
Hi Timo,
On Wed, Aug 22, 2012 at 9:50 PM, Timo Kokkonen timo.t.kokko...@iki.fi wrote:
The ir-rx51 driver calls omap_pm_set_max_mpu_wakeup_lat() in order to
avoid problems that occur when MPU goes to sleep in the middle of
sending an IR code. Without such calls it takes ridiculously long for
the MPU to wake up from a sleep, which distorts the IR signal
completely.
However, the actual problem is that probably the GP timers are not
able to wake up the MPU at all. That is, adjusting the latency
requirements is not the correct way to solve the issue either. The
reason why this used to work with the original 2.6.28 based N900
kernel that is shipped with the product is that placing strict latency
requirements prevents the MPU from going to sleep at all. Furthermore,
the only PM layer imlementation available at the moment for OMAP3
doesn't do anything with the latency requirement placed with
omap_pm_set_max_mpu_wakeup_lat() calls.
That is correct. The API to use is the PM QoS API which cpuidle uses
to determine the next MPU state based on the allowed latency.
A more appropriate fix for the problem would be to modify the idle
layer so that it does not allow MPU going to too deep sleep modes when
it is expected that the timers need to wake up MPU.
The idle layer already uses the PM QoS framework to decide the next
MPU state. I think the right solution is to convert from
omap_pm_set_max_mpu_wakeup_lat to the PM QoS API.
Cf. http://marc.info/?l=linux-omapm=133968658305580w=2 for an
example of the conversion.
Therefore, it makes sense to actually remove this call entirely from
the ir-rx51 driver as it is both wrong and does nothing useful at the
moment.
Signed-off-by: Timo Kokkonen timo.t.kokko...@iki.fi
Regards,
Jean
---
arch/arm/mach-omap2/board-rx51-peripherals.c | 2 --
drivers/media/rc/ir-rx51.c | 9 -
include/media/ir-rx51.h | 2 --
3 files changed, 13 deletions(-)
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c
b/arch/arm/mach-omap2/board-rx51-peripherals.c
index ca07264..e0750cb 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -34,7 +34,6 @@
#include plat/gpmc.h
#include plat/onenand.h
#include plat/gpmc-smc91x.h
-#include plat/omap-pm.h
#include mach/board-rx51.h
@@ -1227,7 +1226,6 @@ static void __init rx51_init_tsc2005(void)
#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
static struct lirc_rx51_platform_data rx51_lirc_data = {
- .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
.pwm_timer = 9, /* Use GPT 9 for CIR */
};
diff --git a/drivers/media/rc/ir-rx51.c b/drivers/media/rc/ir-rx51.c
index 7eed541..ac7d3f0 100644
--- a/drivers/media/rc/ir-rx51.c
+++ b/drivers/media/rc/ir-rx51.c
@@ -267,12 +267,6 @@ static ssize_t lirc_rx51_write(struct file *file, const
char *buf,
if (count WBUF_LEN)
lirc_rx51-wbuf[count] = -1; /* Insert termination mark */
- /*
-* Adjust latency requirements so the device doesn't go in too
-* deep sleep states
-*/
- lirc_rx51-pdata-set_max_mpu_wakeup_lat(lirc_rx51-dev, 50);
-
lirc_rx51_on(lirc_rx51);
lirc_rx51-wbuf_index = 1;
pulse_timer_set_timeout(lirc_rx51, lirc_rx51-wbuf[0]);
@@ -292,9 +286,6 @@ static ssize_t lirc_rx51_write(struct file *file, const
char *buf,
*/
lirc_rx51_stop_tx(lirc_rx51);
- /* We can sleep again */
- lirc_rx51-pdata-set_max_mpu_wakeup_lat(lirc_rx51-dev, -1);
-
return n;
}
diff --git a/include/media/ir-rx51.h b/include/media/ir-rx51.h
index 104aa89..57523f2 100644
--- a/include/media/ir-rx51.h
+++ b/include/media/ir-rx51.h
@@ -3,8 +3,6 @@
struct lirc_rx51_platform_data {
int pwm_timer;
-
- int(*set_max_mpu_wakeup_lat)(struct device *dev, long t);
};
#endif
--
1.7.12
--
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[PATCH v5 0/8] ARM: OMAP2+: PM: introduce the power domains functional states
Here is a re-spin after some comments and suggestions after review. Implement the functional states for the power domains: - unify the API to use the functional states. pwrdm_set_next_fpwrst now is the function to control the power domains power and logic states, - reorganize the powerdomain API in internal and external parts, in powerdomain.h [1] - protect the power domain state change by a lock in pwrdm_set_next_fpwrst, - introduce the functional states for power domains power states and logic power states, and the conversion functions between the functional and internal states, - program the logic power state of power domains from the functional states, in pwrdm_set_next_fpwrst - convert the OMAP2/3/4 PM code to use the updated API, - provide the power domains statistics by functional states, - provide ftrace tracepoints with the functional state, - provide error logs in critical code, which makes the development easier. Note: [1] the physical split of internal and external APIs into different header files is not part of this series, it comes as a separate patch set. Based on mainline kernel 3.6.0-rc1. Tested on OMAP3 Beagleboard, with suspend and cpuidle in RET and OFF modes. History: v5: - complete rework after review and suggestions, - improved locking on next state read/write; spinlock instead of mutex - added more error logging in critical code, v4: - reworked the code after internal review and testing with OMAP34 device OFF, - fixed the tracepoints generation code, - introduce a function that returns power domains achievable functional states, in order to return a valid state for power domains that only support some of the power states. Although it has been tested OK the code is in RFC state. v3: - fix a bug in OMAP3 cpuidle which prevented the IO wake-ups in PER v2: - add the logic power states, - provide the power domains statistics by functional states v1: - initial implementation, in RFC state Jean Pihet (7): ARM: OMAP2+: PM: introduce power domains functional states ARM: OMAP2+: PM: introduce power domains achievable functional states ARM: OMAP2+: PM: add a lock to protect the powerdomains next state ARM: OMAP2+: PM: use the functional power states API ARM: OMAP2+: PM: use power domain functional state in stats counters ARM: OMAP2+: PM debug: trace the functional power domains states ARM: OMAP2+: PM: reorganize the powerdomain API in public and private parts Nishanth Menon (1): ARM: OMAP2+: powerdomain: add error logs arch/arm/mach-omap2/cpuidle34xx.c | 58 ++-- arch/arm/mach-omap2/cpuidle44xx.c | 24 +- arch/arm/mach-omap2/omap-hotplug.c |2 +- arch/arm/mach-omap2/omap-mpuss-lowpower.c | 39 ++-- arch/arm/mach-omap2/pm-debug.c | 15 +- arch/arm/mach-omap2/pm24xx.c | 14 +- arch/arm/mach-omap2/pm34xx.c | 79 +++--- arch/arm/mach-omap2/pm44xx.c | 24 +- arch/arm/mach-omap2/powerdomain-common.c | 99 ++ arch/arm/mach-omap2/powerdomain.c | 456 +--- arch/arm/mach-omap2/powerdomain.h | 152 ++--- arch/arm/mach-omap2/powerdomain2xxx_3xxx.c |6 + arch/arm/mach-omap2/powerdomain44xx.c |3 + 13 files changed, 753 insertions(+), 218 deletions(-) -- 1.7.7.6 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/8] ARM: OMAP2+: PM: introduce power domains functional states
Introduce the functional states for power domains, which include
the power states and the logic states.
This patch provides the API functions to set and read the power
domains settings and to convert between the functional (i.e. logical)
and the internal (or registers) values.
OMAP2, OMAP3 and OMAP4 platforms are using common conversion routines.
In the new API only the function pwrdm_set_next_fpwrst shall be used
to change a power domain target state, along with the associated
PWRDM_FUNC_* and PWRDM_LOGIC_* macros as the state parameters.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/powerdomain-common.c | 99
arch/arm/mach-omap2/powerdomain.c | 225 +++-
arch/arm/mach-omap2/powerdomain.h | 45 +-
arch/arm/mach-omap2/powerdomain2xxx_3xxx.c |6 +
arch/arm/mach-omap2/powerdomain44xx.c |3 +
5 files changed, 368 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain-common.c
b/arch/arm/mach-omap2/powerdomain-common.c
index c0aeabf..a0fcee3 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -108,3 +108,102 @@ u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
return 0;
}
+/**
+ * omap2_pwrdm_fpwrst_to_pwrst - Convert functional (i.e. logical) to
+ * internal (i.e. registers) values for the power domains states.
+ * @struct powerdomain * to convert the values for
+ * @fpwrst: functional power state
+ *
+ * Returns the internal power state value for the power domain, or
+ * -EINVAL in case of invalid parameters passed in.
+ */
+int omap2_pwrdm_fpwrst_to_pwrst(struct powerdomain *pwrdm, u8 fpwrst)
+{
+ int ret;
+
+ switch (fpwrst) {
+ case PWRDM_FUNC_PWRST_ON:
+ ret = PWRDM_POWER_ON;
+ break;
+ case PWRDM_FUNC_PWRST_INACTIVE:
+ ret = PWRDM_POWER_INACTIVE;
+ break;
+ case PWRDM_FUNC_PWRST_CSWR:
+ case PWRDM_FUNC_PWRST_OSWR:
+ ret = PWRDM_POWER_RET;
+ break;
+ case PWRDM_FUNC_PWRST_OFF:
+ ret = PWRDM_POWER_OFF;
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * omap2_pwrdm_fpwrst_to_logic_pwrst - Convert functional (i.e. logical) to
+ * internal (i.e. registers) values for the power domains logic states.
+ * @struct powerdomain * to convert the values for
+ * @pwrst: functional power state
+ *
+ * Returns the internal logic state value for the power domain, or
+ * -EINVAL in case of invalid parameters passed in.
+ */
+int omap2_pwrdm_fpwrst_to_logic_pwrst(struct powerdomain *pwrdm, u8 fpwrst)
+{
+ int ret;
+
+ switch (fpwrst) {
+ case PWRDM_FUNC_PWRST_ON:
+ case PWRDM_FUNC_PWRST_INACTIVE:
+ case PWRDM_FUNC_PWRST_CSWR:
+ ret = PWRDM_LOGIC_MEM_PWRST_RET;
+ break;
+ case PWRDM_FUNC_PWRST_OSWR:
+ case PWRDM_FUNC_PWRST_OFF:
+ ret = PWRDM_LOGIC_MEM_PWRST_OFF;
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * omap2_pwrdm_pwrst_to_fpwrst - Convert internal (i.e. registers) to
+ * functional (i.e. logical) values for the power domains states.
+ * @struct powerdomain * to convert the values for
+ * @pwrst: internal power state
+ *
+ * Returns the functional power state value for the power domain, or
+ * -EINVAL in case of invalid parameters passed in.
+ */
+int omap2_pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic)
+{
+ int ret;
+
+ switch (pwrst) {
+ case PWRDM_POWER_ON:
+ ret = PWRDM_FUNC_PWRST_ON;
+ break;
+ case PWRDM_POWER_INACTIVE:
+ ret = PWRDM_FUNC_PWRST_INACTIVE;
+ break;
+ case PWRDM_POWER_RET:
+ if (logic == PWRDM_LOGIC_MEM_PWRST_RET)
+ ret = PWRDM_FUNC_PWRST_CSWR;
+ else
+ ret = PWRDM_FUNC_PWRST_OSWR;
+ break;
+ case PWRDM_POWER_OFF:
+ ret = PWRDM_FUNC_PWRST_OFF;
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 69b36e1..6fc3c84 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1,7 +1,7 @@
/*
* OMAP powerdomain control
*
- * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011-2012 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
@@ -128,14 +128,14 @@ static void _update_logic_membank_counters(struct
powerdomain *pwrdm)
prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm);
if ((pwrdm-pwrsts_logic_ret == PWRSTS_OFF_RET)
- (prev_logic_pwrst == PWRDM_POWER_OFF
[PATCH 2/8] ARM: OMAP2+: PM: introduce power domains achievable functional states
Note: the patch is in RFC state because the state machine for setting
the next power domain states needs more discussion. Validated on OMAP34
with cpuidle and suspend/resume, though.
Power domains have varied capabilities. When attempting a low power
state such as OFF/RET, a specific min requested state may not be
supported on the power domain. This is because a combination
of system power states where the parent PD's state is not in line
with expectation can result in system instabilities.
This patch provides a function that returns the achievable functional
power state for a power domain and its use by pwrdm_set_next_fpwrst.
The achievable power state is first looked for in the lower power
states in order to maximize the power savings, then if not found
in the higher power states.
Inspired from Tero's work on OMAP4 device OFF support, generalized
to the functional power states and reworked as per Nishant's
suggestions.
Signed-off-by: Jean Pihet j-pi...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 152 +++--
arch/arm/mach-omap2/powerdomain.h |1 +
2 files changed, 130 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 6fc3c84..3a1f56c 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -199,6 +199,53 @@ static int _pwrdm_post_transition_cb(struct powerdomain
*pwrdm, void *unused)
return 0;
}
+/**
+ * Search down then up for a valid state from a list of allowed states.
+ * Used by pwrdm_get_achievable_fpwrst to look for allowed power and
+ * logic states for a powerdomain.
+ *
+ * @pwrsts: list of allowed states, defined as a bitmask
+ * @pwrst: initial state to be used as a starting point
+ * @min: minimum allowed state
+ * @max: maximum allowed state
+ *
+ * Returns the matching allowed state.
+ */
+static inline int _match_pwrst(u32 pwrsts, int pwrst, int min, int max)
+{
+ int found = 1, new_pwrst = pwrst;
+
+ /*
+* Search lower: if the requested state is not supported
+* try the lower states, stopping at the minimum allowed
+* state
+*/
+ while (!(pwrsts (1 new_pwrst))) {
+ if (new_pwrst = min) {
+ found = 0;
+ break;
+ }
+ new_pwrst--;
+ }
+
+ /*
+* Search higher: if no lower state found fallback to the higher
+* states, stopping at the maximum allowed state
+*/
+ if (!found) {
+ new_pwrst = pwrst;
+ while (!(pwrsts (1 new_pwrst))) {
+ if (new_pwrst = max) {
+ new_pwrst = max;
+ break;
+ }
+ new_pwrst++;
+ }
+ }
+
+ return new_pwrst;
+}
+
/* Public functions */
/**
@@ -553,6 +600,57 @@ int pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8
pwrst, u8 logic)
return ret;
}
+/**
+ * pwrdm_get_achievable_fpwrst() - Provide achievable functional state
+ * @pwrdm: struct powerdomain * to set
+ * @fpwrst: minimum functional state we would like to hit
+ * (one of the PWRDM_FUNC_* macros)
+ *
+ * Power domains have varied capabilities. When attempting a low power
+ * state such as OFF/RET, a specific min requested state may not be
+ * supported on the power domain. This is because a combination
+ * of system power states where the parent PD's state is not in line
+ * with expectation can result in system instabilities.
+ *
+ * The achievable power state is first looked for in the lower power
+ * states in order to maximize the power savings, then if not found
+ * in the higher power states.
+ *
+ * Returns the achievable functional power state, or -EINVAL in case of
+ * invalid parameters.
+ */
+int pwrdm_get_achievable_fpwrst(struct powerdomain *pwrdm, u8 fpwrst)
+{
+ int pwrst = pwrdm_fpwrst_to_pwrst(pwrdm, fpwrst);
+ int logic = pwrdm_fpwrst_to_logic_pwrst(pwrdm, fpwrst);
+ int new_fpwrst, new_pwrst, new_logic;
+
+ if (!pwrdm || IS_ERR(pwrdm)) {
+ pr_debug(%s: invalid params: pwrdm=%p, fpwrst=%0x\n,
+__func__, pwrdm, fpwrst);
+ return -EINVAL;
+ }
+
+ if ((pwrst 0) || (logic 0)) {
+ pr_debug(%s: invalid params for pwrdm %s, fpwrst=%0x\n,
+__func__, pwrdm-name, fpwrst);
+ return PWRDM_FUNC_PWRST_ON;
+ }
+
+ new_pwrst = _match_pwrst(pwrdm-pwrsts, pwrst, PWRDM_POWER_OFF,
+PWRDM_POWER_ON);
+ new_logic = _match_pwrst(pwrdm-pwrsts_logic_ret, logic,
+PWRDM_LOGIC_MEM_PWRST_OFF,
+PWRDM_LOGIC_MEM_PWRST_RET);
+
+ new_fpwrst = pwrdm_pwrst_to_fpwrst(pwrdm, new_pwrst
[PATCH 3/8] ARM: OMAP2+: PM: add a lock to protect the powerdomains next state
pwrdm_set_next_fpwrst and pwrdm_read_next_fpwrst are intented
to be the only API to program and request the next state of a power
domain.
This patch protects the power domain next state settings and structs
from concurrent accesses by the use of a lock.
A spinlock is used since pwrdm_set_next_fpwrst and
pwrdm_read_next_fpwrst can be called from atomic context
(.i.e) either from cpuidle path or suspend path.
[ambr...@ti.com: reported the atomic context issue and suggested
to replace the mutex with a spinlock]
Signed-off-by: Jean Pihet j-pi...@ti.com
Reported-by: Ambresh K ambr...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 36 +++-
arch/arm/mach-omap2/powerdomain.h |3 +++
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 3a1f56c..a8f7a81 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
INIT_LIST_HEAD(pwrdm-voltdm_node);
voltdm_add_pwrdm(voltdm, pwrdm);
+ spin_lock_init(pwrdm-lock);
list_add(pwrdm-node, pwrdm_list);
/* Initialize the powerdomain's state counter */
@@ -601,6 +602,22 @@ int pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8
pwrst, u8 logic)
}
/**
+ * _pwrdm_read_next_fpwrst - get next powerdomain functional power state
+ * @pwrdm: struct powerdomain * to get power state
+ *
+ * Return the powerdomain @pwrdm's next functional power state.
+ * Returns -EINVAL if the powerdomain pointer is null or returns
+ * the next power state upon success.
+ */
+int _pwrdm_read_next_fpwrst(struct powerdomain *pwrdm)
+{
+ int next_pwrst = pwrdm_read_next_pwrst(pwrdm);
+ int next_logic = pwrdm_read_logic_retst(pwrdm);
+
+ return pwrdm_pwrst_to_fpwrst(pwrdm, next_pwrst, next_logic);
+}
+
+/**
* pwrdm_get_achievable_fpwrst() - Provide achievable functional state
* @pwrdm: struct powerdomain * to set
* @fpwrst: minimum functional state we would like to hit
@@ -670,6 +687,7 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
int sleep_switch = -1, ret = 0, hwsup = 0;
int new_fpwrst, next_fpwrst, pwrst, logic;
u8 curr_pwrst;
+ unsigned long flags;
if (!pwrdm || IS_ERR(pwrdm)) {
pr_debug(%s: invalid params: pwrdm=%p\n, __func__, pwrdm);
@@ -678,13 +696,15 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
pr_debug(%s(%s, fpwrst=%0x)\n, __func__, pwrdm-name, fpwrst);
+ spin_lock_irqsave(pwrdm-lock, flags);
+
new_fpwrst = pwrdm_get_achievable_fpwrst(pwrdm, fpwrst);
pwrst = pwrdm_fpwrst_to_pwrst(pwrdm, new_fpwrst);
logic = pwrdm_fpwrst_to_logic_pwrst(pwrdm, new_fpwrst);
- next_fpwrst = pwrdm_read_next_fpwrst(pwrdm);
+ next_fpwrst = _pwrdm_read_next_fpwrst(pwrdm);
if (new_fpwrst == next_fpwrst)
- return ret;
+ goto out;
curr_pwrst = pwrdm_read_pwrst(pwrdm);
if (curr_pwrst PWRDM_POWER_ON) {
@@ -732,6 +752,8 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
break;
}
+out:
+ spin_unlock_irqrestore(pwrdm-lock, flags);
return ret;
}
@@ -801,10 +823,14 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
*/
int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm)
{
- int next_pwrst = pwrdm_read_next_pwrst(pwrdm);
- int next_logic = pwrdm_read_logic_retst(pwrdm);
+ int ret;
+ unsigned long flags;
- return pwrdm_pwrst_to_fpwrst(pwrdm, next_pwrst, next_logic);
+ spin_lock_irqsave(pwrdm-lock, flags);
+ ret = _pwrdm_read_next_fpwrst(pwrdm);
+ spin_unlock_irqrestore(pwrdm-lock, flags);
+
+ return ret;
}
/**
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index 45c449d..23b9da9 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -17,6 +17,7 @@
#include linux/types.h
#include linux/list.h
+#include linux/spinlock.h
#include linux/atomic.h
#include plat/cpu.h
@@ -109,6 +110,7 @@ struct powerdomain;
* @pwrdm_clkdms: Clockdomains in this powerdomain
* @node: list_head linking all powerdomains
* @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ * @lock: powerdomain next state registers protection lock
* @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
* @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
* @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
@@ -142,6 +144,7 @@ struct powerdomain {
struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
struct list_head node;
struct list_head voltdm_node;
+ spinlock_t lock;
int state;
unsigned state_counter[PWRDM_MAX_PWRSTS];
unsigned ret_logic_off_counter;
--
1.7.7.6
[PATCH 4/8] ARM: OMAP2+: PM: use the functional power states API
Use the functional power states as the API to control power
domains:
- use the PWRDM_FUNC_PWRST_* and PWRDM_LOGIC_MEM_PWRST_*
macros for the power states and logic settings,
- the pwrdm_set_next_fpwrst function, which controls
the power states and logic settings of power domains, shall
be used instead of pwrdm_set_next_pwrst to program the power
domains next states.
Note: the internal code for power domains state management still
uses the internal power states.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 58 +++---
arch/arm/mach-omap2/cpuidle44xx.c | 24 +++--
arch/arm/mach-omap2/omap-hotplug.c|2 +-
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 39 +++---
arch/arm/mach-omap2/pm24xx.c | 14 ++---
arch/arm/mach-omap2/pm34xx.c | 79 +++--
arch/arm/mach-omap2/pm44xx.c | 24 +++--
arch/arm/mach-omap2/powerdomain.c |2 +-
8 files changed, 116 insertions(+), 126 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index f2a49a4..4ca37d2 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -44,32 +44,32 @@ struct omap3_idle_statedata {
static struct omap3_idle_statedata omap3_idle_data[] = {
{
- .mpu_state = PWRDM_POWER_ON,
- .core_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_FUNC_PWRST_ON,
+ .core_state = PWRDM_FUNC_PWRST_ON,
},
{
- .mpu_state = PWRDM_POWER_ON,
- .core_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_FUNC_PWRST_ON,
+ .core_state = PWRDM_FUNC_PWRST_ON,
},
{
- .mpu_state = PWRDM_POWER_RET,
- .core_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_FUNC_PWRST_CSWR,
+ .core_state = PWRDM_FUNC_PWRST_ON,
},
{
- .mpu_state = PWRDM_POWER_OFF,
- .core_state = PWRDM_POWER_ON,
+ .mpu_state = PWRDM_FUNC_PWRST_OFF,
+ .core_state = PWRDM_FUNC_PWRST_ON,
},
{
- .mpu_state = PWRDM_POWER_RET,
- .core_state = PWRDM_POWER_RET,
+ .mpu_state = PWRDM_FUNC_PWRST_CSWR,
+ .core_state = PWRDM_FUNC_PWRST_CSWR,
},
{
- .mpu_state = PWRDM_POWER_OFF,
- .core_state = PWRDM_POWER_RET,
+ .mpu_state = PWRDM_FUNC_PWRST_OFF,
+ .core_state = PWRDM_FUNC_PWRST_CSWR,
},
{
- .mpu_state = PWRDM_POWER_OFF,
- .core_state = PWRDM_POWER_OFF,
+ .mpu_state = PWRDM_FUNC_PWRST_OFF,
+ .core_state = PWRDM_FUNC_PWRST_OFF,
},
};
@@ -84,8 +84,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
local_fiq_disable();
- pwrdm_set_next_pwrst(mpu_pd, mpu_state);
- pwrdm_set_next_pwrst(core_pd, core_state);
+ pwrdm_set_next_fpwrst(mpu_pd, mpu_state);
+ pwrdm_set_next_fpwrst(core_pd, core_state);
if (omap_irq_pending() || need_resched())
goto return_sleep_time;
@@ -100,7 +100,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
* Call idle CPU PM enter notifier chain so that
* VFP context is saved.
*/
- if (mpu_state == PWRDM_POWER_OFF)
+ if (mpu_state == PWRDM_FUNC_PWRST_OFF)
cpu_pm_enter();
/* Execute ARM wfi */
@@ -110,7 +110,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
* Call idle CPU PM enter notifier chain to restore
* VFP context.
*/
- if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
+ if (pwrdm_read_prev_fpwrst(mpu_pd) == PWRDM_FUNC_PWRST_OFF)
cpu_pm_exit();
/* Re-allow idle for C1 */
@@ -159,20 +159,20 @@ static int next_valid_state(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
struct omap3_idle_statedata *cx = omap3_idle_data[index];
- u32 mpu_deepest_state = PWRDM_POWER_RET;
- u32 core_deepest_state = PWRDM_POWER_RET;
+ u32 mpu_deepest_state = PWRDM_FUNC_PWRST_CSWR;
+ u32 core_deepest_state = PWRDM_FUNC_PWRST_CSWR;
int idx;
int next_index = 0; /* C1 is the default value */
if (enable_off_mode) {
- mpu_deepest_state = PWRDM_POWER_OFF;
+ mpu_deepest_state = PWRDM_FUNC_PWRST_OFF;
/*
* Erratum i583: valable for ES rev Es1.2 on 3630.
* CORE OFF mode is not supported in a stable form, restrict
* instead the CORE state to RET.
*/
if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
- core_deepest_state
[PATCH 6/8] ARM: OMAP2+: PM debug: trace the functional power domains states
Trace the power domain transitions using the functional power states,
which include the power and logic states.
While at it, fix the trace in the case a power domain did not hit
the desired state, as reported by Paul Walmsley.
Reported-by: Paul Walmsley p...@pwsan.com
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 15 +--
1 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 6b8580b..06a566b 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -144,7 +144,7 @@ static void _update_logic_membank_counters(struct
powerdomain *pwrdm)
static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
{
- int prev, state, trace_state = 0;
+ int prev, next, state, trace_state;
if (pwrdm == NULL)
return -EINVAL;
@@ -165,10 +165,10 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
* If the power domain did not hit the desired state,
* generate a trace event with both the desired and hit states
*/
- if (state != prev) {
+ next = pwrdm_read_next_fpwrst(pwrdm);
+ if (next != prev) {
trace_state = (PWRDM_TRACE_STATES_FLAG |
- ((state OMAP_POWERSTATE_MASK) 8) |
- ((prev OMAP_POWERSTATE_MASK) 0));
+ (next 8) | (prev 0));
trace_power_domain_target(pwrdm-name, trace_state,
smp_processor_id());
}
@@ -781,13 +781,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8
pwrst)
pr_debug(powerdomain: setting next powerstate for %s to %0x\n,
pwrdm-name, pwrst);
- if (arch_pwrdm arch_pwrdm-pwrdm_set_next_pwrst) {
- /* Trace the pwrdm desired target state */
- trace_power_domain_target(pwrdm-name, pwrst,
- smp_processor_id());
- /* Program the pwrdm desired target state */
+ if (arch_pwrdm arch_pwrdm-pwrdm_set_next_pwrst)
ret = arch_pwrdm-pwrdm_set_next_pwrst(pwrdm, pwrst);
- }
return ret;
}
--
1.7.7.6
--
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[PATCH 8/8] ARM: OMAP2+: PM: reorganize the powerdomain API in public and private parts
The newly added code for functional power states re-defines the
API to query and control the power domains settings.
The API is now split in the following parts in powerdomain.h:
- the public or external API, to be used by external PM components:
cpuidle, suspend, pm, clock* etc.
- the private or internal API, to be used by the low level PM code
only: powerdomain*, pm-debug, hwmod, voltage, clockdomain.
No functional change is introduced by this patch.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/powerdomain.h | 119 -
1 files changed, 65 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index df83c7c..0bf613c 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -24,6 +24,11 @@
#include voltage.h
+/***
+ * External API, to be used by external PM components: cpuidle,
+ * suspend, pm, clock* etc.
+ ***/
+
/* Powerdomain functional power states, used by the external API functions */
enum pwrdm_func_state {
PWRDM_FUNC_PWRST_OFF= 0x0,
@@ -44,6 +49,62 @@ enum pwrdm_logic_mem_state {
PWRDM_MAX_LOGIC_MEM_PWRST /* Last value, used as the max value */
};
+struct clockdomain;
+struct powerdomain;
+
+struct powerdomain *pwrdm_lookup(const char *name);
+
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+ void *user);
+int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
+ void *user);
+
+int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+int (*fn)(struct powerdomain *pwrdm,
+ struct clockdomain *clkdm));
+struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
+
+int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+
+/* Functions that query and control the power domain state setings */
+int pwrdm_get_achievable_fpwrst(struct powerdomain *pwrdm, u8 fpwrst);
+int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
+ enum pwrdm_func_state fpwrst);
+int pwrdm_read_prev_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_read_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
+int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
+
+int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
+bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
+
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
+
+int pwrdm_pre_transition(struct powerdomain *pwrdm);
+int pwrdm_post_transition(struct powerdomain *pwrdm);
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+
+extern void omap242x_powerdomains_init(void);
+extern void omap243x_powerdomains_init(void);
+extern void omap3xxx_powerdomains_init(void);
+extern void am33xx_powerdomains_init(void);
+extern void omap44xx_powerdomains_init(void);
+
+
+/***
+ * Internal API, to be included by the low level PM code only:
+ * powerdomain*, pm-debug, hwmod, voltage, clockdomain
+ ***/
+
/* Powerdomain basic power states */
#define PWRDM_POWER_OFF0x0
#define PWRDM_POWER_RET0x1
@@ -92,9 +153,6 @@ enum pwrdm_logic_mem_state {
/* XXX A completely arbitrary number. What is reasonable here? */
#define PWRDM_TRANSITION_BAILOUT 10
-struct clockdomain;
-struct powerdomain;
-
/**
* struct powerdomain - OMAP powerdomain
* @name: Powerdomain name
@@ -221,67 +279,17 @@ int pwrdm_register_platform_funcs(struct pwrdm_ops
*custom_funcs);
int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
int pwrdm_complete_init(void);
-struct powerdomain *pwrdm_lookup(const char *name);
-
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
- void *user);
-int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
- void *user);
-
-int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_for_each_clkdm
[PATCH 7/8] ARM: OMAP2+: powerdomain: add error logs
From: Nishanth Menon n...@ti.com
Silent failure makes debug hard. So, provide rate limited error
messages in functional and oft-used code to prevent spam
when something goes wrong..
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/powerdomain.c | 72 +---
1 files changed, 58 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 06a566b..691247e 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,6 +19,7 @@
#include linux/list.h
#include linux/errno.h
#include linux/string.h
+#include linux/ratelimit.h
#include trace/events/power.h
#include cm2xxx_3xxx.h
@@ -146,8 +147,12 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
int prev, next, state, trace_state;
- if (pwrdm == NULL)
+ if (pwrdm == NULL) {
+ WARN_ONCE(1, null pwrdm\n);
+ pr_err_ratelimited(%s: powerdomain: null pwrdm param\n,
+ __func__);
return -EINVAL;
+ }
state = pwrdm_read_fpwrst(pwrdm);
@@ -174,6 +179,8 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
}
break;
default:
+ pr_err_ratelimited(%s: powerdomain %s: bad flag %d\n,
+ __func__, pwrdm-name, flag);
return -EINVAL;
}
@@ -690,7 +697,8 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
unsigned long flags;
if (!pwrdm || IS_ERR(pwrdm)) {
- pr_debug(%s: invalid params: pwrdm=%p\n, __func__, pwrdm);
+ pr_err_ratelimited(%s: invalid params: pwrdm=%p\n,
+ __func__, pwrdm);
return -EINVAL;
}
@@ -775,8 +783,11 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8
pwrst)
if (!pwrdm)
return -EINVAL;
- if (!(pwrdm-pwrsts (1 pwrst)))
+ if (!(pwrdm-pwrsts (1 pwrst))) {
+ pr_err_ratelimited(%s: powerdomain %s: bad pwrst %d\n,
+ __func__, pwrdm-name, pwrst);
return -EINVAL;
+ }
pr_debug(powerdomain: setting next powerstate for %s to %0x\n,
pwrdm-name, pwrst);
@@ -924,8 +935,11 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8
pwrst)
if (!pwrdm)
return -EINVAL;
- if (!(pwrdm-pwrsts_logic_ret (1 pwrst)))
+ if (!(pwrdm-pwrsts_logic_ret (1 pwrst))) {
+ pr_err_ratelimited(%s: powerdomain %s: bad pwrst %d\n,
+ __func__, pwrdm-name, pwrst);
return -EINVAL;
+ }
pr_debug(powerdomain: setting next logic powerstate for %s to %0x\n,
pwrdm-name, pwrst);
@@ -958,11 +972,17 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8
bank, u8 pwrst)
if (!pwrdm)
return -EINVAL;
- if (pwrdm-banks (bank + 1))
+ if (pwrdm-banks (bank + 1)) {
+ pr_err_ratelimited(%s: powerdomain %s: bad bank %d\n,
+ __func__, pwrdm-name, bank);
return -EEXIST;
+ }
- if (!(pwrdm-pwrsts_mem_on[bank] (1 pwrst)))
+ if (!(pwrdm-pwrsts_mem_on[bank] (1 pwrst))) {
+ pr_err_ratelimited(%s: powerdomain %s: bank %d bad pwrst %d\n,
+ __func__, pwrdm-name, bank, pwrst);
return -EINVAL;
+ }
pr_debug(powerdomain: setting next memory powerstate for domain %s
bank %0x while pwrdm-ON to %0x\n, pwrdm-name, bank, pwrst);
@@ -996,11 +1016,17 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8
bank, u8 pwrst)
if (!pwrdm)
return -EINVAL;
- if (pwrdm-banks (bank + 1))
+ if (pwrdm-banks (bank + 1)) {
+ pr_err_ratelimited(%s: powerdomain %s: bad bank %d\n,
+ __func__, pwrdm-name, bank);
return -EEXIST;
+ }
- if (!(pwrdm-pwrsts_mem_ret[bank] (1 pwrst)))
+ if (!(pwrdm-pwrsts_mem_ret[bank] (1 pwrst))) {
+ pr_err_ratelimited(%s: powerdomain %s: bank %d bad pwrst %d\n,
+ __func__, pwrdm-name, bank, pwrst);
return -EINVAL;
+ }
pr_debug(powerdomain: setting next memory powerstate for domain %s
bank %0x while pwrdm-RET to %0x\n, pwrdm-name, bank, pwrst);
@@ -1092,8 +1118,11 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8
bank)
if (!pwrdm)
return ret;
- if (pwrdm-banks (bank + 1))
+ if (pwrdm-banks (bank + 1)) {
+ pr_err_ratelimited(%s: powerdomain %s: bad bank %d\n,
+ __func__, pwrdm-name, bank);
[PATCH 5/8] ARM: OMAP2+: PM: use power domain functional state in stats counters
The PM code uses some counters to keep track of the power domains
transitions, in order to provide the information to drivers (in
pwrdm_get_context_loss_count) and to expose the information to
sysfs for debug purpose.
This patch provides the information for each functional state.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/pm-debug.c| 15 ---
arch/arm/mach-omap2/powerdomain.c | 12 ++--
arch/arm/mach-omap2/powerdomain.h |4 ++--
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 814bcd9..8eaa3f2 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -53,9 +53,10 @@ enum {
DEBUG_FILE_TIMERS,
};
-static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
+static const char pwrdm_state_names[][PWRDM_MAX_FUNC_PWRSTS] = {
OFF,
- RET,
+ OSWR,
+ CSWR,
INA,
ON
};
@@ -102,13 +103,13 @@ static int pwrdm_dbg_show_counter(struct powerdomain
*pwrdm, void *user)
strncmp(pwrdm-name, dpll, 4) == 0)
return 0;
- if (pwrdm-state != pwrdm_read_pwrst(pwrdm))
+ if (pwrdm-state != pwrdm_read_fpwrst(pwrdm))
printk(KERN_ERR pwrdm state mismatch(%s) %d != %d\n,
- pwrdm-name, pwrdm-state, pwrdm_read_pwrst(pwrdm));
+ pwrdm-name, pwrdm-state, pwrdm_read_fpwrst(pwrdm));
seq_printf(s, %s (%s), pwrdm-name,
pwrdm_state_names[pwrdm-state]);
- for (i = 0; i PWRDM_MAX_PWRSTS; i++)
+ for (i = 0; i PWRDM_MAX_FUNC_PWRSTS; i++)
seq_printf(s, ,%s:%d, pwrdm_state_names[i],
pwrdm-state_counter[i]);
@@ -137,7 +138,7 @@ static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm,
void *user)
seq_printf(s, %s (%s), pwrdm-name,
pwrdm_state_names[pwrdm-state]);
- for (i = 0; i 4; i++)
+ for (i = 0; i PWRDM_MAX_FUNC_PWRSTS; i++)
seq_printf(s, ,%s:%lld, pwrdm_state_names[i],
pwrdm-state_timer[i]);
@@ -211,7 +212,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm,
void *dir)
t = sched_clock();
- for (i = 0; i 4; i++)
+ for (i = 0; i PWRDM_MAX_FUNC_PWRSTS; i++)
pwrdm-state_timer[i] = 0;
pwrdm-timer = t;
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 1f9ed2c..6b8580b 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -106,7 +106,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
list_add(pwrdm-node, pwrdm_list);
/* Initialize the powerdomain's state counter */
- for (i = 0; i PWRDM_MAX_PWRSTS; i++)
+ for (i = 0; i PWRDM_MAX_FUNC_PWRSTS; i++)
pwrdm-state_counter[i] = 0;
pwrdm-ret_logic_off_counter = 0;
@@ -114,7 +114,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
pwrdm-ret_mem_off_counter[i] = 0;
pwrdm_wait_transition(pwrdm);
- pwrdm-state = pwrdm_read_pwrst(pwrdm);
+ pwrdm-state = pwrdm_read_fpwrst(pwrdm);
pwrdm-state_counter[pwrdm-state] = 1;
pr_debug(powerdomain: registered %s\n, pwrdm-name);
@@ -149,17 +149,17 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm,
int flag)
if (pwrdm == NULL)
return -EINVAL;
- state = pwrdm_read_pwrst(pwrdm);
+ state = pwrdm_read_fpwrst(pwrdm);
switch (flag) {
case PWRDM_STATE_NOW:
prev = pwrdm-state;
break;
case PWRDM_STATE_PREV:
- prev = pwrdm_read_prev_pwrst(pwrdm);
+ prev = pwrdm_read_prev_fpwrst(pwrdm);
if (pwrdm-state != prev)
pwrdm-state_counter[prev]++;
- if (prev == PWRDM_POWER_RET)
+ if (prev == PWRDM_FUNC_PWRST_OSWR)
_update_logic_membank_counters(pwrdm);
/*
* If the power domain did not hit the desired state,
@@ -1367,7 +1367,7 @@ int pwrdm_get_context_loss_count(struct powerdomain
*pwrdm)
return -ENODEV;
}
- count = pwrdm-state_counter[PWRDM_POWER_OFF];
+ count = pwrdm-state_counter[PWRDM_FUNC_PWRST_OFF];
count += pwrdm-ret_logic_off_counter;
for (i = 0; i pwrdm-banks; i++)
diff --git a/arch/arm/mach-omap2/powerdomain.h
b/arch/arm/mach-omap2/powerdomain.h
index 23b9da9..df83c7c 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -146,7 +146,7 @@ struct powerdomain {
struct list_head voltdm_node;
spinlock_t lock;
int state;
- unsigned state_counter[PWRDM_MAX_PWRSTS];
+ unsigned state_counter[PWRDM_MAX_FUNC_PWRSTS];
unsigned ret_logic_off_counter
