* Tarun Kanti DebBarma tarun.ka...@ti.com [110920 03:57]:
@@ -254,9 +259,15 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer);
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
int posted)
{
- if (posted)
Let's leave out these changes for now, they make the
omap2_gp_timer_set_next_event used for system timer interrupts
huge if you take a look at it with objdump.
Later on we might want to split the posted bit check into a separate
inline function, and then you can implement this for the device
The low-level read and write access routines wait on write-pending register
in posted mode to make sure that previous write is complete on respective
registers. This waiting is done in an infinite while loop. Now it is being
modified to use timeout instead.
Signed-off-by: Tarun Kanti DebBarma
