-Original Message-
From: Tony Lindgren [mailto:t...@atomide.com]
Sent: Tuesday, January 25, 2011 10:28 PM
To: Ghorai, Sukumar
Cc: linux-omap@vger.kernel.org; linux-...@lists.infradead.org; linux-arm-
ker...@lists.infradead.org
Subject: Re: [PATCH RESEND v8 3/7] omap: gpmc: enable
snip
+
+static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq,
+ int dir)
+{
+ struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
+ struct clk *dmic_clk, *parent_clk;
On Thu, 2011-01-27 at 18:59 +, Russell King - ARM Linux wrote:
On Thu, Jan 27, 2011 at 06:14:56PM +, Catalin Marinas wrote:
On 17 January 2011 19:24, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Rather than turning off CPU domain switching when the build architecture
On Fri, Jan 28, 2011 at 09:46:06AM +, Catalin Marinas wrote:
Does this mean that we could still configure a kernel to run on CPU_V6
with domains disabled? The vectors page becomes read-only and setting
the TLS would fail.
Yes it will, so that's not acceptable either.
My point is that we
The following set of patches applies on linux-2.6.
The main motivations behind this patch series are -
1. support NAND I/O in irq mode.
2. support of different ECC schema.
3. also add support ecc layout as like in romcode ecc layout, but not
enabled
v9: gpmc_init()
zoom3 and 3630-sdp having the x16 nand device.
This patch configure gpmc as x16 and select the currect function in driver
for polled mode (without prefetch enable) transfer.
Signed-off-by: Sukumar Ghorai s-gho...@ti.com
---
arch/arm/mach-omap2/board-3430sdp.c |2 +-
nand transfer type (sDMA, Polled, prefetch) can be select from board file,
enabling all transfer type in driver, by default.
this helps in multi-omap build and to select different transfer type for
different board.
Signed-off-by: Sukumar Ghorai s-gho...@ti.com
---
add support the irq mode in GPMC.
gpmc_init() function move after omap_init_irq() as it has dependecy on irq.
Signed-off-by: Sukumar Ghorai s-gho...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 45 +--
arch/arm/mach-omap2/io.c |2 -
This patch makes it possible to select sw or hw (different layout options)
ecc scheme supported by omap nand driver.
Signed-off-by: Vimal Singh vimalsi...@ti.com
Signed-off-by: Sukumar Ghorai s-gho...@ti.com
---
arch/arm/mach-omap2/board-flash.c |1 +
This patch overrides nand ecc layout and bad block descriptor (for 8-bit
device) to support hw ecc in romcode layout. So as to have in sync with ecc
layout throughout; i.e. x-loader, u-boot and kernel.
This enables to flash x-loader, u-boot, kernel, FS images from kernel itself
and compatiable
Configure the FIFO THREASHOLD value different for read and write to keep busy
both filling and to drain out of FIFO at reading and writing.
Signed-off-by: Vimal Singh vimalsi...@ti.com
Signed-off-by: Sukumar Ghorai s-gho...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 11 +++
This patch enable prefetch-irq mode for nand transfer(read, write)
Signed-off-by: Vimal Singh vimalsi...@ti.com
Signed-off-by: Sukumar Ghorai s-gho...@ti.com
---
arch/arm/mach-omap2/board-flash.c |2 +
arch/arm/plat-omap/include/plat/nand.h |4 +-
drivers/mtd/nand/omap2.c
On Fri, 2011-01-28 at 09:59 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 09:46:06AM +, Catalin Marinas wrote:
My point is that we may want SWP_EMULATE disabled (or depending on !
CPU_USE_DOMAINS). With domains enabled every read-only user page is
writeable by the
From: Rajendra Nayak rna...@ti.com
Enable all DPLL autoidle at boot on OMAP4.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/clock44xx_data.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
The series mainly contains dpll initialisation, CPUx clock
domain offset fix, addiing INACTIVE power domain state and
fixing logic flag for IVAHD and ABE power domains.
The series is boot tested on OMAP4430 SDP.
The following changes since commit 1bae4ce27c9c90344f23c65ea6966c50ffeae2f5:
Linus
CPU0 and CPU1 clockdomain is at the offset of 0x18 from the LPRM base.
The header file has set it wrongly to 0x0. Offset 0x0 is for CPUx power
domain control register
Fix the same.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
IVAHD and ABE power domain logic state is populated using directly
value instead of the capability flags.
Fix the same.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/powerdomains44xx_data.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff
From: Rajendra Nayak rna...@ti.com
Enable auto/hw gate control for all dpll MX postdividers.
This requires the corresponding CLOCK_MX_IDLE_CONTROL to
be populated for all respective clock nodes.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/clock44xx_data.c | 22
On OMAP4, one can explicitly program INACTIVE as the power state of
the logic area inside the power domain. Techincally PD state programmed
to ON and if all the clock domains within the PD are idled, is equivalent
tp PD programmed to INACTIVE and all the clock domains within the PD are
idled.
From: Rajendra Nayak rna...@ti.com
On OMAP4, the dpll post divider outputs (MX outputs)
provide a way to allow/deny autoidle.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to
On Fri, Jan 28, 2011 at 10:46:51AM +, Catalin Marinas wrote:
On Fri, 2011-01-28 at 09:59 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 09:46:06AM +, Catalin Marinas wrote:
My point is that we may want SWP_EMULATE disabled (or depending on !
CPU_USE_DOMAINS). With
The _add_optional_clock_alias function expects an entry
already existing in the clkdev table in the form of
dev-id=NULL, con-id=role which might not be the case
always.
Instead, just check if an entry already exists in clkdev
in the dev-id=dev_name, con-id=role form, else go ahead
and add one.
On Tue, 2011-01-25 at 09:03 -0800, ext Tony Lindgren wrote:
* Kevin Hilman khil...@ti.com [110124 13:56]:
Sumit Semwal sumit.sem...@ti.com writes:
v10 of the patch series corrects return-error handling from
platform_request_irq()
based on comments from Sergei Shtylyov and Russell
On Fri, 2011-01-28 at 11:06 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 10:46:51AM +, Catalin Marinas wrote:
On Fri, 2011-01-28 at 09:59 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 09:46:06AM +, Catalin Marinas wrote:
My point is that we may
-Original Message-
From: Santosh Shilimkar [mailto:santosh.shilim...@ti.com]
Sent: Friday, January 28, 2011 4:35 PM
To: linux-omap@vger.kernel.org
Cc: khil...@ti.com; p...@pwsan.com; b-cous...@ti.com; rna...@ti.com;
linux-arm-ker...@lists.infradead.org; Santosh Shilimkar
Subject:
On Fri, Jan 28, 2011 at 12:25:18PM +, Catalin Marinas wrote:
On Fri, 2011-01-28 at 11:06 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 10:46:51AM +, Catalin Marinas wrote:
On Fri, 2011-01-28 at 09:59 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at
On Fri, 2011-01-28 at 13:05 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 12:25:18PM +, Catalin Marinas wrote:
With your latest patches, do we use the TLS emulation on ARMv7 (UP) if
v6 is compiled in? If that's the case, we may have a problem - I talked
to the toolchain
On Fri, Jan 28, 2011 at 12:25:18PM +, Catalin Marinas wrote:
On Fri, 2011-01-28 at 11:06 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 10:46:51AM +, Catalin Marinas wrote:
On Fri, 2011-01-28 at 09:59 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at
On Fri, Jan 28, 2011 at 01:10:56PM +, Catalin Marinas wrote:
On Fri, 2011-01-28 at 13:05 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 12:25:18PM +, Catalin Marinas wrote:
With your latest patches, do we use the TLS emulation on ARMv7 (UP) if
v6 is compiled in? If
Remove duplicated #include('s) in
arch/arm/mach-omap1/time.c
Signed-off-by: Huang Weiyi weiyi.hu...@gmail.com
---
arch/arm/mach-omap1/time.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index f83fc33..6885d2f
Free allocated memory on error exit.
Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com
---
arch/arm/mach-omap2/mux.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index df8d2f2..18aea0c 100644
---
On Fri, 2011-01-28 at 13:21 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 12:25:18PM +, Catalin Marinas wrote:
With your latest patches, do we use the TLS emulation on ARMv7 (UP) if
v6 is compiled in? If that's the case, we may have a problem - I talked
to the toolchain
The temporary string holding the directory name to be created should
be released.
Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com
---
arch/arm/mach-omap2/voltage.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/voltage.c
* Catalin Marinas catalin.mari...@arm.com [110128 07:11]:
On Fri, 2011-01-28 at 13:21 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 12:25:18PM +, Catalin Marinas wrote:
With your latest patches, do we use the TLS emulation on ARMv7 (UP) if
v6 is compiled in? If that's
* Ghorai, Sukumar s-gho...@ti.com [110128 00:14]:
-Original Message-
From: Tony Lindgren [mailto:t...@atomide.com]
Sent: Tuesday, January 25, 2011 10:28 PM
To: Ghorai, Sukumar
Cc: linux-omap@vger.kernel.org; linux-...@lists.infradead.org; linux-arm-
Sricharan wrote:
Use the mux framework to initialise the serial pads.
Signed-off-by: sricharan r.sricha...@ti.com
---
arch/arm/mach-omap2/board-omap4panda.c | 72
+++-
1 files changed, 71 insertions(+), 1 deletions(-)
diff --git
sricharan wrote:
1) All the pads of a hwmod for the device are classified
as static/dynamic. If a pad requires remuxing during
the device transitions between enable/idle transitions
then it is added to the dynamic list, static otherwise.
2) Both the static/dynamic pads of a hwmod
From: Nicole Chalhoub n-chalh...@ti.com
One criterion of C-states selection is based on the load factor. High
load prevents deep C-states. The load is evaluated and updated at
each scheduler tick, and thus not updated when in tickless mode. As a
result, the CPU load calculated on the tick just
Ricardo Salveti de Araujo ricardo.salv...@canonical.com writes:
In case in user has a OMAP3630 ES1.2 the kernel should warn the user
about the ERRATUM, but using printk instead of WARN_ON is already
enough, as there is nothing else the user can do besides changing the
board.
I agree, it
Aaro Koskinen aaro.koski...@nokia.com writes:
The temporary string holding the directory name to be created should
be released.
Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com
Thanks, queuing in pm-fixes for 2.6.38.
Kevin
---
arch/arm/mach-omap2/voltage.c |1 +
1 files
I have a tsc2004 touch controller on I2C3 that is powered by vaux1, and since
its probed I have to turn the power on before it can be probed. I've created:
static struct regulator_consumer_supply dm3730logic_vaux1_supply = {
.supply= vaux1,
};
/* VAUX1 for touch chip */
static
Hi Vishwa,
Vishwanath BS vishwanath...@ti.com writes:
From: Thara Gopinath th...@ti.com
In OMAP3, for perfomrance reasons when VDD1 is at voltage above
1.075V, VDD2 should be at 1.15V for perfomrance reasons. This
patch introduce this cross VDD dependency for OMAP3 VDD1.
Signed-off-by:
Is there any reason, to date, that the ARM architecture has not had the
following kernel configuration option?
config GENERIC_CMOS_UPDATE
def_bool y
Regards,
Grant
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