+ samsung soc mailing list
On Wed, Oct 16, 2013 at 12:52:42AM +0200, Tomasz Figa wrote:
Hi Charles,
On Tuesday 15 of October 2013 13:26:22 Charles Keepax wrote:
ALIAS(SCLK_MMC1, s3c-sdhci.1, mmc_busclk.2),
ALIAS(SCLK_MMC0, s3c-sdhci.0, mmc_busclk.2),
- ALIAS(SCLK_SPI1,
On Wednesday 16 of October 2013 09:10:35 Charles Keepax wrote:
+ samsung soc mailing list
On Wed, Oct 16, 2013 at 12:52:42AM +0200, Tomasz Figa wrote:
Hi Charles,
On Tuesday 15 of October 2013 13:26:22 Charles Keepax wrote:
ALIAS(SCLK_MMC1, s3c-sdhci.1, mmc_busclk.2),
Hi Shaik,
I tried to build your driver. It does not compile, so please fix it.
CC drivers/media/platform/exynos-scaler/scaler-m2m.o
drivers/media/platform/exynos-scaler/scaler-m2m.c: In function
'scaler_m2m_open':
drivers/media/platform/exynos-scaler/scaler-m2m.c:616:2: error: implicit
Hi,
On Wednesday, October 16, 2013 08:21:30 AM Naveen Krishna Chatradhi wrote:
On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 on INTEN, INTSTAT registers and at an offset of
12 on INTCLEAR register.
On Exynos5420, the FALL interrupt
Hi Tomasz,
On Wed, Oct 16, 2013 at 12:19 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Leela,
On Tuesday 15 of October 2013 16:50:53 Leela Krishna Amudala wrote:
Add clock nodes for oscillator clock, input clocks and parents of input
clocks to gsc power domain so that we can set/restore
Hi Tomasz,
On Wed, Oct 16, 2013 at 12:21 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Leela,
On Tuesday 15 of October 2013 16:50:54 Leela Krishna Amudala wrote:
Adds G-Scaler devices to the DT device list
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
On Wed, Oct 16, 2013 at 3:38 PM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Hi Tomasz,
On Wed, Oct 16, 2013 at 12:21 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Leela,
On Tuesday 15 of October 2013 16:50:54 Leela Krishna Amudala wrote:
Adds G-Scaler devices to the DT device list
On Wednesday 16 of October 2013 15:46:21 Leela Krishna Amudala wrote:
On Wed, Oct 16, 2013 at 3:38 PM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Hi Tomasz,
On Wed, Oct 16, 2013 at 12:21 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Leela,
On Tuesday 15 of October 2013
On Wed, Oct 16, 2013 at 11:10:59AM +0200, Tomasz Figa wrote:
If you have hardware to test this, especially with possibility of checking
the SPI frequency I would really appreciate this, as I unfortunately don't
have such.
I might not be able to get around to it this week, but I
certainly
Adds G-Scaler devices to the DT device list
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index
[ I was a bit too quick with hitting the Send button.. ]
On Wednesday, October 16, 2013 12:06:21 PM Bartlomiej Zolnierkiewicz wrote:
Hi,
On Wednesday, October 16, 2013 08:21:30 AM Naveen Krishna Chatradhi wrote:
On Exynos5250, the FALL interrupt related en, status and clear bits are
As of now, part of Exynos4 clock suspend/resume handling is located
in mach-exynos/pm.c, which is not where code accessing CMU registers
should reside.
This patch implements all the necessary suspend/resume handling code
in Exynos4 clock driver to allow dropping that old code.
Signed-off-by:
This series reworks suspend/resume handling of Samsung clock drivers
to cover more SoC specific aspects that are beyond simple register
save and restore. The goal is to have all the suspend/resume code
that touches the clock controller in single place, which is the
clock driver.
On
As suspend/resume handlers are being moved to SoC specific code, due to
differencies in suspend/resume handling of particular SoCs, to minimize
code duplication this patch provides common register save/restore
helpers that save/restore given list of registers of clock controller.
Signed-off-by:
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
This patch simplifies a bit clock initialization code by removing
remnants of non-DT clock initialization, such as reg_base and xom values
passed in function parameters.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
All the suspend/resume handling is already implemented in Exynos4 clock
driver, so this legacy code can be safely dropped.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/pm.c | 125
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Since all SoC drivers have been moved to local suspend/resume handling,
the old code can be safely dropped.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 2 +-
drivers/clk/samsung/clk-exynos5250.c
From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
ow...@vger.kernel.org] On Behalf Of Sylwester Nawrocki
Sent: Saturday, October 12, 2013 2:32 PM
Subject: [PATCH RFC v2 03/10] exynos4-is: Use mem-to-mem ioctl helpers
Simplify the FIMC mem-to-mem driver by using the m2m ioctl and
From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
ow...@vger.kernel.org] On Behalf Of Sylwester Nawrocki
Sent: Saturday, October 12, 2013 2:32 PM
Subject: [PATCH RFC v2 04/10] s5p-jpeg: Use mem-to-mem ioctl helpers
Simplify the driver by using the m2m ioctl and vb2 helpers.
From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
ow...@vger.kernel.org] On Behalf Of Sylwester Nawrocki
Sent: Saturday, October 12, 2013 2:32 PM
Subject: [PATCH RFC v2 10/10] s5p-g2d: Use mem-to-mem ioctl helpers
Simplify the driver by using the m2m ioctl and vb2 helpers.
From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
ow...@vger.kernel.org] On Behalf Of Sylwester Nawrocki
Sent: Saturday, October 12, 2013 2:32 PM
Subject: [PATCH RFC v2 02/10] mem2mem_testdev: Use mem-to-mem ioctl and
vb2 helpers
Simplify the driver by using the m2m ioctl and
From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
ow...@vger.kernel.org] On Behalf Of Sylwester Nawrocki
Sent: Saturday, October 12, 2013 2:39 PM
Subject: [PATCH RFC v2.1 01/10] V4L: Add mem2mem ioctl and file
operation helpers
This patch adds ioctl helpers to the V4L2
Hi Leela,
On Wednesday 16 of October 2013 16:26:26 Leela Krishna Amudala wrote:
Adds G-Scaler devices to the DT device list
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 20
1 file changed, 20 insertions(+)
Now
From: Lukasz Majewski l.majew...@samsung.com
To make the driver multiplatform-friendly, unconditional initialization
in an initcall is replaced with a platform driver probed only if
respective platform device is registered.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by:
From: Jingoo Han jg1@samsung.com
Exynos Display Port can be used only for Exynos SoCs. In addition,
non-DT for EXYNOS SoCs is not supported from v3.11; thus, there is
no need to support non-DT for Exynos Display Port.
The 'include/video/exynos_dp.h' file has been used for non-DT
support and
From: Sylwester Nawrocki sylvester.nawro...@gmail.com
Use the generic PHY API instead of the platform callback
for the MIPI DSIM DPHY enable/reset control.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Acked-by: Felipe Balbi
From: Sylwester Nawrocki sylvester.nawro...@gmail.com
Generic PHY drivers are used to handle the MIPI CSIS and MIPI DSIM
DPHYs so we can remove now unused code at arch/arm/plat-samsung.
In case there is any board file for S5PV210 platforms using MIPI
CSIS/DSIM (not any upstream currently) it
Hi Greg,
This series includes video PHY adaptation to Generic PHY Framework.
With the adaptation they were able to get rid of plat data callbacks.
Since you've taken the Generic PHY Framework, I think this series should
also go into your tree.
We should thank Sylwester for actively testing and
From: Jingoo Han jg1@samsung.com
Use the generic PHY API to control the DP PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/video/exynos_dp.txt | 17
From: Sylwester Nawrocki sylvester.nawro...@gmail.com
Use the generic PHY API instead of the platform callback
to control the MIPI CSIS DPHY.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Acked-by: Felipe Balbi ba...@ti.com
From: Jingoo Han jg1@samsung.com
Add a PHY provider driver for the Samsung Exynos SoC Display Port PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Felipe Balbi ba...@ti.com
Signed-off-by:
From: Sylwester Nawrocki sylvester.nawro...@gmail.com
Add a PHY provider driver for the Samsung S5P/Exynos SoC MIPI CSI-2
receiver and MIPI DSI transmitter DPHYs.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Kishon
Fix argument passed to the register setup helper function so
the phy is actually disabled. Now due to cutpaste error 1 is
passed to both phy_power_on() and phy_power_off().
Reported by: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
This
Hi Kukjin,
On Saturday 28 of September 2013 19:49:14 Tomasz Figa wrote:
All S3C64XX SoCs come with ARM1176JZF-s core, which fully supports
ARMv6K extensions. This patch lets the kernel use them on S3C6410 by
adding selection of CPU_V6K to ARCH_S3C64XX.
Signed-off-by: Tomasz Figa
Hi Kukjin,
On Sunday 29 of September 2013 18:12:01 Tomasz Figa wrote:
According to board schematics, for HSMMC1 a GPIO line is used to detect
card presence, while currently it is being configured for internal card
detect line, which is multiplexed with card detect line of HSMMC0 and
thus
Since the patches extending support of amba-pl08x DMA engine driver to
PL080S DMA engine (PL080 modified by Samsung) found in Samsung S3C64xx
SoCs got merged into Linux 3.12, it is a good time to migrate the
platform to use this driver and drop the legacy DMA code.
Due to changes scattered across
This patch adds all required platform-specific data and initialization
code to support the generic amba-pl08x driver on S3C64xx SoCs.
Also some compatibility definitions are added to make the transition
from legacy API to DMA engine easier. The biggest hack here is passing
const char * pointers
Since support for generic PL08x DMA engine driver has been added, there
is no need to keep the old legacy driver, so this patch removes it.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
arch/arm/mach-s3c64xx/Kconfig| 5 -
arch/arm/mach-s3c64xx/Makefile | 1 -
This patch adds clkdev aliases for clocks used by PL08x DMA driver.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/clk/samsung/clk-s3c64xx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/samsung/clk-s3c64xx.c
b/drivers/clk/samsung/clk-s3c64xx.c
index
With support for amba-pl08x driver, on S3C64xx the generic DMA engine
API can be used instead of the private s3c-dma interface.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
sound/soc/samsung/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
With support for amba-pl08x driver, on S3C64xx the generic DMA engine
API can be used instead of the private s3c-dma interface.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig
Since the old DMA driver got removed, these aliases are no longer
necessary.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/clk/samsung/clk-s3c64xx.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-s3c64xx.c
b/drivers/clk/samsung/clk-s3c64xx.c
index
The legacy S3C64xx DMA driver has been removed, DMA support on
S3C64xx is provided only by the generic PL08x driver.
This patch modifies the Kconfig entry of Samsung ASoC subsystem, which
relies on availability of DMA, to always select the S3C64XX_PL080
symbol.
Signed-off-by: Tomasz Figa
The legacy S3C64xx DMA driver has been removed, DMA support on
S3C64xx is provided only by the generic PL08x driver.
This patch modifies the Kconfig entry of spi-s3c64xx driver, which
relies on availability of DMA, to always select the S3C64XX_PL080
symbol.
Signed-off-by: Tomasz Figa
On Wed, Oct 16, 2013 at 09:58:09PM +0530, Kishon Vijay Abraham I wrote:
Hi Greg,
This series includes video PHY adaptation to Generic PHY Framework.
With the adaptation they were able to get rid of plat data callbacks.
Since you've taken the Generic PHY Framework, I think this series
откорректируйте зрение без проблем http://teling.by/bitrix/images/cbqgp.htm
Vyacheslav Tyrtov v.tyr...@samsung.com writes:
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture.
Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
Patches add new platform
On Thursday, October 17, 2013 2:04 AM, Sylwester Nawrocki wrote:
Fix argument passed to the register setup helper function so
the phy is actually disabled. Now due to cutpaste error 1 is
passed to both phy_power_on() and phy_power_off().
Reported by: Kyungmin Park kyungmin.p...@samsung.com
On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.
On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT and
This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
Also updated the Documentation at
Documentation/devicetree/bindings/thermal/exynos-thermal.txt
Note: The platform data structure
Adds G-Scaler device nodes to the DT device list
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
Changes since V1:
- Changed the patch subject
- Changed the node name to video-scaler
suggested by Tomasz Figa t.f...@samsung.com
Note: G-scaler probe test
55 matches
Mail list logo
