On Wed, Jul 16, 2014 at 11:23:09AM +0900, YoungJun Cho wrote:
Hi Inki,
On 07/15/2014 11:34 AM, Inki Dae wrote:
On 2014년 07월 14일 20:03, Thierry Reding wrote:
On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote:
On 07/14/2014 06:41 PM, Thierry Reding wrote:
[...]
That said, I've
The host controller by itself may sometimes need to handle PHY
and/or calibrate some of the PHY settings to get full support out
of the PHY controller. The PHY core provides a calibration
funtionality now to do so.
Therefore, facilitate getting the two possible PHYs, viz.
USB 2.0 type (UTMI+) and
On Exynos4 USE_DELAYED_RESET_ASSERTION must be set in
ARM_COREx_OPTION register during CPU power down. This is the proper way
of powering down CPU on Exynos4.
Additionally on Exynos4212 without this the CPU clock down feature won't
work after powering down some CPU and the online CPUs will work
Increase max i2c bus frequency beyond the default for faster
data transfers. According to the manual, these faster speeds are
only available when the board is wired up the right way. In this case,
the vendor kernel has run at this speed for a long time.
sda-delay is needed for talking to RTC on
The ODROID kernel shows that the PMIC interrupt line is hooked up
to pin GPX3-2.
This is needed for the max77686-irq driver to create the PMIC IRQ
domain, which is needed by max77686-rtc.
Signed-off-by: Daniel Drake dr...@endlessm.com
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 11
(-)
This just entered linux-next (see next-20140716).
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 36c7747..cae8ebd 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -47,10 +47,6 @@
#include asm/irq.h
-#ifdef CONFIG_SAMSUNG_CLOCK
, as s5pv210 was their last user.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
This one also landed in today's linux-next (ie, next-20140716).
[...]
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h
b/arch/arm/mach-s5pv210/include/mach/gpio.h
deleted file mode 100644
index 6c8b903..000
On Fri, 2014-07-04 at 19:48 +0200, Tomasz Figa wrote:
Since all in-tree boards have been moved to device tree, we can now drop
legacy code and make mach-s5pv210 DT-only. This patch does it.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
This patch showed up in next-20140716 too
Hi Thierry,
On 07/16/2014 04:54 PM, Thierry Reding wrote:
On Wed, Jul 16, 2014 at 11:23:09AM +0900, YoungJun Cho wrote:
Hi Inki,
On 07/15/2014 11:34 AM, Inki Dae wrote:
On 2014년 07월 14일 20:03, Thierry Reding wrote:
On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote:
On 07/14/2014
, as s5pv210 was their last user.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
I noticed another thing now this patch showed up in next-20140716.
[...]
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8185b5..1091b0a 100644
--- a/arch/arm/plat-samsung/Kconfig
On Fri, 2014-07-04 at 19:48 +0200, Tomasz Figa wrote:
After refactoring suspend/resume, which was last part with dependencies
on legacy code, all Kconfig symbols related to Samsung ATAGS support can
be deselected and more unused code removed. This includes most of s5p-*
code as well, as
Hi Krzysztof,
Please see my comment below.
On 16.07.2014 10:23, Krzysztof Kozlowski wrote:
On Exynos4 USE_DELAYED_RESET_ASSERTION must be set in
ARM_COREx_OPTION register during CPU power down. This is the proper way
of powering down CPU on Exynos4.
Additionally on Exynos4212 without this
On śro, 2014-07-16 at 12:48 +0200, Tomasz Figa wrote:
Hi Krzysztof,
Please see my comment below.
On 16.07.2014 10:23, Krzysztof Kozlowski wrote:
On Exynos4 USE_DELAYED_RESET_ASSERTION must be set in
ARM_COREx_OPTION register during CPU power down. This is the proper way
of powering
Hi Krzysztof,
On 14.07.2014 09:45, Krzysztof Kozlowski wrote:
Fix building of exynos defconfig with disabled PM_SLEEP:
CONFIG_PM_SLEEP=n
CONFIG_PM_SLEEP_SMP=n
CONFIG_SUSPEND=n
by moving functions for power up/down of CPU and cluster to platsmp.c
The build error messages:
Hi Naveen,
On 14.07.2014 13:37, Naveen Krishna Chatradhi wrote:
This patch set does the following
1: Get fifosize from DT node. But, not mandating it.
2. Corrects the case and default order in a switch
3. Defines a variable to simply the code.
Console messages on Exynos5420 based peach pit
On Exynos4 USE_DELAYED_RESET_ASSERTION must be set in
ARM_COREx_OPTION register during CPU power down. This is the proper way
of powering down CPU on Exynos4.
Additionally on Exynos4212 without this the CPU clock down feature won't
work after powering down some CPU and the online CPUs will work
On 16.07.2014 10:50, Daniel Drake wrote:
Increase max i2c bus frequency beyond the default for faster
data transfers. According to the manual, these faster speeds are
only available when the board is wired up the right way. In this case,
the vendor kernel has run at this speed for a long time.
On 16.07.2014 10:50, Daniel Drake wrote:
The ODROID kernel shows that the PMIC interrupt line is hooked up
to pin GPX3-2.
This is needed for the max77686-irq driver to create the PMIC IRQ
domain, which is needed by max77686-rtc.
Signed-off-by: Daniel Drake dr...@endlessm.com
---
1 file changed, 4 deletions(-)
This just entered linux-next (see next-20140716).
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 36c7747..cae8ebd 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -47,10 +47,6 @@
#include
On 16.07.2014 12:04, Paul Bolle wrote:
On Fri, 2014-07-04 at 19:48 +0200, Tomasz Figa wrote:
[snip]
-
-config MACH_AQUILA
-bool Aquila
-select CPU_S5PV210
-select S3C_DEV_FB
-select S3C_DEV_HSMMC
-select S3C_DEV_HSMMC1
-select S3C_DEV_HSMMC2
-select
On 16.07.2014 11:47, Paul Bolle wrote:
On Fri, 2014-07-04 at 19:48 +0200, Tomasz Figa wrote:
[snip]
config SAMSUNG_GPIO_EXTRA
int Number of additional GPIO pins
default 128 if SAMSUNG_GPIO_EXTRA128
So a second order effect is that SAMSUNG_GPIO_EXTRA can now be removed.
Which
On 16.07.2014 12:15, Paul Bolle wrote:
On Fri, 2014-07-04 at 19:48 +0200, Tomasz Figa wrote:
[snip]
-config PLAT_S5P
-bool
-depends on ARCH_S5PV210
-default y
-select ARCH_REQUIRE_GPIOLIB
-select ARM_VIC
-select NO_IOPORT_MAP
-select PLAT_SAMSUNG
-select
On 16.07.2014 12:24, Paul Bolle wrote:
On Fri, 2014-07-04 at 19:48 +0200, Tomasz Figa wrote:
[snip]
-config S5P_GPIO_DRVSTR
-bool
-help
- Internal configuration to get and set correct GPIO driver strength
- helper
-
This one is used (as a macro) in
Hi Krzysztof,
On 16.07.2014 14:07, Krzysztof Kozlowski wrote:
[snip]
+#ifdef CONFIG_SMP
+extern void exynos_clear_delayed_reset_assertion(u32 core_id);
+#endif
Is the ifdef really needed? The only difference it makes if the function
is used but not compiled in is that with it the
On śro, 2014-07-16 at 15:05 +0200, Tomasz Figa wrote:
Hi Krzysztof,
On 16.07.2014 14:07, Krzysztof Kozlowski wrote:
[snip]
+#ifdef CONFIG_SMP
+extern void exynos_clear_delayed_reset_assertion(u32 core_id);
+#endif
Is the ifdef really needed? The only difference it makes if the
Cleanup a little the SMP/hotplug code for Exynos by:
1. Moving completely all functions from hotplug.c into the platsmp.c;
2. Deleting the hotplug.c file.
After recent cleanups (e.g. 75ad2ab28f0f ARM: EXYNOS: use
v7_exit_coherency_flush macro for cache disabling) there was only CPU
power down
On Exynos4 USE_DELAYED_RESET_ASSERTION must be set in
ARM_COREx_OPTION register during CPU power down. This is the proper way
of powering down CPU on Exynos4.
Additionally on Exynos4212 without this the CPU clock down feature won't
work after powering down some CPU and the online CPUs will work
The __ref annotation for exynos_cpu_die() is not needed because the
function does not reference any __init/__exit symbol or call.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/mach-exynos/platsmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Jul 16, 2014, at 6:44 AM, Catalin Marinas wrote:
On 15 Jul 2014, at 15:53, Jungseok Lee jungseokle...@gmail.com wrote:
On Jul 15, 2014, at 7:41 AM, Catalin Marinas wrote:
On Mon, Jul 14, 2014 at 09:38:59PM +0100, Joel Schopp wrote:
I agree that these patches would be very useful. I just
On Wed, 2014-07-16 at 14:43 +0200, Tomasz Figa wrote:
On 16.07.2014 11:27, Paul Bolle wrote:
There are three further references to CONFIG_SAMSUNG_CLOCK in this file.
Those should be removed too, shouldn't they?
That's right. Apparently I missed them. I guess that's not critical,
though,
On Wed, 2014-07-16 at 16:26 +0200, Paul Bolle wrote:
On Wed, 2014-07-16 at 14:43 +0200, Tomasz Figa wrote:
That's right. Apparently I missed them. I guess that's not critical,
though, and could be done in separate patch, right?
This is not critical at all, so that's fine with me.
On 16.07.2014 16:35, Paul Bolle wrote:
On Wed, 2014-07-16 at 16:26 +0200, Paul Bolle wrote:
On Wed, 2014-07-16 at 14:43 +0200, Tomasz Figa wrote:
That's right. Apparently I missed them. I guess that's not critical,
though, and could be done in separate patch, right?
This is not critical at
On Wed, Jul 16, 2014 at 01:51:40PM +0530, Vivek Gautam wrote:
The host controller by itself may sometimes need to handle PHY
and/or calibrate some of the PHY settings to get full support out
of the PHY controller. The PHY core provides a calibration
funtionality now to do so.
Therefore,
Hello Mark,
The s3c64xx SPI driver DT binding is currently broken. Commit
3146bee (spi: s3c64xx: Added provision for dedicated cs pin)
added a new cs-gpio property and made it a requirement in
order to make the driver behave in the same way that it used to.
The motivation of the offending commit
From: Naveen Krishna Chatradhi ch.nav...@samsung.com
Samsung SPI driver now uses the generic SPI cs-gpios
binding so update the documentation accordingly.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
[javier.marti...@collabora.co.uk: split changes and improve commit message]
This reverts commit 3146beec21b64f4551fcf0ac148381d54dc41b1b.
This commit resulted in a DT backward compatibility breakage.
Some devices use the native chip select (CS) instead of a GPIO
pin to drive the CS line. But the SPI driver made it mandatory
to specify a GPIO pin in the SPI device node
From: Naveen Krishna Chatradhi ch.nav...@samsung.com
The s3c64xx SPI driver uses a custom DT binding to specify
the GPIO used to drive the chip select (CS) line instead of
using the generic cs-gpios property already defined in:
Documentation/devicetree/bindings/spi/spi-bus.txt.
It's unfortunate
Hello Javier,
On 16 July 2014 20:49, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Mark,
The s3c64xx SPI driver DT binding is currently broken. Commit
3146bee (spi: s3c64xx: Added provision for dedicated cs pin)
added a new cs-gpio property and made it a requirement
On 07/16/2014 06:02 PM, Mark Brown wrote:
On Wed, Jul 16, 2014 at 05:19:06PM +0200, Javier Martinez Canillas wrote:
*sigh* Yesterday Naveen submitted another, different, patch series also
attempting to improve things which I'm not seeing any reference to here.
Please coordinate with Naveen
On Wed, Jun 25, 2014 at 09:39:20AM -0700, Doug Anderson wrote:
The original code for the exynos i2c controller registered for the
noirq variants. However during review feedback it was moved to
SIMPLE_DEV_PM_OPS without anyone noticing that it meant we were no
longer actually noirq (despite
Hi,
On Friday, May 30, 2014 03:53:09 PM Bartlomiej Zolnierkiewicz wrote:
Hi,
On Friday, May 30, 2014 01:34:45 PM Tomasz Figa wrote:
Hi Daniel,
On 30.05.2014 11:30, Daniel Lezcano wrote:
On 04/24/2014 07:42 PM, Tomasz Figa wrote:
Hi Daniel,
Please see my comments inline.
On Tue, Jun 24, 2014 at 04:56:54PM -0700, Doug Anderson wrote:
From: Vincent Palatin vpala...@chromium.org
When the wake-up is triggered by the PMIC RTC, the RTC driver is trying
to read the PMIC interrupt status over I2C and fails because the I2C
controller is not resumed yet.
Let's resume
On Wed, Jun 25, 2014 at 10:55:31AM -0700, Doug Anderson wrote:
Sachin,
On Wed, Jun 25, 2014 at 3:02 AM, Sachin Kamat sachin.ka...@samsung.com
wrote:
All Exynos5 platforms have HSI2C controllers and are needed by
various IPs connected to the boards based on these SoCs. Thus
select this
Wolfram,
On Wed, Jul 16, 2014 at 10:35 AM, Wolfram Sang w...@the-dreams.de wrote:
On Tue, Jun 24, 2014 at 04:56:54PM -0700, Doug Anderson wrote:
From: Vincent Palatin vpala...@chromium.org
When the wake-up is triggered by the PMIC RTC, the RTC driver is trying
to read the PMIC interrupt
On 2014년 07월 16일 19:12, YoungJun Cho wrote:
Hi Thierry,
On 07/16/2014 04:54 PM, Thierry Reding wrote:
On Wed, Jul 16, 2014 at 11:23:09AM +0900, YoungJun Cho wrote:
Hi Inki,
On 07/15/2014 11:34 AM, Inki Dae wrote:
On 2014년 07월 14일 20:03, Thierry Reding wrote:
On Mon, Jul 14, 2014 at
Hi Mike,
On Tue, Jul 15, 2014 at 9:20 AM, Thomas Abraham ta.oma...@gmail.com wrote:
Hi Tomasz,
On Mon, Jul 14, 2014 at 7:08 PM, Thomas Abraham thomas...@samsung.com wrote:
Changes since v6:
- Fixes suggested by Amit Daniel amit.dan...@samsung.com.
This patch series removes the use of
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