Hi Bart,
Thanks for your review.
On 08/28/2017 09:15 PM, Bart Van Assche wrote:
> On Mon, 2017-08-28 at 17:49 +0530, Alim Akhtar wrote:
>> This entire file uses UFS_BIT macro for bits definition, expect for few
>> places. This patch convert those defines to use UFS_BIT macr
reviewing over head.
I am floating these as a new patch set.
[1] https://www.spinics.net/lists/linux-scsi/msg90292.html
These patches are based on mainline v4.17-rc3.
Alim Akhtar (4):
scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
scsi: ufs: add quirk not to allow reset of interrupt
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon <ess...@gmail.com>
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 75 +--
drivers/scsi/ufs/ufshcd.h
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host controller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon <ess...@gmail.com>
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.
Signed-off-by: Seungwon Jeon <ess...@gmail.com>
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 5 ++---
drivers/scsi/ufs/ufshcd.h | 2 ++
2 file
Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.
Signed-off-by: Seungwon Jeon <ess...@gmail.com>
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 3 ++-
drivers/scsi/ufs/ufshcd.h | 6 +++
work as HCI has only 36bit addressing and SMMU has created mapping of
64 bit and as the device truncates the address, its mapping will not
be found by iommu.
To resolve such issues, let the variant driver sets its own DMA mask.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
driver
Hi Subhash
On 05/17/2018 03:01 AM, Subhash Jadavani wrote:
> On 2018-05-15 21:31, Alim Akhtar wrote:
>> Ping !!!
>>
>> On Thu, Mar 8, 2018 at 4:33 PM, Alim Akhtar <alim.akh...@samsung.com>
>> wrote:
>>> Currently DMA mask for UFS HCI is set by readi
Hi All,
Any thought on this patch set?
On Sun, May 6, 2018 at 3:44 PM, Alim Akhtar <alim.akh...@samsung.com> wrote:
> Hi All
>
> These patches are part of a larger patch series [1] which attempts upstreaming
> EXYNOS UFS driver support. There was not much activities after v
Ping !!!
On Thu, Mar 8, 2018 at 4:33 PM, Alim Akhtar <alim.akh...@samsung.com> wrote:
> Currently DMA mask for UFS HCI is set by reading CAP register's
> [64AS] bit. Some HCI controller like Exynos support 36-bit bus address.
> This works perfectly fine with DMA mask se
Hi Bart
On 05/20/2018 07:51 PM, Bart Van Assche wrote:
> On Sun, 2018-05-20 at 07:54 +0530, Alim Akhtar wrote:
>> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
>> index a355d98..9a1374e 100644
>> --- a/drivers/scsi/ufs/ufshcd.c
>> +++ b/drivers/scsi
work as HCI has only 36bit addressing and SMMU has created mapping of
64 bit and as the device truncates the address, its mapping will not
be found by iommu.
To resolve such issues, let the variant driver sets its own DMA mask.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
driver
work as HCI has only 36bit addressing and SMMU has created mapping of
64 bit and as the device truncates the address, its mapping will not
be found by iommu.
To resolve such issues, let the variant driver sets its own DMA mask.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
driver
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