On 3/28/24 06:57, Mathieu Desnoyers wrote:
> On 2024-03-28 01:39, Vineet Gupta wrote:
>> Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing()
>> across all architectures")
>>
>> Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
>> at least).
>>
On 2024-03-28 01:39, Vineet Gupta wrote:
Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing() across
all architectures")
Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).
Legacy ARC700 cpus could be VIPT aliasing (based on cache
Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing()
across all architectures")
Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).
Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) however recently that