he fix.
Reviewed-by: Joseph Lo <jose...@nvidia.com>
Please note that I have not encountered any problems without this change
so far, but I noticed this from reviewing the suspend sequence. I have
tested this on tegra20, tegra30, tegra114 and tegra124 and verified that
suspend/resume to LP1 is
On 03/11/2015 04:34 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Mar 09, 2015 at 10:31:41AM +0800, Joseph Lo wrote:
Expending the usage for both Tegra Tegra64 SoCs.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/tegra.c | 31
Oops, sorry for typo. Thanks, Uwe.
On 03/12/2015 12:22 AM, Uwe Kleine-König wrote:
On Mon, Mar 09, 2015 at 10:31:41AM +0800, Joseph Lo wrote:
Expending the usage for both Tegra Tegra64 SoCs.
Expanding? Mabe better: Moving this code to drivers/soc/tegra allows the
aarch64 SoCs to use it, too
Hi Thierry,
On 06/27/2014 04:49 AM, Thierry Reding wrote:
[snip]
+
+#define MC_INTSTATUS 0x000
+#define MC_INT_DECERR_MTS (1 16)
+#define MC_INT_SECERR_SEC (1 13)
+#define MC_INT_DECERR_VPR (1 12)
+#define MC_INT_INVALID_APB_ASID_UPDATE (1 11)
+#define MC_INT_INVALID_SMMU_PAGE (1 10)
/resume via RTC
wakealarm IRQ)
Joseph, if you see any issue here, please respond. Thanks.
Thanks for taking care of this. LGTM.
Reviewed-by: Joseph Lo jose...@nvidia.com
--
To unsubscribe from this list: send the line unsubscribe linux-tegra in
the body of a message to majord...@vger.kernel.org
On 02/13/2014 03:39 AM, Stephen Warren wrote:
On 02/11/2014 02:21 PM, Stefan Agner wrote:
Am 2014-02-11 21:47, schrieb Thierry Reding:
On Tue, Feb 11, 2014 at 09:11:32PM +0100, Stefan Agner wrote:
Trigger type needs to be IRQ_TYPE_LEVEL_HIGH since the interrupt
signal gets inverted by the PMC
On Thu, 2013-12-19 at 03:30 +0800, Mike Turquette wrote:
Quoting Stephen Warren (2013-12-18 10:28:32)
On 12/18/2013 02:42 AM, Joseph Lo wrote:
On Wed, 2013-12-18 at 06:58 +0800, Stephen Warren wrote:
On 12/17/2013 02:26 AM, Joseph Lo wrote:
Add External Memory Controller (EMC) clock
On Wed, 2013-12-18 at 06:53 +0800, Stephen Warren wrote:
On 12/17/2013 02:26 AM, Joseph Lo wrote:
This patch moves the tegra_btc_strapping variable to the tegra-soc.h for
the global visibility that the other Tegra device driver can access it.
It also a preparation that we can move out
This patch moves out the Tegra20 EMC driver from mach-tegra to the
drivers/memory folder. And register the EMC driver to the EMC interface
of the Tegra CCF driver.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
arch/arm/mach-tegra/Makefile
The EMC scaling function was lost after Tegra deprecated the legacy
clock driver and switched to CCF driver. In this series, we add the EMC
clock driver in the Tegra CCF driver. And re-register the EMC driver to
the EMC clock driver to support EMC scaling again.
Verified on Seaboard.
Joseph Lo
Add External Memory Controller (EMC) clock interface for the Tegra CCF
driver to support EMC scaling.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/tegra/Makefile | 1 +
drivers/clk/tegra/clk-emc.c | 183
This patch moves the tegra_btc_strapping variable to the tegra-soc.h for
the global visibility that the other Tegra device driver can access it.
It also a preparation that we can move out the Tegra20 EMC driver from
mach-tegra to the drivers folder.
Signed-off-by: Joseph Lo jose...@nvidia.com
Re-register the EMC clock to the EMC clock driver in the Tegra CCF
driver to support EMC scaling.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/tegra/clk-tegra20.c | 25 +++--
1 file changed, 15 insertions(+), 10
On Wed, 2013-10-16 at 18:48 +0800, Thierry Reding wrote:
On Tue, Oct 15, 2013 at 03:50:42PM -0600, Stephen Warren wrote:
On 10/15/2013 09:28 AM, Thierry Reding wrote:
-#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
I expect that was added deliberately. Perhaps Peter or Joseph can
On Thu, 2013-10-17 at 03:12 +0800, Thierry Reding wrote:
On Wed, Oct 16, 2013 at 10:31:11AM +0800, Joseph Lo wrote:
On Wed, 2013-10-16 at 05:50 +0800, Stephen Warren wrote:
On 10/15/2013 09:28 AM, Thierry Reding wrote:
Extend the list of power gates found on Tegra114. Note
On Wed, 2013-10-16 at 05:50 +0800, Stephen Warren wrote:
On 10/15/2013 09:28 AM, Thierry Reding wrote:
Extend the list of power gates found on Tegra114. Note that there are
now holes in the list, so perhaps a simple array is no longer the best
data structure to represent it. But perhaps
Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.
Cc: Mike Turquette mturque...@linaro.org
Signed-off-by: Joseph Lo jose...@nvidia.com
properties for devices of Tegra124
V2:
* fix the label name of not_ca9 in patch 3/4 of this series
Joseph Lo (4):
clk: tegra124: add wait_for_reset and disable_clock for
tegra_cpu_car_ops
ARM: tegra: CPU hotplug support for Tegra124
ARM: tegra: make tegra_resume can work with current
The CPUIdle function of Tegra124 is identical to Tegra114, so we share
the same driver with Tegra114.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* no change
---
arch/arm/mach-tegra/Makefile | 3 +++
arch/arm/mach-tegra/cpuidle.c | 4 +++-
2
The procedure of CPU hotplug for Tegra124 is same with Tegra114. We
re-use the same function with it.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* no change
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/hotplug.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch
This patch makes the Tegra RTC enabled as default for Tegra124 platform.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
Note:
This patch was based on the patch ARM: tegra: add clock properties for
devices of Tegra124 that already queued in linux-tegra.
---
arch/arm/boot/dts/tegra124.dtsi | 1
common to other chips.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* new in this series
---
arch/arm/mach-tegra/sleep-tegra30.S | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S
b/arch/arm/mach-tegra/sleep-tegra30.S
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* squash from 2/7 to 5/7 in V1
---
arch/arm/mach-tegra/Makefile| 1
of re-calculate the LP1 data for Tegra30/114
* squash the 2 to 5 into patch 3/4 of this series
Joseph Lo (4):
clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
ARM: tegra: re-calculate the LP1 data for Tegra30/114
ARM: tegra: add LP1 support code for Tegra124
ARM: tegra
Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette mturque...@linaro.org
Signed-off-by: Joseph Lo jose...@nvidia.com
Acked-by: Stephen Warren swar
On Wed, 2013-10-09 at 11:11 +0800, Joseph Lo wrote:
On Wed, 2013-10-09 at 01:00 +0800, Stephen Warren wrote:
On 10/08/2013 02:23 AM, Joseph Lo wrote:
diff --git a/arch/arm/mach-tegra/reset-handler.S
b/arch/arm/mach-tegra/reset-handler.S
not_ca9:
+ mov32 r9, 0xc0f
+ cmp
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/iomap.h | 3 +++
arch/arm/mach-tegra/sleep-tegra30.S
Enable LP1 suspend mode for Tegra124 Venice2 board.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/boot/dts/tegra124-venice2.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch/arm/boot/dts/tegra124-venice2.dts
index 279c7b5
Enable the Tegra RTC device on Venice2. It also can be used as a wakeup
device when platform suspended.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/boot/dts/tegra124-venice2.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch
for devices of Tegra124
* [PATCH 0/4] ARM: tegra: add CPU hot-plug and idle support for Tegra124
Verified on Cardhu, Dalmore and Venice2 and with THUMB2_KERNEL as well.
Joseph Lo (7):
clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
ARM: tegra: add flow controller to support
To support LP1, we need to hook sleep_core function. That will turn off
MMU and jump to the IRAM to execute the rest of LP1 suspend function.
And we need the the LP1 IRAM addr to backup the original content and
replace it with LP1 low level support code.
Signed-off-by: Joseph Lo jose
Hook the tegra_cpu_tear_down function for Tegra124 to support platform
suspend.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 36ed88a
Enable the configuration of flow controller to support the last CPU
(CPU0) suspend function with cluster power down.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/flowctrl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach
Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette mturque...@linaro.org
Signed-off-by: Joseph Lo jose...@nvidia.com
---
drivers/clk/tegra/clk-tegra124
On Wed, 2013-10-09 at 17:20 +0800, Joseph Lo wrote:
Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette mturque...@linaro.org
Signed-off-by: Joseph
This patch adds clock properties for devices in the DT for basic support
of Tegra124 SoC.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
This patch was based on the series of Tegra124 clock driver and the basic
support of Tegra124. It coulud be used to replace the HACK patch in the
basic support
properties for devices of Tegra124
Joseph Lo (4):
clk: tegra124: add wait_for_reset and disable_clock for
tegra_cpu_car_ops
ARM: tegra: CPU hotplug support for Tegra124
ARM: tegra: make tegra_resume can work with current and later chips
ARM: tegra: enable CPU idle for Tegra124
arch/arm
The procedure of CPU hotplug for Tegra124 is same with Tegra114. We
re-use the same function with it.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/hotplug.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/mach-tegra
Signed-off-by: Joseph Lo jose...@nvidia.com
---
This patch depends on the patch series [PATCH 0/5] Tegra124 clock support
that sent by Peter on 10/4/2013.
---
drivers/clk/tegra/clk-tegra124.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/clk/tegra/clk
cpu_resume.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/reset-handler.S | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-tegra/reset-handler.S
b/arch/arm/mach-tegra/reset-handler.S
index f527b2c..b63e69c 100644
--- a/arch/arm/mach-tegra
The CPUIdle function of Tegra124 is identical to Tegra114, so we share
the same driver with Tegra114.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/Makefile | 3 +++
arch/arm/mach-tegra/cpuidle.c | 4 +++-
2 files changed, 6
On Tue, 2013-10-08 at 16:23 +0800, Joseph Lo wrote:
The CPU hot-plug and idle function for Tegra124 was identical to Tegra114,
so we share the driver with it.
Because this series touches common CPU resume function across Tegra
chips, I forgot to mention.
Verified on Seaboard, Cardhu, Dalmore
On Wed, 2013-10-09 at 00:51 +0800, Stephen Warren wrote:
On 10/08/2013 02:23 AM, Joseph Lo wrote:
Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid
On Wed, 2013-10-09 at 01:00 +0800, Stephen Warren wrote:
On 10/08/2013 02:23 AM, Joseph Lo wrote:
Because the CPU0 was the first up and the last down core when cluster
power up/down or platform suspend. So only CPU0 needs the rest of the
functions to reset flow controller and re-enable SCU
Add tegra_chip_id 0x40 for Tegra124
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/fuse.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index def7968..c01d047 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm
Add Tegra124 SoC support that base on CortexA15MP Core.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/Kconfig | 8
arch/arm/mach-tegra/tegra.c | 1 +
2 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index
The power up method is same as Tegra114, so we share the same function
for it.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/platsmp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2d02036..eb72ae7
mmc ${mmc_dev}:${boot_part} ${kernel_addr_r} kernel.img
ext2load mmc ${mmc_dev}:${boot_part} ${ramdisk_addr_r} rootfs.img
ext2load mmc ${mmc_dev}:${boot_part} ${fdt_addr_r} tegra124-venice2.dtb
bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
Verified on Venice2.
Joseph Lo (7):
ARM: tegra
Initial support for Tegra 124 SoC. This is expected to be included in
the board DTS files.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/boot/dts/tegra124.dtsi | 132
1 file changed, 132 insertions(+)
create mode 100644 arch/arm/boot/dts
Add support for the Tegra124 based Venice2 reference board.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/tegra124-venice2.dts | 21 +
2 files changed, 23 insertions(+), 1 deletion(-)
create mode 100644
Add Tegra124 support in tegra_defconfig file.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index ec4f6e7..4934295 100644
--- a/arch/arm
This patch is only a hack for Tegra124 bring up testing. Please don't
merge this. The same function can be replaced by Tegra124 clock driver.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/boot/dts/tegra124.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot
On Tue, 2013-10-08 at 01:18 +0800, Stephen Warren wrote:
On 10/07/2013 01:31 AM, Joseph Lo wrote:
Initial support for Tegra 124 SoC. This is expected to be included in
the board DTS files.
The pmc node should also be fixed.
+ pmc {
+ compatible = nvidia,tegra124-pmc, nvidia
] ~ [v2 3/7] into the 1st patch in v2
* add PMC compatible value for Tegra124
* fix the device node name with address
* fix PMC compatible value in DT
Joseph Lo (6):
ARM: tegra: add Tegra124 SoC support
ARM: tegra: add PMC compatible value for Tegar124
ARM: tegra: Add initial device tree
This patch is only a hack for Tegra124 bring up testing. Please don't
merge this. The same function can be replaced by Tegra124 clock driver.
* re-use UART-A in DT
* add a temp PMC compatible value
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* add a temp PMC compatible value fot Tegra124
Add support for the Tegra124 based Venice2 reference board.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* fix the device node name with register address
* remove an extra blank line
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/tegra124-venice2.dts | 20
The PMC HW is not identical to the existing Tegra SoC. Hence add to it.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* new in v2
---
arch/arm/mach-tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 93a4dbc..3744af9
Add Tegra124 support in tegra_defconfig file.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* no change
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index ec4f6e7..4934295 100644
Add Tegra124 SoC support that base on CortexA15MP Core. And enable the
SMP function that can re-use the same procedure with Tegra114.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* squash the [v1 1/7] ~ [v2 3/7] into the 1st patch in v2
---
arch/arm/mach-tegra/Kconfig | 8
arch
Initial support for Tegra 124 SoC. This is expected to be included in
the board DTS files.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* fix device node name with register address
* fix PMC compitable value for Tegra124
---
arch/arm/boot/dts/tegra124.dtsi | 132
On Tue, 2013-09-03 at 21:31 +0800, Peter De Schrijver wrote:
This patch converts the Tegra114 audio clock registration to be table driven
like the periph clocks.
s/audio/PMC/ :)
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-tegra114.c | 58
On Sat, 2013-08-24 at 03:45 +0800, Colin Cross wrote:
Joseph Lo jose...@nvidia.com reported a lockup on Tegra3 caused
by a race condition in coupled cpuidle. When two or more cpus
Actually this issue can be reproduced on both Tegra20/30 platforms. And
I suggest using Tegra20 to replace Tegra3
The cpu and pclk_p_cclk was a virtual clock name that was used in
the legacy Tegra clock framework. It was not used after converting to
CCF. Fix it as the correct clock name that we are using.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
drivers/cpufreq/tegra-cpufreq.c | 4 ++--
1 file
On Tue, 2013-08-13 at 03:24 +0800, Stephen Warren wrote:
On 08/12/2013 03:40 AM, Joseph Lo wrote:
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are
clock gated and SDRAM in self-refresh mode. That means the low level LP1
suspending and resuming code couldn't be run
, so we do these jobs mainly in
this patch:
* moving LP1 low level handling code to IRAM
* marking LP1 mask
* copying the physical address of tegra_resume to PMC_SCRATCH41
* re-calculate the CPU power timer based on 32KHz
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* using a #define
to tegra_resume that was expected to be stored
in PMC_SCRATCH41 to restore CPU context and back to kernel.
Based on the work by: Bo Yan b...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* setting up CCLK burst policy to PLLX in lp1_resume
V2:
* using IS_ENABLE for SoC specific code
* moving
Enabling the LP1 suspend mode for Tegra devices.
Tested-by: Marc Dietrich marvi...@gmx.de # paz00 board
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* fix the Tested-by line
V2:
* no change
---
arch/arm/boot/dts/tegra114-dalmore.dts | 2 +-
arch/arm/boot/dts/tegra20-colibri-512.dtsi
in PLLX. Then jumping to
tegra_resume that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams scwilli...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* remove the no meaning message AND MUST BE FIRST
V2
When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have different polarity of the request of SYSCLK, this patch
configure the polarity from the DT for the board.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* no change
V2:
* s/inverts/polarity/
---
arch
. And the
root cause of this is about the default settings of EMC registers that
cause the DRAM can't leave self-refresh mode immediately. If you want
to test with quick LP1 resume on Dalmore, I can provide another HACK for
this.
Joseph Lo (8):
ARM: tegra: add common resume handling code for LP1
resume
code into IRAM, so that it is accessible before SDRAM access has been
re-enabled.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* no change
V2:
* update the commit message
* move the define of IRAM_CODE_AREA to iomap.h
* move the THUMB marco code before the 'bx' instruction
---
arch/arm
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* move the CCLKG burst policy resume code to tegra_cpu_car_ops
V2:
* update the commit message
---
drivers/clk/tegra/clk-tegra114.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra
.
Based on the work by:
Colin Cross ccr...@android.com
Gary King gk...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* switch SCLK burst policy reg to CLK_S after disabling PLLs to align
with Tegra30/114
V2:
* using IS_ENABLE for SoC specific code
* calculating
On Fri, 2013-08-09 at 03:54 +0800, Stephen Warren wrote:
On 08/07/2013 08:23 PM, Joseph Lo wrote:
On Thu, 2013-08-08 at 00:46 +0800, Stephen Warren wrote:
..
I still have absolutely no idea why Tegra30 and Tegra114 are different.
You mentioned something about this low-level code only
On Wed, 2013-08-07 at 02:37 +0800, Stephen Warren wrote:
On 08/06/2013 03:10 AM, Joseph Lo wrote:
On Tue, 2013-08-06 at 01:39 +0800, Stephen Warren wrote:
On 08/05/2013 11:00 AM, Stephen Warren wrote:
On 08/05/2013 02:02 AM, Joseph Lo wrote:
On Sat, 2013-08-03 at 04:32 +0800, Stephen
On Thu, 2013-08-08 at 00:46 +0800, Stephen Warren wrote:
On 08/07/2013 03:12 AM, Joseph Lo wrote:
On Wed, 2013-08-07 at 02:37 +0800, Stephen Warren wrote:
On 08/06/2013 03:10 AM, Joseph Lo wrote:
On Tue, 2013-08-06 at 01:39 +0800, Stephen Warren wrote:
On 08/05/2013 11:00 AM, Stephen
On Tue, 2013-08-06 at 01:00 +0800, Stephen Warren wrote:
On 08/05/2013 02:02 AM, Joseph Lo wrote:
On Sat, 2013-08-03 at 04:32 +0800, Stephen Warren wrote:
On 08/02/2013 02:09 AM, Joseph Lo wrote:
On Tue, 2013-07-30 at 06:51 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo
On Tue, 2013-08-06 at 01:48 +0800, Stephen Warren wrote:
On 08/05/2013 05:21 AM, Joseph Lo wrote:
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are
clock gated and SDRAM in self-refresh mode. That means the low level LP1
suspending and resuming code couldn't be run
On Tue, 2013-08-06 at 01:53 +0800, Stephen Warren wrote:
On 08/05/2013 05:21 AM, Joseph Lo wrote:
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
V2
On Tue, 2013-08-06 at 01:56 +0800, Stephen Warren wrote:
On 08/05/2013 05:20 AM, Joseph Lo wrote:
This series adds the support of LP1 suspend mode for Tegra.
V2:
* double confirm each patch can be built with all the combination of
Tegra SoCs by bisect
* and make sure the function
On Tue, 2013-07-30 at 07:45 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo wrote:
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
diff --git
On Tue, 2013-07-30 at 07:53 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo wrote:
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
diff --git
On Sat, 2013-08-03 at 04:32 +0800, Stephen Warren wrote:
On 08/02/2013 02:09 AM, Joseph Lo wrote:
On Tue, 2013-07-30 at 06:51 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo wrote:
When the system suspends to LP1, the clock of the CPU would be switched to
CLK_M (12MHz
On Sat, 2013-08-03 at 04:40 +0800, Stephen Warren wrote:
On 08/02/2013 03:27 AM, Joseph Lo wrote:
On Tue, 2013-07-30 at 07:13 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo wrote:
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are
clock gated
On Sat, 2013-08-03 at 04:24 +0800, Stephen Warren wrote:
On 08/02/2013 01:48 AM, Joseph Lo wrote:
On Tue, 2013-07-30 at 06:47 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo wrote:
When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have
with quick LP1 resume on Dalmore, I can provide another HACK for
this.
Joseph Lo (8):
ARM: tegra: add common resume handling code for LP1 resuming
ARM: tegra: config the polarity of the request of sys clock
clk: tegra114: add LP1 suspend/resume support
ARM: tegra: add common LP1 suspend
in PMC_SCRATCH41 to restore CPU context and back to kernel.
Based on the work by: Bo Yan b...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* using IS_ENABLE for SoC specific code
* moving the fix of PLL lock func to previous patch
---
arch/arm/mach-tegra/Makefile| 1
Enabling the LP1 suspend mode for Tegra devices.
Tested-by: Marc Dietrich marvi...@gmx.de
[Tegra20 paz00 board]
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* no change
---
arch/arm/boot/dts/tegra114-dalmore.dts | 2 +-
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 2 +-
arch/arm/boot
.
Based on the work by:
Colin Cross ccr...@android.com
Gary King gk...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* using IS_ENABLE for SoC specific code
* modify tegra20_sdram_pad_save as suggestion
---
arch/arm/mach-tegra/Makefile| 1 +
arch/arm/mach-tegra/pm-tegra20
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* update the commit message
---
drivers/clk/tegra/clk-tegra114.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index f74ed19..b0e745a 100644
, so we do these jobs mainly in
this patch:
* moving LP1 low level handling code to IRAM
* marking LP1 mask
* copying the physical address of tegra_resume to PMC_SCRATCH41
* re-calculate the CPU power timer based on 32KHz
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* don't duplicate
resume
code into IRAM, so that it is accessible before SDRAM access has been
re-enabled.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* update the commit message
* move the define of IRAM_CODE_AREA to iomap.h
* move the THUMB marco code before the 'bx' instruction
---
arch/arm/mach-tegra/iomap.h
in PLLX. Then jumping to
tegra_resume that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams scwilli...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* remove wait_for_us
* using IS_ENABLE for SoC specific
When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have different polarity of the request of SYSCLK, this patch
configure the polarity from the DT for the board.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* s/inverts/polarity/
---
arch/arm/mach-tegra
On Tue, 2013-07-30 at 06:47 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo wrote:
When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have different polarity of the request of SYSCLK, this patch
configure the polarity from the DT
On Tue, 2013-07-30 at 06:51 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo wrote:
When the system suspends to LP1, the clock of the CPU would be switched to
CLK_M (12MHz Oscillator) during suspend/resume flow. The clock driver
needs to restore the clock of CPU after LP1
On Tue, 2013-07-30 at 07:13 +0800, Stephen Warren wrote:
On 07/26/2013 03:15 AM, Joseph Lo wrote:
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are
clock gated and SDRAM in self-refresh mode. That means the low level LP1
suspending and resuming code couldn't be run
The IRQ trigger type of Palmas MFD device (tps65913) is designed as
low-level sensitive on Dalmore. The wrong configuration would cause an
interrupt storm when booting the system. Fixing it in DT with appropriate
interrupt type.
Cc: Laxman Dewangan ldewan...@nvidia.com
Signed-off-by: Joseph Lo
On Wed, 2013-07-31 at 00:24 +0800, Stephen Warren wrote:
On 07/30/2013 03:46 AM, Joseph Lo wrote:
On Fri, 2013-07-26 at 23:16 +0800, Stephen Warren wrote:
On 07/24/2013 04:54 AM, Joseph Lo wrote:
The IRQ trigger type of Palmas MFD device (tps65913) is edge trigger. The
wrong configuration
On Fri, 2013-07-26 at 23:16 +0800, Stephen Warren wrote:
On 07/24/2013 04:54 AM, Joseph Lo wrote:
The IRQ trigger type of Palmas MFD device (tps65913) is edge trigger. The
wrong configuration would cause an interrupt storm when booting the
system. Fixing it in DT with appropriate interrupt
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