Re: [PATCH V2 0/7] ARM: tegra30: cpuidle: add LP2 support

2012-10-22 Thread Joseph Lo
On Fri, 2012-10-19 at 16:48 +0800, Joseph Lo wrote: The CPU idle LP2 is a power gating idle mode for Tegra30. It supports the secondary CPUs (i.e., CPU1-CPU3) to go into LP2 dynamically. When any of the secondary CPUs go into LP2, it can be power gated alone. There is a limitation on CPU0. The

[PATCH V2 0/7] ARM: tegra30: cpuidle: add LP2 support

2012-10-19 Thread Joseph Lo
The CPU idle LP2 is a power gating idle mode for Tegra30. It supports the secondary CPUs (i.e., CPU1-CPU3) to go into LP2 dynamically. When any of the secondary CPUs go into LP2, it can be power gated alone. There is a limitation on CPU0. The CPU0 can go into LP2 only when all secondary CPUs are