Hi Stephen,
Thanks for review and sorry for late response due to national holiday
yesterday.
On Wed, 2012-10-10 at 06:26 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The CPU idle LP2 is a power gating idle mode for Tegra30. It supports the
secondary CPUs (i.e.,
On Wed, 2012-10-10 at 06:22 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
diff --git a/arch/arm/mach-tegra/cpuidle.c
On Wed, 2012-10-10 at 06:29 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
LP2 is one of the Tegra low power states that supports power gating both
CPU cores and GICs. Adding a resume function for taking care the CPUs that
resume from LP2. This function was been
On Wed, 2012-10-10 at 06:38 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
This supports power-gated (LP2) idle on secondary CPUs for Tegra30.
The secondary CPUs can go into LP2 state independently. When CPU goes
into LP2 state, it saves it's state and puts itself to
On Wed, 2012-10-10 at 06:38 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gate low power state (e.g.,
On Wed, 2012-10-10 at 06:49 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The cpuidle LP2 is a power gating idle mode. It support power gating
vdd_cpu rail after all cpu cores in LP2. For Tegra30, the CPU0 must
be last one to go into LP2. We need to take care and
On 10/11/2012 03:15 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:38 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
This supports power-gated (LP2) idle on secondary CPUs for Tegra30.
The secondary CPUs can go into LP2 state independently. When CPU goes
into LP2 state,
On 10/11/2012 05:24 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:49 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The cpuidle LP2 is a power gating idle mode. It support power gating
vdd_cpu rail after all cpu cores in LP2. For Tegra30, the CPU0 must
be last one to go
On Thu, Oct 11, 2012 at 9:37 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 10/11/2012 05:24 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:49 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The cpuidle LP2 is a power gating idle mode. It support power gating
vdd_cpu
Hi,
I've finally managed to get HDMI working on Tegra20. Unfortunately the
xf86-video-modesetting driver doesn't work on top of it yet, but I think
that's a different error somewhere else and I'm still trying to figure
out what exactly is going wrong. However, a framebuffer console can be
run on
On 10/11/2012 02:07 PM, Thierry Reding wrote:
Hi,
I've finally managed to get HDMI working on Tegra20. Unfortunately
the xf86-video-modesetting driver doesn't work on top of it yet,
but I think that's a different error somewhere else and I'm still
trying to figure out what exactly is going
On Fri, 2012-10-12 at 07:36 +0800, Stephen Warren wrote:
On 10/11/2012 02:07 PM, Thierry Reding wrote:
Hi,
I've finally managed to get HDMI working on Tegra20. Unfortunately
the xf86-video-modesetting driver doesn't work on top of it yet,
but I think that's a different error somewhere
Thank you for your hard work, Thierry!
We're looking forward to your final merged drm driver and hope we can
get it into 3.8.
Mark
On Fri, 2012-10-12 at 04:07 +0800, Thierry Reding wrote:
* PGP Signed by an unknown key
Hi,
I've finally managed to get HDMI working on Tegra20. Unfortunately
On Fri, 2012-10-12 at 00:24 +0800, Stephen Warren wrote:
On 10/11/2012 03:15 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:38 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
This supports power-gated (LP2) idle on secondary CPUs for Tegra30.
The secondary CPUs can go
On Thu, Oct 11, 2012 at 05:36:35PM -0600, Stephen Warren wrote:
On 10/11/2012 02:07 PM, Thierry Reding wrote:
Hi,
I've finally managed to get HDMI working on Tegra20. Unfortunately
the xf86-video-modesetting driver doesn't work on top of it yet,
but I think that's a different error
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