The tegra_cpu_car_ops provide the interface for CPU to control
it's clock gating and reset status. The other drivers should use
this for CPU control. And should not directly access CAR registers
to control CPU.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/clock.c
Replacing the code that directly access to CAR registers with
tegra_cpu_car_ops. This ops hides CPU CAR access inside and
provides control interface for it.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/platsmp.c | 29 +
1 files changed, 5
There are some common macros for Tegra low-level assembly code. Clean
up them into one header file and move the definitions that will be
re-used into it as well.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/headsmp.S |6 +---
arch/arm/mach-tegra/sleep.S | 33
-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/Makefile|1 +
arch/arm/mach-tegra/common.c|1 +
arch/arm/mach-tegra/hotplug.c |8
arch/arm/mach-tegra/sleep-t20.S | 82 +++
arch/arm/mach-tegra/sleep.h |3 +
5 files changed
...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/Makefile|1 +
arch/arm/mach-tegra/common.c|2 +
arch/arm/mach-tegra/hotplug.c | 110 +--
arch/arm/mach-tegra/sleep-t30.S | 107
Replacing the code that directly access to CAR registers with
tegra_cpu_car_ops. This ops hides CPU CAR access inside and
provides control interface for it.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/platsmp.c | 29 +
1 files changed, 5
There are some common macros for Tegra low-level assembly code. Clean
up them into one header file and move the definitions that will be
re-used into it as well.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/headsmp.S |6 +---
arch/arm/mach-tegra/sleep.S | 33
The tegra_cpu_car_ops provide the interface for CPU to control
it's clock gating and reset status. The other drivers should use
this for CPU control. And should not directly access CAR registers
to control CPU.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/clock.c
Enable HOTPLUG_CPU after the SoC specific code to hotplug a CPU
been merged.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/configs/tegra_defconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs
Hi Stephen,
On Thu, 2012-08-16 at 00:05 +0800, Stephen Warren wrote:
On 08/15/2012 03:22 AM, Joseph Lo wrote:
This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.
The first 3 patches make the CPU clock and reset control be a module and
the abstraction APIs for TegraXX
on Seaboard(Tegra20) and Cardhu(Tegra30)
V3:
* fix the build error when HOTPLUG_CPU disabled [4/6] [5/6]
V2:
* add one more patch for enable HOTPLUG_CPU [6/6]
* move all the SoC specific CPU shutdown code into platform_cpu_die [4/6]
Joseph Lo (6):
ARM: tegra: introduce tegra_cpu_car_ops structures
ARM
Replacing the code that directly access to CAR registers with
tegra_cpu_car_ops. This ops hides CPU CAR access inside and
provides control interface for it.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* no change
V2:
* no change
arch/arm/mach-tegra/platsmp.c | 29
The tegra_cpu_car_ops provide the interface for CPU to control
it's clock gating and reset status. The other drivers should use
this for CPU control. And should not directly access CAR registers
to control CPU.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* no change
V2:
* no change
arch
There are some common macros for Tegra low-level assembly code. Clean
up them into one header file and move the definitions that will be
re-used into it as well.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* no change
V2:
* no change
arch/arm/mach-tegra/headsmp.S |6 +---
arch/arm
...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* fix the compiling error when HOTPLUG_CPU disabled
V2:
* move the SoC specific CPU shutdown code into platform_cpu_die
arch/arm/mach-tegra/Makefile|1 +
arch/arm/mach-tegra/common.c|2 +
arch/arm/mach-tegra
-by: Joseph Lo jose...@nvidia.com
---
V3:
* fix the compiling error when HOTPLUG_CPU disabled
V2:
* no change
arch/arm/mach-tegra/Makefile|1 +
arch/arm/mach-tegra/common.c|1 +
arch/arm/mach-tegra/hotplug.c |8
arch/arm/mach-tegra/sleep-t20.S | 82
Currently the tegra20 and tegra30 share the same symbol for
tegra_clk_32k_ops. This will cause a compile error when building
a tegra20-only kernel image. Add tegra_clk_32k_ops for tegra20 and
modify tegra30_clk_32k_ops for tegra30.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach
It should use tegra30_audio_sync_clk_ops for tegra30. It will cause
the tegra30 use the wrong audio_sync_clk_ops when build a kernel with
a tegra20 and tegra30 both supported kernel. And building error when
a tegra30-only kernel.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach
and Tegra30 will only support booting using
device tree, Hence, there is never a need to fall back to using
soc_data_tegra20 if of_mach_device() fails. Instead, make this case an
error. This removes the reference to soc_data_tegra20, and hence solves
the compile failure.
Signed-off-by: Joseph Lo jose
On Sat, 2012-08-18 at 03:01 +0800, Stephen Warren wrote:
On 08/17/2012 01:04 AM, Joseph Lo wrote:
When compiling a kernel that supports only Tegra30 and not Tegra20,
the SDHCI driver will fail to compile since the of_match_device() failure
fallback code unconditinally references
On Wed, 2012-10-03 at 07:21 +0800, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
sleep.S doesn't provide anything useful any more; commit b4e395b ARM:
tegra: Remove flow controller programming removed the last public code
here, so that everyting that was left was just macros
For the naming consistency under the mach-tegra, we re-name the file of
sleep-tXX to sleep-tegraXX (e.g., sleep-t30 to sleep-tegra30).
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/Makefile |4 ++--
.../mach-tegra/{sleep-t20.S = sleep-tegra20.S
Williams scwilli...@nvidia.com
Colin Cross ccr...@android.com
Gary King gk...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/headsmp.S | 58 +
arch/arm/mach-tegra/reset.c |6
arch/arm/mach-tegra/sleep.h |1 +
3
Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gate low power state (e.g., LP2).
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/common.c |1 +
1 files
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU low-power state maintenance (e.g., LP2). One
thing needs to notice the rail_off_ready API only availalbe for cpu_g
cluster not cpu_lp cluster.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch
scwilli...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/Makefile |1 +
arch/arm/mach-tegra/cpuidle-tegra30.c | 79 +-
arch/arm/mach-tegra/pm.c | 88 +
arch/arm/mach-tegra/pm.h
-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/flowctrl.c | 47
arch/arm/mach-tegra/flowctrl.h |8 ++
2 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index
go into LP2 safely. Then power gating the
CPU rail.
Base on the work by:
Scott Williams scwilli...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/cpuidle-tegra30.c | 39 -
arch/arm/mach-tegra/pm.c | 152 +
arch
Hi Lorenzo,
Thanks for your review.
On Tue, 2012-10-09 at 00:35 +0800, Lorenzo Pieralisi wrote:
On Mon, Oct 08, 2012 at 11:26:17AM +0100, Joseph Lo wrote:
This supports power-gated (LP2) idle on secondary CPUs for Tegra30.
The secondary CPUs can go into LP2 state independently. When CPU
Hi Stephen,
Thanks for review and sorry for late response due to national holiday
yesterday.
On Wed, 2012-10-10 at 06:26 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The CPU idle LP2 is a power gating idle mode for Tegra30. It supports the
secondary CPUs (i.e., CPU1
On Wed, 2012-10-10 at 06:22 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
diff --git a/arch/arm/mach-tegra/cpuidle.c
b/arch/arm/mach
On Wed, 2012-10-10 at 06:29 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
LP2 is one of the Tegra low power states that supports power gating both
CPU cores and GICs. Adding a resume function for taking care the CPUs that
resume from LP2. This function was been
On Wed, 2012-10-10 at 06:38 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
This supports power-gated (LP2) idle on secondary CPUs for Tegra30.
The secondary CPUs can go into LP2 state independently. When CPU goes
into LP2 state, it saves it's state and puts itself
On Wed, 2012-10-10 at 06:38 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gate low power state (e.g
On Wed, 2012-10-10 at 06:49 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The cpuidle LP2 is a power gating idle mode. It support power gating
vdd_cpu rail after all cpu cores in LP2. For Tegra30, the CPU0 must
be last one to go into LP2. We need to take care
On Fri, 2012-10-12 at 00:24 +0800, Stephen Warren wrote:
On 10/11/2012 03:15 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:38 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
This supports power-gated (LP2) idle on secondary CPUs for Tegra30.
The secondary CPUs can go
On Fri, 2012-10-12 at 00:37 +0800, Stephen Warren wrote:
On 10/11/2012 05:24 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:49 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The cpuidle LP2 is a power gating idle mode. It support power gating
vdd_cpu rail after all
On Fri, 2012-10-12 at 00:48 +0800, Colin Cross wrote:
On Thu, Oct 11, 2012 at 9:37 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 10/11/2012 05:24 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:49 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The cpuidle LP2
On Fri, 2012-10-12 at 00:48 +0800, Colin Cross wrote:
On Thu, Oct 11, 2012 at 9:37 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 10/11/2012 05:24 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:49 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo wrote:
The cpuidle LP2
On Fri, 2012-10-12 at 15:54 +0800, Shawn Guo wrote:
On Thu, Oct 11, 2012 at 09:48:45AM -0700, Colin Cross wrote:
As is, coupled cpuidle will work on Tegra30, but it will unnecessarily
wake up the secondary cpus during the transitions to off and back on
again. Those cpus will immediately go
On Sat, 2012-10-13 at 05:04 +0800, Stephen Warren wrote:
On 10/12/2012 01:07 AM, Joseph Lo wrote:
On Fri, 2012-10-12 at 00:37 +0800, Stephen Warren wrote:
On 10/11/2012 05:24 AM, Joseph Lo wrote:
On Wed, 2012-10-10 at 06:49 +0800, Stephen Warren wrote:
On 10/08/2012 04:26 AM, Joseph Lo
Adding the AHB and APB bus clock control interface for Tegra30.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/common.c |4 +
arch/arm/mach-tegra/tegra30_clocks.c | 106 +
arch/arm/mach-tegra/tegra30_clocks.h |1
Previous work can be found at:
V1:
http://www.mail-archive.com/linux-tegra@vger.kernel.org/msg06319.html
Joseph Lo (7):
ARM: tegra: cpuidle: separate cpuidle driver for different chips
ARM: tegra: cpuidle: add LP2 resume function
ARM: tegra30: cpuidle: add LP2 driver for secondary CPUs
ARM
The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* only remove the line of file name and path in the (c) header
arch/arm/mach-tegra/Makefile
Williams scwilli...@nvidia.com
Colin Cross ccr...@android.com
Gary King gk...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* moving the code that only for Tegra30 inside the ifdef in the tegra_resume
arch/arm/mach-tegra/headsmp.S | 58
Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gate low power state (e.g., LP2).
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* same with V1
arch/arm/mach-tegra/common.c
scwilli...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* static initialization for idle states when PM_SLEEP is true or not
* using inline fuction to replace the empty fuction when #ifdef false
* convert the phy cpu number by cpu_logical_map
* update the usage of tegra_cpu_lp2_mask
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU low-power state maintenance (e.g., LP2). One
thing needs to notice the rail_off_ready API only availalbe for cpu_g
cluster not cpu_lp cluster.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2
-by: Joseph Lo jose...@nvidia.com
---
V2:
* same with V1
arch/arm/mach-tegra/flowctrl.c | 47
arch/arm/mach-tegra/flowctrl.h |8 ++
2 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra
On Mon, 2012-10-22 at 12:38 +0800, Prashant Gaikwad wrote:
On Friday 19 October 2012 12:08 PM, Joseph Lo wrote:
Adding the AHB and APB bus clock control interface for Tegra30.
Signed-off-by: Joseph Lojose...@nvidia.com
---
arch/arm/mach-tegra/common.c |4 +
arch
On Fri, 2012-10-19 at 16:48 +0800, Joseph Lo wrote:
The CPU idle LP2 is a power gating idle mode for Tegra30. It supports the
secondary CPUs (i.e., CPU1-CPU3) to go into LP2 dynamically. When any of
the secondary CPUs go into LP2, it can be power gated alone. There is a
limitation on CPU0
Add L2 cache controller binding into DT for Tegra.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/boot/dts/tegra20.dtsi |9 +
arch/arm/boot/dts/tegra30.dtsi |9 +
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b
Moving L2 cache init to DT support.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/common.c | 11 ---
1 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0e31f8c..a8f9175 100644
--- a/arch
On Sat, 2012-10-27 at 01:04 +0800, Stephen Warren wrote:
On 10/26/2012 04:34 AM, Joseph Lo wrote:
Add L2 cache controller binding into DT for Tegra.
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
+ L2: cache-controller@50043000 {
+ compatible
Add L2 cache controller binding into DT for Tegra.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* remove L2 label for cache-controller DT binding
---
arch/arm/boot/dts/tegra20.dtsi |9 +
arch/arm/boot/dts/tegra30.dtsi |9 +
2 files changed, 18 insertions(+), 0
Moving L2 cache init to DT support.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* no changes
---
arch/arm/mach-tegra/common.c | 11 ---
1 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 177f164
/linux-tegra@vger.kernel.org/msg06478.html
V1:
http://www.mail-archive.com/linux-tegra@vger.kernel.org/msg06319.html
Joseph Lo (7):
ARM: tegra: cpuidle: separate cpuidle driver for different chips
ARM: tegra: cpuidle: add CPU resume function
ARM: tegra30: cpuidle: add powered-down state
The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* no change
V2:
* only remove the line of file name and path in the (c) header
---
arch/arm/mach-tegra/Makefile
LP2 in the code
which is exactly the same meaning of CPU power down.
Based on the work by:
Scott Williams scwilli...@nvidia.com
Colin Cross ccr...@android.com
Gary King gk...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* update subject and the commit message
V2:
* moving
Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gating low power state.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* update the commit message
V2:
* no change
---
arch/arm
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance. One thing
needs to notice the rail_off_ready API only availalbe for cpu_g cluster
not cpu_lp cluster.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3:
* update
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: Joseph
-by: Joseph Lo jose...@nvidia.com
---
V3:
* Fix the potential issue that will cause the CPU corruption when CPUs
doing LP2. All CPUs entering LP2 is not working. The CPU0 can enter
LP2 only when all secondary CPU is offline. This can be covered by
CPUquiet and cluster switching mechanism.
* update
On Wed, 2012-10-31 at 06:27 +0800, Stephen Warren wrote:
On 10/30/2012 04:03 PM, Antti P Miettinen wrote:
Joseph Lo jose...@nvidia.com writes:
+ writel(tegra_in_lp2.bits[0], tegra_cpu_lp2_mask);
BTW, writel_relaxed() would probably be more than enough? IRAM is mapped
stronly
On Wed, 2012-10-31 at 06:45 +0800, Stephen Warren wrote:
On 10/29/2012 04:28 AM, Joseph Lo wrote:
This adds a powered-down state for cpuidle. It's a power gating idle
mode. It supports the secondary CPUs (i.e., CPU1-CPU3) to go into
powered-down state independently. When any
:
http://www.mail-archive.com/linux-tegra@vger.kernel.org/msg06478.html
V1:
http://www.mail-archive.com/linux-tegra@vger.kernel.org/msg06319.html
Joseph Lo (7):
ARM: tegra: cpuidle: separate cpuidle driver for different chips
ARM: tegra: cpuidle: add CPU resume function
ARM: tegra30: cpuidle
LP2 in the code
which is exactly the same meaning of CPU power down.
Based on the work by:
Scott Williams scwilli...@nvidia.com
Colin Cross ccr...@android.com
Gary King gk...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V4:
* rebased on next-20121031
* add ifdef
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: Joseph
The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V4:
* no change
V3:
* no change
V2:
* only remove the line of file name and path in the (c) header
---
arch/arm/mach
the legacy power state LP2 in the
code which is exactly the same meaning of CPU power down.
Based on the work by:
Scott Williams scwilli...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V4:
* rebased on next-20121031
V3:
* remove the redundant header file
* update the subject
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance. One thing
needs to notice the rail_off_ready API only availalbe for cpu_g cluster
not cpu_lp cluster.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V4:
* rebased
-by: Joseph Lo jose...@nvidia.com
---
V4:
* rebased on next-20121031
V3:
* Fix the potential issue that will cause the CPU corruption when CPUs
doing LP2. All CPUs entering LP2 is not working. The CPU0 can enter
LP2 only when all secondary CPU is offline. This can be covered by
CPUquiet and cluster
On Thu, 2012-11-01 at 05:19 +0800, Colin Cross wrote:
On Wed, Oct 31, 2012 at 2:41 AM, Joseph Lo jose...@nvidia.com wrote:
This supports power-gated idle on secondary CPUs for Tegra30. The
secondary CPUs can go into powered-down state independently. When
CPU goes into this state, it saves
need to restore it's settings and re-enable
it after the power be resumed.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/common.c |6 +-
arch/arm/mach-tegra/headsmp.S | 11 +++
arch/arm/mach-tegra/pm.c |2 --
arch/arm/mach-tegra/pm.h |2
Enable the data prefetch on L2. The bit28 in aux ctrl register.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/common.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index c25746e
On Sat, 2012-11-10 at 05:54 +0800, Stephen Warren wrote:
On 11/06/2012 02:32 AM, Joseph Lo wrote:
The L2 RAM is in different power domain from the CPU cluster. So the
L2 content can be retained over CPU suspend/resume. To do that, we
need to disable L2 after the MMU is disabled, and enable
need to restore it's settings and re-enable
it after the power be resumed.
Signed-off-by: Joseph Lo jose...@nvidia.com
Acked-by: Peter De Schrijver pdeschrij...@nvidia.com
---
V2:
* fix the missing definition of L2X0_CTRL_EN
---
arch/arm/mach-tegra/common.c |6 +-
arch/arm/mach-tegra
: fix the potensial race condition and deadlock)
Before the patch be applied, please don't merge the last patch that apply
coupled cpuidle for powered-down cpuidle driver.
Verified on Seaboard(Tegra20) and Cardhu(Tegra30).
Joseph Lo (5):
ARM: tegra20: cpuidle: add powered-down state
Cross ccr...@android.com
Gary King gk...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 84 +++
arch/arm/mach-tegra/pm.c |2 +
arch/arm/mach-tegra/sleep-tegra20.S | 145 +
arch
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/tegra20_clocks.c | 102 ++
1 files changed, 102 insertions
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: Joseph
...@nvidia.com
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 129 -
arch/arm/mach-tegra/sleep-tegra20.S | 53 ++
arch/arm/mach-tegra/sleep.S | 19 +
arch/arm/mach-tegra/sleep.h |3 +
4
mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).
Signed-off-by: Joseph Lo jose...@nvidia.com
---
arch/arm/mach-tegra/Kconfig |1 +
arch/arm/mach-tegra/cpuidle-tegra20.c | 37
On Tue, 2012-12-04 at 13:12 +0800, Prashant Gaikwad wrote:
On Monday 03 December 2012 08:30 AM, Joseph Lo wrote:
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.
Signed-off-by: Joseph Lo jose...@nvidia.com
On Tue, 2012-12-04 at 02:18 +0800, Stephen Warren wrote:
On 12/02/2012 08:00 PM, Joseph Lo wrote:
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20
On Tue, 2012-12-04 at 02:31 +0800, Stephen Warren wrote:
On 12/02/2012 08:00 PM, Joseph Lo wrote:
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20
On Tue, 2012-12-04 at 02:40 +0800, Stephen Warren wrote:
On 12/02/2012 08:00 PM, Joseph Lo wrote:
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI for waiting
On Tue, 2012-12-04 at 02:52 +0800, Stephen Warren wrote:
On 12/02/2012 08:00 PM, Joseph Lo wrote:
The powered-down cpuidle mode of Tegra20 needs the CPU0 be the last one
core to go into this mode before other core. The coupled cpuidle framework
can help to sync the MPCore to coupled state
, then we will abort the
powered-down idle for the both CPUs that already in coupled state
Verified on Seaboard(Tegra20) and Cardhu(Tegra30).
Joseph Lo (6):
ARM: tegra: add pending SGI checking API
ARM: tegra20: cpuidle: add powered-down state for secondary CPU
ARM: tegra20: clocks: add
interrupt. It
still can be maintained by Tegra legacy interrupt controller. If there
is any pending PPI or SPI when CPU in powered-down CPU idle mode. The
CPU can be woken up immediately. So we don't need to take care the same
situation for PPI or SPI.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* refine the code sequence in tegra20_cpu_rail_off_ready
---
arch/arm/mach-tegra/tegra20_clocks.c | 99
mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V2:
* handling the case of SGI pending before go into powered-down idle mode
---
arch/arm/mach-tegra/Kconfig
return ret;
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 63cb643..32ecdb6 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -71,6 +71,7 @@ struct tegra_gpio_bank {
u32 oe[4];
u32 int_enb[4];
u32 int_lvl[4];
+
config ARCH_TEGRA_3x_SOC
bool Enable support for Tegra30 family
+ select ARCH_NEEDS_CPU_IDLE_COUPLED
select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_743622
select ARM_ERRATA_751472
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c
Sorry, there is something wrong.
Please ignore this mail.
On Wed, 2012-12-05 at 18:01 +0800, Joseph Lo wrote:
return ret;
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 63cb643..32ecdb6 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
Sorry, there is something wrong.
Please ignore this mail.
On Wed, 2012-12-05 at 18:01 +0800, Joseph Lo wrote:
config ARCH_TEGRA_3x_SOC
bool Enable support for Tegra30 family
+ select ARCH_NEEDS_CPU_IDLE_COUPLED
select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_743622
On Thu, 2012-12-06 at 06:09 +0800, Stephen Warren wrote:
On 12/05/2012 03:01 AM, Joseph Lo wrote:
The powered-down CPU idle mode of Tegra cut off the vdd_cpu rail, it
include the power of GIC. That caused the SGI (Software Generated
Interrupt) been lost. Because the SGI can't wake up
On Thu, 2012-12-06 at 06:18 +0800, Stephen Warren wrote:
On 12/05/2012 03:01 AM, Joseph Lo wrote:
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20
a new patch for checking if there is any pending SGI
* if there is a SGI pending for the CPU, then we will abort the
powered-down idle for the both CPUs that already in coupled state
Verified on Seaboard(Tegra20) and Cardhu(Tegra30).
Joseph Lo (5):
ARM: tegra: add pending SGI checking API
ARM
interrupt. It
still can be maintained by Tegra legacy interrupt controller. If there
is any pending PPI or SPI when CPU in powered-down CPU idle mode. The
CPU can be woken up immediately. So we don't need to take care the same
situation for PPI or SPI.
Signed-off-by: Joseph Lo jose...@nvidia.com
---
V3
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