Felipe Balbi wrote at Friday, August 18, 2017 3:30 AM:
> Hi,
>
> kbuild test robot writes:
> > tree: https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
> > testing/next
> > head: 862b43460309779e5814616a68aa36d29a70d6e0
> > commit:
From: Stephen Warren <swar...@nvidia.com>
When the gadget serial device has no associated TTY, do not pass any
received data into the TTY layer for processing; simply drop it instead.
This prevents the TTY layer from calling back into the gadget serial
driver, which will then crash
Felipe,
I've found a problem in the gadget serial driver, which I believe is
triggered in the following scenario:
1) Both host and gadget system have a USB gadget serial port open.
2) Gadget side application closes the serial port.
3) Host side sends data to the serial port.
(Steps 2, 3
On 07/06/2017 11:16 AM, Dmitry Osipenko wrote:
On 06.07.2017 19:46, Stephen Warren wrote:
On 07/05/2017 07:24 PM, Peter Chen wrote:
On Wed, Jul 05, 2017 at 08:19:53PM +0300, Dmitry Osipenko wrote:
From: Thierry Reding <tred...@nvidia.com>
Override the compatible string of the fir
On 07/06/2017 10:57 AM, Dmitry Osipenko wrote:
On 06.07.2017 19:38, Stephen Warren wrote:
On 07/05/2017 11:19 AM, Dmitry Osipenko wrote:
Override the compatible string of the first USB controller to enable
device mode.
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts
b/arch/arm/boot/dts
On 07/05/2017 07:24 PM, Peter Chen wrote:
On Wed, Jul 05, 2017 at 08:19:53PM +0300, Dmitry Osipenko wrote:
From: Thierry Reding
Override the compatible string of the first USB controller to enable
device mode.
Signed-off-by: Thierry Reding
---
isting behaviour.
Acked-by: Stephen Warren <swar...@nvidia.com>
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isting behaviour. I hope
someone tested this on real HW?
Acked-by: Stephen Warren <swar...@nvidia.com>
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On 07/05/2017 11:19 AM, Dmitry Osipenko wrote:
From: Thierry Reding
Override the compatible string of the first USB controller to enable
device mode.
I don't have easy access to this HW any more to test this patch; we do
have one in our automated test system, but it's
On 07/05/2017 11:19 AM, Dmitry Osipenko wrote:
Override the compatible string of the first USB controller to enable
device mode.
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts
b/arch/arm/boot/dts/tegra20-paz00.dts
usb@c500 {
+ compatible = "nvidia,tegra20-udc";
On 07/05/2017 04:13 PM, Dmitry Osipenko wrote:
On 05.07.2017 23:31, Stephen Warren wrote:
On 07/05/2017 11:19 AM, Dmitry Osipenko wrote:
Some time ago Thierry Reding sent out patches that enabled UDC on NVIDIA
Tegra, unfortunately they haven't got enough traction to get into the
kernel. I've
On 07/05/2017 11:19 AM, Dmitry Osipenko wrote:
Since NVIDIA Tegra 20/30/40/TK1 are supported now by the ChipIdea driver,
let's enable this driver in tegra_defconfig.
Shouldn't this patch be earlier in the series so that we don't
completely break USB support between the patch which switches a
On 07/05/2017 11:19 AM, Dmitry Osipenko wrote:
Some time ago Thierry Reding sent out patches that enabled UDC on NVIDIA
Tegra, unfortunately they haven't got enough traction to get into the
kernel. I've rebased those patches and added a fix for the Ethernet USB
Gadget on Tegra20, Marc Dietrich
Baolin,
I have a question about the following commit:
511a36d2f357 "usb: gadget: Add the gserial port checking in gs_start_tx()"
When usb gadget is set gadget serial function, it will be crash in below
situation.
It will clean the 'port->port_usb' pointer in gserial_disconnect() function
On 08/02/2016 01:29 PM, Stefan Wahren wrote:
Hi Stephen,
Stephen Warren <swar...@wwwdotorg.org> hat am 2. August 2016 um 19:19
geschrieben:
On 07/26/2016 12:53 PM, Stefan Wahren wrote:
The Raspberry Pi Zero is a minified version of model A+. It's
notable there is no PWR LED and the A
On 07/26/2016 12:53 PM, Stefan Wahren wrote:
The Raspberry Pi Zero is a minified version of model A+. It's
notable there is no PWR LED and the ACT LED is inverted.
Patches 3-6,
Acked-by: Stephen Warren <swar...@nvidia.com>
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
b/arch/ar
On 05/26/2016 03:17 PM, Stephen Warren wrote:
On 05/26/2016 09:40 AM, Thierry Reding wrote:
From: Thierry Reding <tred...@nvidia.com>
All of these Tegra SoC generations have a ChipIdea UDC IP block that can
be used for device mode communication with a host. Implement rudimentary
s
On 05/26/2016 09:40 AM, Thierry Reding wrote:
From: Thierry Reding
All of these Tegra SoC generations have a ChipIdea UDC IP block that can
be used for device mode communication with a host. Implement rudimentary
support that doesn't allow switching between host and device
On 05/05/2016 02:05 AM, Hans de Goede wrote:
Hi,
On 04-05-16 22:25, Thierry Reding wrote:
On Wed, May 04, 2016 at 11:23:20AM -0600, Stephen Warren wrote:
On 05/04/2016 08:40 AM, Thierry Reding wrote:
From: Thierry Reding <tred...@nvidia.com>
Starting with commit 0b52297f2288 ("
On 05/04/2016 08:40 AM, Thierry Reding wrote:
From: Thierry Reding
Starting with commit 0b52297f2288 ("reset: Add support for shared reset
controls") there is a reference count for reset control assertions. The
goal is to allow resets to be shared by multiple devices and an
On 05/04/2016 08:39 AM, Thierry Reding wrote:
From: Thierry Reding
There are three EHCI controllers on Tegra SoCs, each with its own reset
line. However, the first controller contains a set of UTMI configuration
registers that are shared with its siblings. These registers
On 04/06/2016 11:08 AM, Thierry Reding wrote:
On Tue, Apr 05, 2016 at 03:10:16PM -0600, Stephen Warren wrote:
On 04/05/2016 08:44 AM, Thierry Reding wrote:
On Wed, Mar 16, 2016 at 11:59:44AM -0600, Stephen Warren wrote:
On 03/04/2016 09:19 AM, Thierry Reding wrote:
From: Thierry Reding <t
On 04/05/2016 08:44 AM, Thierry Reding wrote:
On Wed, Mar 16, 2016 at 11:59:44AM -0600, Stephen Warren wrote:
On 03/04/2016 09:19 AM, Thierry Reding wrote:
From: Thierry Reding <tred...@nvidia.com>
Extend the binding to cover the set of feature found in Tegra210.
Acked-by: Stephen
On 03/04/2016 09:19 AM, Thierry Reding wrote:
From: Thierry Reding <tred...@nvidia.com>
Extend the binding to cover the set of feature found in Tegra210.
Acked-by: Stephen Warren <swar...@nvidia.com>
diff --git
a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-p
2x super-speed USB: usb3-0, usb3-1
Oh, is the physical port ID implicit in the DT node name? It may be
worth mentioning that when describing the properties for each type of node.
I'll assume that's how the USB2<->USB3 mapping works. All of my comments
are mainly re: the descri
-0, usb3-1
If that's how this works (which might be worth mentioning in the binding
doc), then:
Acked-by: Stephen Warren <swar...@nvidia.com>
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More maj
inding is
no longer suitable.
Assuming the rest of the edits to this file in patch 1/9 get pulled into
this patch, or perhaps this patch simply gets squashed into path 1/9,
then this patch,
Acked-by: Stephen Warren <swar...@nvidia.com>
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On 03/04/2016 09:19 AM, Thierry Reding wrote:
From: Thierry Reding <tred...@nvidia.com>
Extend the Tegra XUSB controller device tree binding with Tegra210
support.
Acked-by: Stephen Warren <swar...@nvidia.com>
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On 11/07/2015 05:16 PM, Stefan Wahren wrote:
> Hi,
>
> i try to run linux-next-20151106 (U-Boot + USB patches from Stephen
> Warren) on my Raspberry Pi B rev2 and get a kernel oops (see bootlog at
> the end). I bisect the issue to this commit:
>
> 09a75e8577901489f77a14a3b
On 10/29/2015 01:41 AM, Uwe Kleine-König wrote:
> Hello Stephen,
>
> On Wed, Oct 28, 2015 at 09:55:05PM -0600, Stephen Warren wrote:
>> On 10/27/2015 12:18 PM, Uwe Kleine-König wrote:
>>> Hello,
>>>
>>> On Tue, Oct 27, 2015 at 09:08:27AM -0600, Stephen
On 10/27/2015 12:18 PM, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Oct 27, 2015 at 09:08:27AM -0600, Stephen Warren wrote:
>> On 10/27/2015 01:41 AM, Uwe Kleine-König wrote:
>>> Hello,
>>>
>>> On Mon, Oct 26, 2015 at 08:08:58PM -0600, Stephen Warren wro
On 10/27/2015 01:41 AM, Uwe Kleine-König wrote:
Hello,
On Mon, Oct 26, 2015 at 08:08:58PM -0600, Stephen Warren wrote:
On 10/26/2015 03:28 AM, Alexander Aring wrote:
This patch changes devm_phy_get to devm_phy_optional_get. Which fixes the
error handling when trying to get the phy. Currently
On 10/26/2015 03:28 AM, Alexander Aring wrote:
> This patch changes devm_phy_get to devm_phy_optional_get. Which fixes the
> error handling when trying to get the phy. Currently on all errors we
> try to look for an old style USB PHY. With this patch we try to look for
> an old USB PHY when
From: Stephen Warren <swar...@nvidia.com>
Add device-tree binding documentation for the XUSB (xHCI) controller
present on Tegra124 and later SoCs.
Signed-off-by: Andrew Bresticker <abres...@chromium.org>
[swarren, combined separate MFD, mailbox, XHCI bindings into one node
On 06/23/2015 05:56 AM, Roger Quadros wrote:
+ Kukjin, Stephen,
for board specific USB question.
On Tue, 23 Jun 2015 16:35:49 +0800
Li Jun b47...@freescale.com wrote:
On Tue, Jun 23, 2015 at 10:43:28AM +0300, Roger Quadros wrote:
If the dr_mode was otg for such case and we want OTG
On 04/23/2015 08:06 AM, Johan Hovold wrote:
Make sure only to copy any actual data rather than the whole buffer,
when releasing the temporary buffer used for unaligned non-isochronous
transfers.
Compile-tested only.
Tested-by: Stephen Warren swar...@nvidia.com
(Tested a USB network device
On 12/23/2014 11:36 AM, Felipe Balbi wrote:
On Thu, Dec 04, 2014 at 01:06:07PM +0100, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Commit 1290a958d48e (usb: phy: propagate __of_usb_find_phy()'s error on
failure) broke platforms that rely on deferred probing to order probing
of
On 09/16/2014 05:51 PM, Andrew Bresticker wrote:
On Tue, Sep 16, 2014 at 4:15 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 09/16/2014 04:46 PM, Andrew Bresticker wrote:
On Tue, Sep 16, 2014 at 9:57 AM, Andrew Bresticker
abres...@chromium.org wrote:
On Tue, Sep 16, 2014 at 8:26 AM
On 09/17/2014 02:47 PM, Dinh Nguyen wrote:
Hi Robert,
On 9/12/14, 7:13 AM, Robert Baldyga wrote:
Hi Dinh,
On 08/26/2014 06:19 PM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Add the proper init calls for either host, gadget or both in platform.c
On 09/15/2014 01:30 PM, Andrew Bresticker wrote:
On Mon, Sep 15, 2014 at 11:09 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 09/15/2014 11:06 AM, Andrew Bresticker wrote:
On Mon, Sep 15, 2014 at 12:00 AM, Tomeu Vizoso to...@tomeuvizoso.net wrote:
On 12 September 2014 18:37, Andrew
On 09/16/2014 10:57 AM, Andrew Bresticker wrote:
On Tue, Sep 16, 2014 at 8:26 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 09/15/2014 01:30 PM, Andrew Bresticker wrote:
On Mon, Sep 15, 2014 at 11:09 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 09/15/2014 11:06 AM, Andrew
On 09/16/2014 04:46 PM, Andrew Bresticker wrote:
On Tue, Sep 16, 2014 at 9:57 AM, Andrew Bresticker
abres...@chromium.org wrote:
On Tue, Sep 16, 2014 at 8:26 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 09/15/2014 01:30 PM, Andrew Bresticker wrote:
On Mon, Sep 15, 2014 at 11:09 AM
On 09/15/2014 11:06 AM, Andrew Bresticker wrote:
On Mon, Sep 15, 2014 at 12:00 AM, Tomeu Vizoso to...@tomeuvizoso.net wrote:
On 12 September 2014 18:37, Andrew Bresticker abres...@chromium.org wrote:
On Tue, Sep 9, 2014 at 1:21 AM, Tomeu Vizoso to...@tomeuvizoso.net wrote:
On 8 September 2014
On 09/02/2014 03:34 PM, Andrew Bresticker wrote:
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra xHCI controller's firmware and the
host processor.
The series,
Reviewed-by: Stephen Warren swar...@nvidia.com
I'd like Thierry to review
On 09/02/2014 03:34 PM, Andrew Bresticker wrote:
Add support for the on-chip xHCI host controller present on Tegra SoCs.
The driver is currently very basic: it loads the controller with its
firmware, starts the controller, and is able to service messages sent
by the controller's firmware. The
On 08/27/2014 10:36 AM, Andrew Bresticker wrote:
On Mon, Aug 25, 2014 at 12:12 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
- #phy-cells: Should be 1. The specifier is the index of the PHY to
reference.
See dt-bindings/pinctrl/pinctrl
On 08/27/2014 11:38 AM, Andrew Bresticker wrote:
On Mon, Aug 25, 2014 at 12:01 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
The Tegra xHCI controller's firmware communicates requests to the host
processor through a mailbox interface. While
On 08/27/2014 12:13 PM, Andrew Bresticker wrote:
On Wed, Aug 27, 2014 at 10:50 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/27/2014 11:38 AM, Andrew Bresticker wrote:
On Mon, Aug 25, 2014 at 12:01 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 08/18/2014 11:08 AM, Andrew
On 08/27/2014 03:56 PM, Andrew Bresticker wrote:
On Wed, Aug 27, 2014 at 11:19 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/27/2014 12:13 PM, Andrew Bresticker wrote:
On Wed, Aug 27, 2014 at 10:50 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 08/27/2014 11:38 AM, Andrew
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
The Tegra xHCI controller's firmware communicates requests to the host
processor through a mailbox interface. While there is only a single
communication channel, messages sent by the controller can be divided
into two groups: those intended for
On 08/25/2014 12:48 PM, Stephen Warren wrote:
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra xHCI controller's firmware and the
host processor.
diff --git
a/Documentation/devicetree
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
Add new bindings used for USB support by the Tegra XUSB pad controller.
This includes additional PHY types, USB-specific pinconfig properties, etc.
I'll mainly defer to Thierry for this patch, since he's the expert on
this HW module.
diff
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
The xHCI controller will also send messages
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
Add device-tree binding documentation for the xHCI controller present
on Tegra124 and later SoCs.
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
Add support for the on-chip xHCI host controller present on Tegra SoCs.
The driver is currently very basic: it loads the controller with its
firmware, starts the controller, and is able to service messages sent
by the controller's firmware. The
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
This series adds support for xHCI on NVIDIA Tegra SoCs. This includes:
- adding a driver for the mailbox used to communicate with the xHCI
controller's firmware,
- extending the XUSB pad controller driver to support the USB PHY
types
On 07/02/2014 08:02 AM, Alan Stern wrote:
On Wed, 2 Jul 2014, Tuomas Tynkkynen wrote:
Hi all,
This series fixes a probe order issue with the Tegra EHCI driver.
Basically, the register area of the 1st USB controller contains some
registers that are global to all of the controllers, but that
On 07/02/2014 10:09 AM, Alan Stern wrote:
On Wed, 2 Jul 2014, Stephen Warren wrote:
On 07/02/2014 08:02 AM, Alan Stern wrote:
On Wed, 2 Jul 2014, Tuomas Tynkkynen wrote:
Hi all,
This series fixes a probe order issue with the Tegra EHCI driver.
Basically, the register area of the 1st USB
get called multiple
times. This then leads to warnings about unbalanced regulator_disable if
the EHCI driver is unbound and bound again at runtime.
The series,
Reviewed-by: Stephen Warren swar...@nvidia.com
diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c
-static
On 06/27/2014 09:00 AM, Felipe Balbi wrote:
On Wed, Jun 25, 2014 at 04:30:48PM -0700, Andrew Bresticker wrote:
+static int usb3_phy_power_on(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+ int port = usb3_phy_to_port(phy);
+ int lane =
On 06/27/2014 03:19 PM, Andrew Bresticker wrote:
On Thu, Jun 26, 2014 at 11:07 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 06/25/2014 06:06 PM, Andrew Bresticker wrote:
On Wed, Jun 25, 2014 at 3:37 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 06/18/2014 12:16 AM, Andrew
On 06/25/2014 06:06 PM, Andrew Bresticker wrote:
On Wed, Jun 25, 2014 at 3:37 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add support for the on-chip XHCI host controller present on Tegra SoCs.
The driver is currently very basic: it loads
On 06/25/2014 05:30 PM, Andrew Bresticker wrote:
On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each
On 06/25/2014 04:25 PM, Andrew Bresticker wrote:
Thanks for the review Stephen!
On Wed, Jun 25, 2014 at 2:46 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add new bindings used for USB support by the Tegra XUSB pad controller.
This includes
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add new bindings used for USB support by the Tegra XUSB pad controller.
This includes additional PHY types, USB-specific pinconfig properties, etc.
diff --git
a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra XHCI controller and the host.
Sorry for the slow review.
diff --git
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add device-tree binding documentation for the XHCI controller present
on Tegra124 and later SoCs.
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add device-tree binding documentation for the XHCI controller present
on Tegra124 and later SoCs.
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
+
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
The Tegra XHCI controller communicates requests to the host through
a mailbox interface. Host drivers which can handle these requests,
such as the Tegra XUSB pad controller driver and upcoming Tegra XHCI
host controller driver, can send
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
diff --git
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add support for the on-chip XHCI host controller present on Tegra SoCs.
The driver is currently very basic: it loads the controller with its
firmware, starts the controller, and is able to service messages sent
by the controller's firmware.
On 06/25/2014 04:37 PM, Andrew Bresticker wrote:
On Wed, Jun 25, 2014 at 2:42 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra XHCI
On 06/25/2014 05:01 PM, Andrew Bresticker wrote:
On Wed, Jun 25, 2014 at 2:52 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add device-tree binding documentation for the XHCI controller present
on Tegra124 and later SoCs.
diff --git
On 06/25/2014 05:02 PM, Andrew Bresticker wrote:
On Wed, Jun 25, 2014 at 2:54 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
Add device-tree binding documentation for the XHCI controller present
on Tegra124 and later SoCs.
diff --git
On 06/17/2014 08:17 AM, Tuomas Tynkkynen wrote:
The tegra_ehci_hcd structure is located in the private space allocated
by the core USB code so it must not be accessed after the HCD is
freed.
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
This seems to be a
On 05/14/2014 06:33 PM, Andrew Bresticker wrote:
Initialize the XUSB-related clocks with appropriate parents and rates
for both Tegra114 and Tegra124.
These first 4 clock driver patches look plausible to me, although I
didn't look that hard!
Peter or Mike, if they look OK to you, can you
On 05/14/2014 06:32 PM, Andrew Bresticker wrote:
This is a first pass at the host and PHY drivers necessary for USB3.0
support on Tegra114 and Tegra124. The Tegra XHCI host controller requires
external firmware [1] which must be loaded before using any USB ports owned
by the controller. The
On 05/14/2014 06:33 PM, Andrew Bresticker wrote:
Board-specific USB configuration data is stored in FUSE_SKU_CALIB_0.
Export a function to read it so the PHY can be properly configured.
This patch seems conceptually fine to me. Presumably once Peter's fuse
driver is fleshed out, it can expose
On 05/10/2014 06:00 AM, Vivek Gautam wrote:
Using devm_ioremap_resource() API should actually be preferred over
devm_ioremap(), since the former request the mem region first and then
gives back the ioremap'ed memory pointer.
devm_ioremap_resource() calls request_mem_region(), therby preventing
,
Acked-by: Stephen Warren swar...@nvidia.com
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On 04/15/2014 10:06 AM, Laurent Pinchart wrote:
Platform drivers sometimes need to perform specific handling of hub
control requests. Make this possible by exporting the ehci_hub_control()
function which can then be called from a custom hub control handler in
the default case.
I recall trying
From: Stephen Warren swar...@nvidia.com
To avoid memory fetch underflows with larger USB transfers, Tegra SoCs
need txfill_tuning's txfifothresh register field set to a non-default
value. Add a custom reset override in order to set this up.
These values are recommended practice for all Tegra
On 04/09/2014 07:57 AM, Sergei Shtylyov wrote:
Return to the 'phy' field of 'struct usb_hcd' its historic name
'transceiver'.
This is in preparation to adding the generic PHY support.
Surely if the correct term is transceiver, we should be adding generic
transceiver support not generic PHY
On 04/09/2014 10:27 AM, Sergei Shtylyov wrote:
Hello.
On 04/09/2014 07:31 PM, Stephen Warren wrote:
Return to the 'phy' field of 'struct usb_hcd' its historic name
'transceiver'.
This is in preparation to adding the generic PHY support.
Surely if the correct term is transceiver, we
On 04/09/2014 10:53 AM, Sergei Shtylyov wrote:
On 04/09/2014 08:48 PM, Stephen Warren wrote:
Return to the 'phy' field of 'struct usb_hcd' its historic name
'transceiver'.
This is in preparation to adding the generic PHY support.
Surely if the correct term is transceiver, we should
On 04/09/2014 12:16 PM, Sergei Shtylyov wrote:
Hello.
On 04/09/2014 09:56 PM, Alan Stern wrote:
Ok, the existing field is being replaced by something? I didn't get
that
No, not replaced. I'm adding the support for generic PHY to the
existing
USB PHY support. I thought that was
these defines can be dropped.
Reviewed-by: Stephen Warren swar...@nvidia.com
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On 02/16/2014 05:37 PM, Jingoo Han wrote:
On Friday, February 14, 2014 6:44 PM, Robert Baldyga wrote:
On 02/13/2014 10:10 PM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Hello,
This patch series combines the dwc2 host driver and the s3c-hsotg peripheral
driver into a
On 02/13/2014 11:47 AM, Andre Heider wrote:
On Wed, Feb 12, 2014 at 08:00:18PM -0700, Stephen Warren wrote:
On 02/12/2014 11:52 AM, Andre Heider wrote:
Hi guys,
I just tried today's Linus' master (45f7fdc2ff) with usb-linus (3635c7e2d5)
merged on top to give the latest dwc2 fixes another try
On 02/13/2014 02:10 PM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Hello,
This patch series combines the dwc2 host driver and the s3c-hsotg peripheral
driver into a single dual-roler driver similar to the dwc3.
The patch series moves the s3c-hsotg files into the
On 02/12/2014 11:52 AM, Andre Heider wrote:
Hi guys,
I just tried today's Linus' master (45f7fdc2ff) with usb-linus (3635c7e2d5)
merged on top to give the latest dwc2 fixes another try.
Unfortunately I'm getting various crashes on system startup. Kernel boots
fine, dwc2 and the integrated
On 02/04/2014 02:45 PM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
This means that the driver can be in host or peripheral mode when the
appropriate
connector is used. When an A-cable is plugged in, the driver behaves in host
mode, and when a B-cable is used, the
(link below), so I feel
comfortable saying:
Tested-by: Stephen Warren swar...@wwwdotorg.org
https://github.com/swarren/linux-rpi/commit/f7b9c896153cc0501acecb58053db978ec00a5bf
@@ -2579,9 +2579,11 @@ static void _dwc2_hcd_endpoint_reset(struct usb_hcd
*hcd,
spin_lock_irqsave(hsotg-lock
On 02/01/2014 03:00 AM, Andre Heider wrote:
On Fri, Jan 31, 2014 at 11:48:37PM -0700, Stephen Warren wrote:
On 01/31/2014 11:12 AM, Andre Heider wrote:
On Mon, Jan 13, 2014 at 01:50:09PM -0800, Paul Zimmerman wrote:
The DWC2 driver should now be in good enough shape to move out of
staging. I
On 01/31/2014 12:37 PM, Paul Zimmerman wrote:
From: Andre Heider [mailto:a.hei...@gmail.com]
Sent: Friday, January 31, 2014 11:04 AM
On Fri, Jan 31, 2014 at 12:15:26PM -0600, Felipe Balbi wrote:
On Fri, Jan 31, 2014 at 07:12:36PM +0100, Andre Heider wrote:
On Mon, Jan 13, 2014 at 01:50:09PM
On 01/31/2014 11:12 AM, Andre Heider wrote:
On Mon, Jan 13, 2014 at 01:50:09PM -0800, Paul Zimmerman wrote:
The DWC2 driver should now be in good enough shape to move out of
staging. I have stress tested it overnight on RPI running mass
storage and Ethernet transfers in parallel, and for
when
enqueuing URBs to a LS endpoint on a FS bus.
with my dwc2 testing in NetBSD, so I adapted the change to dwc2.
Tested-by: Stephen Warren swar...@wwwdotorg.org
The built-in USB Ethernet on my model B still works fine with this
change. A USB keyboard/mouse combo isn't reliable (it keeps
that ack happen? I didn't see it. But anyway,
Acked-by: Stephen Warren swar...@nvidia.com
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From: Stephen Warren swar...@nvidia.com
Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.
Cc: tred...@nvidia.com
Cc: pdeschrij...@nvidia.com
Cc: linux-te
On 10/04/2013 12:02 AM, Paul Walmsley wrote:
Selecting CONFIG_USB_EHCI_TEGRA requires CONFIG_USB_ULPI_VIEWPORT.
Otherwise the build can break with:
drivers/usb/phy/phy-tegra-usb.c: In function 'ulpi_open':
drivers/usb/phy/phy-tegra-usb.c:689:31: error:
'ulpi_viewport_access_ops'
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