Hi,
Here is a patch against current 2191 SVN revision to add support for the
ASUS A7V600 motherboard in the flashrom utility.
It disables flash write protection and detects the Pm49fl002 flash chip.
Concerning the port of LinuxBios to this board, I've just been able to
add support for the SuperIO (ITE8212F) and activate the serial port ...
more to come.
Index: flash.h
===================================================================
--- flash.h (révision 2191)
+++ flash.h (copie de travail)
@@ -51,6 +51,7 @@
#define PMC_ID 0x9D /* PMC Manufacturer ID[B code */
#define PMC_49FL004 0x6E /* PMC 49FL004 device code */
+#define PMC_49FL002 0x6D /* PMC 49FL002 device code */
#define WINBOND_ID 0xDA /* Winbond Manufacture ID code */
#define W_29C011 0xC1 /* Winbond w29c011 device code */
Index: flash_enable.c
===================================================================
--- flash_enable.c (révision 2191)
+++ flash_enable.c (copie de travail)
@@ -327,6 +327,56 @@
{0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, // Slave, should not be here, to fix known bug for A01.
};
+
+static int mbenable_asus_a7v600(void)
+{
+ unsigned char b;
+
+ printf("Disableing ASUS Flash protection\n");
+
+ /* get io privilege */
+ if (iopl(3) != 0) {
+ perror("Can not set io priviliage");
+ exit(1);
+ }
+
+ /*
+ * The following code is based on a BIOS disassembly
+ * The write (un)protection routines can be found in the BIOS memory,
+ * looking for 'ASUS_FLASH' header
+ *
+
+ Format of Asustek Flash interface:
+ Offset Size Description
+ 00h 10 BYTEs signature "ASUS_FLASH"
+ 0Ah 6 BYTEs blanks (padding)
+ 10h WORD interface version??? (current PFLASH.EXE requires 0101h)
+ 12h DWORD -> position-independent code to enable shadowing
+ 16h WORD size of code pointed at by previous field (<= 0400h)
+ 18h DWORD -> position-independent code to disable shadowing
+ 1Ch WORD size of code pointed at by previous field (<= 0400h)
+
+ */
+
+ // E42C
+ // ??
+ b = inb(0xE42C);
+ outb(b & 0xFE, 0xE42C);
+
+ // PCI
+ // VT8237 Rom Write enable
+ outl(0x80008840, 0xCF8);
+ b = inb(0xCFC);
+ outb(b | 0x10, 0xCFC);
+
+ // Access to the IT8212F GPIO 32
+ // which seems to be linked to the WP pin of the Pm49fl002
+ b = inb(0x372);
+ outb(b | 4, 0x372);
+
+ return 0;
+}
+
static int mbenable_island_aruma(void)
{
#define EFIR 0x2e // Exteneded function index register, either 0x2e or 0x4e
@@ -388,6 +438,7 @@
static MAINBOARD_ENABLE mbenables[] = {
{ "ISLAND", "ARUMA", mbenable_island_aruma },
+ { "ASUS", "A7V600", mbenable_asus_a7v600 },
};
int enable_flash_write()
Index: flashchips.c
===================================================================
--- flashchips.c (révision 2191)
+++ flashchips.c (copie de travail)
@@ -66,6 +66,8 @@
probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub,NULL},
{"SST49LF008A", SST_ID, SST_49LF008A, NULL, 1024, 64 * 1024 ,
probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub, NULL},
+ {"Pm49FL002", PMC_ID, PMC_49FL002, NULL, 256, 16 * 1024,
+ probe_jedec, erase_chip_jedec, write_49fl004,NULL},
{"Pm49FL004", PMC_ID, PMC_49FL004, NULL, 512, 64 * 1024,
probe_jedec, erase_chip_jedec, write_49fl004,NULL},
{"W29C011", WINBOND_ID, W_29C011, NULL, 128, 128,
--
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