Hi there.
While trying to bring up X.org on this beast, I've stumbled upon this
oops in radeon.ko
(right on the first write attempt):
[drm] Initialized drm 1.1.0 20060810
pci 0005:01:00.0: enabling device (0140 - 0143)
[drm] Initialized radeon 1.29.0 20080528 on minor 0
[drm] Setting GART
On Tue, Feb 10, 2009 at 12:30:11PM +0800, Li Jun (Aaron) wrote:
Hi,
When I make zImage, the errors below came out. Any tips?
[linux-2.6-virtex]$ make zImage
CHK include/linux/version.h
CHK include/linux/utsrelease.h
CALLscripts/checksyscalls.sh
CHK
On Tue, Feb 10, 2009 at 11:54 AM, Sachin P. Sant sach...@in.ibm.com wrote:
Sachin P. Sant wrote:
Hi Stephen,
Todays next randconfig build on powerpc fails with
CC mm/slqb.o
mm/slqb.c: In function __slab_free:
mm/slqb.c:1648: error: implicit declaration of function
Hi all,
Maybe a silly questions, but what is the suggested way for handling a
processor which has a PCIe interface, but the interface is not
configured to be the root complex (endpoint only)?
Should the PCIe interface appear in the dts? If so, with what
parameters?
Should the kernel config
On Fri, Feb 6, 2009 at 8:00 AM, Timur Tabi ti...@freescale.com wrote:
The i2c_wait() function is using wait_event_interruptible_timeout() to wait
for
the I2C controller to signal that it has completed an I2C bus operation. If
the process that causes the I2C operation terminated abruptly, the
commit e85477f516c2de7ed515fcf94ceab5282eba7fa4 (powerpc/83xx: Fix
TSEC0 workability on MPC8313E-RDB boards) fixed TSEC0 workability for
rev. A and rev. B boards by using fixed-link property for VSC 7385
5-port switch. But rev. C boards have an option where TSEC0 connected
to a Marvell PHY, which
On Fri, Feb 06, 2009 at 08:00:37AM -0600, Timur Tabi wrote:
The i2c_wait() function is using wait_event_interruptible_timeout() to wait
for
the I2C controller to signal that it has completed an I2C bus operation. If
the process that causes the I2C operation terminated abruptly, the wait will
On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote:
commit e85477f516c2de7ed515fcf94ceab5282eba7fa4 (powerpc/83xx: Fix
TSEC0 workability on MPC8313E-RDB boards) fixed TSEC0 workability for
rev. A and rev. B boards by using fixed-link property for VSC 7385
5-port switch. But rev. C boards have
I might have missed this but what u-boot rev are you using?
- k
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cbe_cpufreq has a partial dependency on cbe_cpufreq_pmi, which cannot
be easily expressed in Kconfig. This fixes it by introducing an
extra Kconfig symbol CBE_CPUFREQ_PMI_ENABLE. To make the dependency
clearer, turn PPC_PMI into an automatic symbol.
Reported-by: Michael Neuling mi...@neuling.org
On Tue, 10 Feb 2009 08:59:57 -0600, Timur Tabi wrote:
On Fri, Feb 6, 2009 at 8:00 AM, Timur Tabi ti...@freescale.com wrote:
The i2c_wait() function is using wait_event_interruptible_timeout() to wait
for
the I2C controller to signal that it has completed an I2C bus operation. If
the
Jean Delvare wrote:
No, that's something for either Ben Dooks (Cc'd) or the powerpc tree.
This patch has nothing to do with ARM, so Kumar will pick it up, if you
ACK it.
--
Timur Tabi
Linux kernel developer at Freescale
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On Tue, 10 Feb 2009 10:01:54 -0600, Timur Tabi wrote:
Jean Delvare wrote:
No, that's something for either Ben Dooks (Cc'd) or the powerpc tree.
This patch has nothing to do with ARM, so Kumar will pick it up, if you
ACK it.
Why are you mentioning ARM?
From MAINTAINERS:
I2C SUBSYSTEM
P:
After the last changes, the mv643xx_eth driver now detects
a spurious interface on port 0. Since only port 1 is actually
connected to a PHY, remove its description.
Signed-off-by: Gabriel Paubert paub...@iram.es
---
Tested on the last batch of Pegasos produced. Caveat: do not enable
the Marvell
Jean Delvare wrote:
To the best of my knowledge i2c-mpc falls into the embedded platforms
category and is thus under Ben's responsibility.
I don't see his Signed-off-by on any patch to i2c-mpc.c for the past
three years (at least). I do see yours, however. You have directly
applied similar
On Tue, Feb 10, 2009 at 07:39:47AM -0500, Scott Coulter wrote:
Hi all,
Maybe a silly questions, but what is the suggested way for handling a
processor which has a PCIe interface, but the interface is not
configured to be the root complex (endpoint only)?
Should the PCIe interface appear
2009/2/9 Mike Mason mm...@us.ibm.com:
The EEH code disables and enables interrupts during the
device recovery process. This is unnecessary for MSI
and MSI-X interrupts because they are effectively disabled
by the DMA Stopped state when an EEH error occurs. The current code is also
incorrect
The following commit:
commit 64b3d0e8122b422e879b23d42f9e0e8efbbf9744
Author: Benjamin Herrenschmidt b...@kernel.crashing.org
Date: Thu Dec 18 19:13:51 2008 +
powerpc/mm: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED
broke setting of the _PAGE_COHERENT bit in the PPC HW PTE. Since
I've posted a patch that I believe should fix your issue.
- k
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I'm resubmitting this patch with a couple changes
suggested by Michael Ellerman. 1) the new functions
should be static, and 2) some people may object to
including unrelated formating changes.
=
The EEH code disables and enables interrupts
Hi,
I am trying to get a 2.6.27.6 kernel to boot on an MPC8568E processor. The
kernel/patches/compiler came from Freescale's LTIB release in December 2008.
Using the same kernel source, toolchain, and ramdisk image, I can boot and run
an SMP kernel on the MPC8572E processor which is on the
Scott Coulter wrote:
Bad trap at PC: 100b7354, SR: 2d000, vector=2020
init has generated signal 5 but has no handler for it
Kernel panic - not syncing: Attempted to kill init!
Rebooting in 180 seconds..
I am not using a debugger, so I can't see where the SIGTRAP would be coming
from.
That's
Scott
That's an SPE Unavailable exception. Try enabling CONFIG_SPE.
That was the problem. Thanks for your help.
Scott
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This device tree does not provide the correct CPU name, as various CPU
models and revisions are used in AmigaOnes. Also the PCI root node does
not contain a interrupt mapping property, as all boards have different
interrupt routing. However the kernel can do a 1:1 mapping of all PCI
interrupts, as
This adds the bootwrapper for the cuImage target and a compatible property
check for pnpPNP,501 to the generic serial console support code.
The default link address for the cuImage target is set to 0x80. This
allows to boot the kernel with AmigaOS4's second level bootloader, which
always loads
CONFIG_CC_OPTIMIZE_FOR_SIZE is selected, because otherwise the kernel
wouldn't boot. The AmigaOne's U-boot firmware seems to have a problem
loading uImages bigger than 1.8 MB.
Signed-off-by: Gerhard Pircher gerhard_pirc...@gmx.net
---
arch/powerpc/configs/amigaone_defconfig | 1636
cbe_cpufreq has a partial dependency on cbe_cpufreq_pmi, which cannot
be easily expressed in Kconfig. This fixes it by introducing an
extra Kconfig symbol CBE_CPUFREQ_PMI_ENABLE. To make the dependency
clearer, turn PPC_PMI into an automatic symbol.
Reported-by: Michael Neuling
James Bottomley wrote:
On Mon, 2009-02-09 at 11:11 +1100, Benjamin Herrenschmidt wrote:
The PS3 platform code wants to use some of the standard SCSI types from
there though, as they are part of the hypervisor ABI. (And in fact it
can be argued that non-block devices using SCSI do exist, such
On Feb 10, 2009, at 2:57 PM, Kumar Gala wrote:
The following commit:
commit 64b3d0e8122b422e879b23d42f9e0e8efbbf9744
Author: Benjamin Herrenschmidt b...@kernel.crashing.org
Date: Thu Dec 18 19:13:51 2008 +
powerpc/mm: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED
broke setting of
On Tue, 2009-02-10 at 11:14 -0600, Linas Vepstas wrote:
2009/2/9 Mike Mason mm...@us.ibm.com:
The EEH code disables and enables interrupts during the
device recovery process. This is unnecessary for MSI
and MSI-X interrupts because they are effectively disabled
by the DMA Stopped state
On Tue, 2009-02-10 at 13:12 -0800, Mike Mason wrote:
I'm resubmitting this patch with a couple changes
suggested by Michael Ellerman. 1) the new functions
should be static, and 2) some people may object to
including unrelated formating changes.
2009/2/10 Michael Ellerman mich...@ellerman.id.au:
On Tue, 2009-02-10 at 11:14 -0600, Linas Vepstas wrote:
On a somewhat-related note: there was an issue (I forget
the details) where the kernel needed to shadow some sort
of MSI state so that it could be correctly, um, kept-track-of,
after an
The Power ISA 2.06 added power of two page sizes to the embedded MMU
architecture. Its done it such a way to be code compatiable with the
existing HW. Made the minor code changes to support both power of two
and power of four page sizes. Also added some new MAS bits and macros
that are defined
On Tue, Feb 10, 2009 at 10:21:04AM -0600, Timur Tabi wrote:
Jean Delvare wrote:
To the best of my knowledge i2c-mpc falls into the embedded platforms
category and is thus under Ben's responsibility.
I don't see his Signed-off-by on any patch to i2c-mpc.c for the past
three years (at
On Fri, Feb 06, 2009 at 08:00:37AM -0600, Timur Tabi wrote:
The i2c_wait() function is using wait_event_interruptible_timeout() to wait
for
the I2C controller to signal that it has completed an I2C bus operation. If
the process that causes the I2C operation terminated abruptly, the wait will
The Power ISA 2.06 added power of two page sizes to the embedded MMU
architecture. Its done it such a way to be code compatiable with the
existing HW. Made the minor code changes to support both power of two
and power of four page sizes. Also added some new MAS bits and macros
that are defined
Create a new header that becomes a single location for defining PowerPC
opcodes used by code that is either generationg instructions
at runtime (fixups, debug, etc.), emulating instructions, or just
compiling instructions old assemblers don't know about.
We currently don't handle the floating
Hi Kumar,
On Tue, 10 Feb 2009 18:28:30 -0600 Kumar Gala ga...@kernel.crashing.org wrote:
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2009 Freescale Semicondutor, Inc. All rights reserved.
If you are going to use All rights reserved, you should also
This patch reworks the way we do I and D cache coherency on PowerPC.
The old way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and = POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec
Hi Jon,
Jon Tollefson wrote:
This patch takes out the reserved region loop from inside
the loop that goes over each node. It looks up the active region containing
the start of the reserved region. If it extends past that active region then
it adjusts the size and gets the next active region
On Tue, 2009-02-10 at 19:17 -0800, Geoff Levand wrote:
Hi Jon,
Jon Tollefson wrote:
This patch takes out the reserved region loop from inside
the loop that goes over each node. It looks up the active region containing
the start of the reserved region. If it extends past that active
On Wed, 2009-02-04 at 22:26 +0100, Ingo Molnar wrote:
+include $(srctree)/arch/$(SRCARCH)/Makefile
+
# arch Makefile may override CC so keep this after arch Makefile is
included
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC)
-print-file-name=include)
CHECKFLAGS +=
We have get_vm_area_caller() and __get_vm_area() but not __get_vm_area_caller()
On powerpc, I use __get_vm_area() to separate the ranges of addresses given
to vmalloc vs. ioremap (various good reasons for that) so in order to be
able to implement the new caller tracking in /proc/vmallocinfo, I
Hi !
The powerpc.git test branch has been rebased on top of next with the
addition of the following patches:
commit 8d30c14cab30d405a05f2aaceda1e9ad57800f36
Author: Benjamin Herrenschmidt b...@kernel.crashing.org
Date: Tue Feb 10 16:02:37 2009 +
powerpc/mm: Rework I$/D$ coherency (v3)
Hi Linus !
This is a single patch, to fix a regression introduced in this merge
window. Please apply.
The following changes since commit 1db8508cf483dc1ecf66141f90a7c03659d69512:
Stefan Richter (1):
hugetlbfs: fix build failure with !CONFIG_HUGETLBFS
are available in the git
James Bottomley wrote:
Actually, I think the fix lies in scsi.h ... we can make that into a
nicely independent protocol header file. Your current woes come because
it pulls in scsi_cmnd.h ... perhaps just getting rid of this will fix
it.
Can the rest of linux-scsi verify that the fix below
Create a new header that becomes a single location for defining PowerPC
opcodes used by code that is either generationg instructions
at runtime (fixups, debug, etc.), emulating instructions, or just
compiling instructions old assemblers don't know about.
We currently don't handle the floating
On Feb 10, 2009, at 6:40 PM, Stephen Rothwell wrote:
Hi Kumar,
On Tue, 10 Feb 2009 18:28:30 -0600 Kumar Gala ga...@kernel.crashing.org
wrote:
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2009 Freescale Semicondutor, Inc. All rights
reserved.
If
The e500mc core supports the new tlbilx instructions that do core
local invalidates and also provide us the ability to take down
all TLB entries matching a given PID.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
(depends on the powerpc: Unify opcode definitions and support patch)
Hi Kumar,
On Wed, 11 Feb 2009 00:11:32 -0600 Kumar Gala ga...@kernel.crashing.org wrote:
posted a new version that should fix this (added GPL license)
Thanks.
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
pgpIDPl9omBfj.pgp
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