On May 21, 2010, at 9:16 AM, Haiying Wang wrote:
P1021 is a dual e500v2 core based SOC with:
* 3 eTSECs (eTSEC1/3 RGMII, eTSEC2 SGMII on this board)
* 2 PCIe Controller
* 1 USB2.0 controller
* eSDHC, eSPI, I2C, DUART
* eLBC (NAND, BCSR, PMC0/1)
* Security Engine (SEC 3.3.2)
* Quicc
Grant Likely wrote:
On Mon, May 24, 2010 at 10:25 AM, Martyn Welch martyn.we...@ge.com wrote:
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO
Hi folks !
Anybody aware of anything other than Cell using that driver ?
I'd like to make it a platform driver instead of having something that
pokes at anything that has a device_type set to nvram (which is
gross and bogus). But I need to know what platforms to fixup...
Cheers,
Ben.
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
the device tree for this information, failing back to the hardcoded values
if
On Tue, May 25, 2010 at 05:43:59PM +1000, Benjamin Herrenschmidt wrote:
Anybody aware of anything other than Cell using that driver ?
I'd like to make it a platform driver instead of having something that
pokes at anything that has a device_type set to nvram (which is
gross and bogus). But I
One day I'll manage to hit Reply or Reply All correctly...
Benjamin Herrenschmidt wrote:
Hi folks !
Anybody aware of anything other than Cell using that driver ?
I'd like to make it a platform driver instead of having something that
pokes at anything that has a device_type set to nvram
Hi All,
Please find a new version of the hw-breakpoint patchset with
changes as described below.
The patchset, passes when tested against breakpoints caused by user-space
instructions but fails against kernel-space instructions (as a result of
emulate_step() failure). They should begin to
Certain architectures (such as PowerPC Book III S) have a need to cleanup
data-structures before the breakpoint is unregistered. This patch introduces
an arch-specific hook in release_bp_slot() along with a weak definition in
the form of a stub funciton.
Signed-off-by: K.Prasad
Implement perf-events based hw-breakpoint interfaces for PowerPC Book III S
processors. These interfaces help arbitrate requests from various users and
schedules them as appropriate.
Signed-off-by: K.Prasad pra...@linux.vnet.ibm.com
---
arch/powerpc/Kconfig |1
An alignment interrupt may intervene between a DSI/hw-breakpoint exception
and the single-step exception. Enable the alignment interrupt (through
modifications to emulate_single_step()) to notify the single-step exception
handler for proper restoration of hw-breakpoints.
Signed-off-by: K.Prasad
A signal delivered between a hw_breakpoint_handler() and the
single_step_dabr_instruction() will not have the breakpoint active during
signal handling (since breakpoint will not be restored through single-stepping
due to absence of MSR_SE bit on the signal frame). Enable breakpoints before
signal
On Mon, May 24, 2010 at 09:38:14PM -0500, Kumar Gala wrote:
The following changes since commit 99ec28f183daa450faa7bdad6f932364ae325648:
FUJITA Tomonori (1):
powerpc: Remove unused 'protect4gb' boot parameter
are available in the git repository at:
Ben, don't forget I still have some
On Tue, May 25, 2010 at 05:43:59PM +1000, Benjamin Herrenschmidt wrote:
Hi folks !
Anybody aware of anything other than Cell using that driver ?
I'd like to make it a platform driver instead of having something that
pokes at anything that has a device_type set to nvram (which is
gross and
Hi,
I am running 2.6.29.1 on MPC8572 dual core with SMP enabled on our customized
board.
I have two applications running. One is to access CPLD registers via PCI bus
and then sleep in an endless loop, the other is to send (and of course receive
data) via TSEC port in an endless loop.
Sooner
On Tue, May 25, 2010 at 2:09 AM, Martyn Welch martyn.we...@ge.com wrote:
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
(cc'ing Josh Boyer and John Linn)
On Thu, May 20, 2010 at 4:01 AM, Sergey Temerkhanov
temerkha...@cifronik.ru wrote:
This patch enables support for Xilinx Virtex 4 FX singe-float FPU.
Changelog v1-v2:
-Added MSR_AP bit definition
-Renamed CONFIG_XILINX_FPU to
Grant Likely wrote:
On Tue, May 25, 2010 at 2:09 AM, Martyn Welch martyn.we...@ge.com wrote:
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code
On Tue, 2010-05-25 at 09:15 -0500, Li, Jianlin (Jianlin) wrote:
Hi,
I am running 2.6.29.1 on MPC8572 dual core with SMP enabled on our customized
board.
I have two applications running. One is to access CPLD registers via PCI bus
and then sleep in an endless loop, the other is to send
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