Hello
Heiko Schocher wrote:
- add binding to OF, compatible name smi,sm501
Signed-off-by: Heiko Schocher h...@denx.de
cc: linux-fb...@vger.kernel.org
cc: devicetree-disc...@ozlabs.org
cc: Ben Dooks b...@simtec.co.uk
cc: Vincent Sanders vi...@simtec.co.uk
cc: Samuel Ortiz
On Tue, Mar 15, 2011 at 2:13 AM, Mahesh J Salgaonkar
mah...@linux.vnet.ibm.com wrote:
During free we do free all of them including RMO region. But since the rtas
region is always on top of RMO, crashkernel memory overlaps rtas region and
we endup freeing that even, which is causing the crash.
On Wed, Feb 09, 2011 at 05:08:08PM -0600, Dave Kleikamp wrote:
so that it can use information from the device tree.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc:
On Tue, Feb 15, 2011 at 09:54:45AM -0500, Josh Boyer wrote:
Hi Ben,
Please pull the 'next' branch of the 4xx tree. These commits have been
sitting there for a while and I wanted to get them into your branch
before tackling the latest round of 476 stuff from Shaggy.
Ben, I don't see any of these
On Mar 5, 2011, at 3:05 PM, Kumar Gala wrote:
From: Kumar Gala kumar.g...@freescale.com
If the spin table is located in the linear mapping (which can happen if
we have 4G or more of memory) we need to access the spin table via a
cacheable coherent mapping like we do on ppc32 (and do
On Mar 11, 2011, at 1:02 AM, Holger Brunck wrote:
Beside the MPC 8360 based board kmeter1 other km83xx boards
from keymile will follow. Therefore the board specific naming
kmeter1 for functions and files were replaced with km83xx.
Additionally some updates were made:
- update defconfig
On Mar 10, 2011, at 5:52 AM, Holger Brunck wrote:
The mgcoge board from keymile is now base for some other
similar boards. Therefore the board specific name mgcoge
was renamed to a generic name km82xx. Additionally some
enhancements were made:
- rework partition table in dts file
On Jan 25, 2011, at 12:02 AM, Liu Yu wrote:
This errata can occur if a single-precision floating-point, double-precision
floating-point or vector floating-point instruction on a mispredicted branch
path signals one of the floating-point data interrupts which are enabled by
the
SPEFSCR
On Jan 13, 2011, at 6:11 AM, Holger Brunck wrote:
The MPC852 based mgsuvd board from Keymile was initially ported,
but later on not developed further. This patch removes the respective
files to decrease merging conflicts and unneeded maintenance.
Signed-off-by: Holger Brunck
On Jan 19, 2011, at 3:07 AM, Xulei wrote:
Update p1022 sata compatible to fsl,p1022-sata, fsl,pq-sata-v2.
p1022ds sata controller is v2 version comparing previous FSL sata
controller, for example, mpc8536.
Signed-off-by: Lei Xu b33...@freescale.com
Signed-off-by: Roy Zang
On Feb 8, 2011, at 5:39 PM, Timur Tabi wrote:
Improve the status messages that are displayed during some operations of the
PowerPC watchdog timer driver. When the watchdog is enabled, the timeout is
displayed as a number of seconds, instead of an obscure period. The
period
is the
On Dec 20, 2010, at 8:59 AM, Ben Dooks wrote:
On Mon, Dec 20, 2010 at 03:37:34PM +0800, Xulei wrote:
Currently I2C_MPC supports 32bit system only, then this
modification makes it support 32bit and 64bit system both.
Signed-off-by: Xulei b33...@freescale.com
This been build or run
On Nov 16, 2010, at 8:28 PM, Shan Hai wrote:
Conversion from float to integer should based on both the instruction
encoding and the sign of the operand.
Signed-off-by: Shan Hai shan@windriver.com
---
arch/powerpc/math-emu/math_efp.c | 12
1 files changed, 8
On Aug 31, 2010, at 10:48 AM, Julia Lawall wrote:
Add a call to of_node_put in the error handling code following a call to
of_find_compatible_node or of_find_node_by_type.
This patch also substantially reorganizes the error handling code in the
function, to that it is possible first to
On Feb 16, 2011, at 8:59 AM, Jean-Denis Boyer wrote:
Hi.
There is a bug in the function gtm_set_ref_timer16.
When called, it correctly sets the requested timer,
but the other timer that shares the register GTCFR is reset.
The parameter 'clear' passed to macro clrsetbits_8 should not be
a
On Jan 19, 2011, at 3:07 AM, Xulei wrote:
In FSL sata v2 block, the snoop bit of PRDT Word3 description
information is at bit28 instead of bit22.
This patch adds FSL sata v2 probe and resolve this difference.
Signed-off-by: Lei Xu b33...@freescale.com
Signed-off-by: Roy Zang
On Tue, Mar 15, 2011 at 10:44 AM, Kumar Gala ga...@kernel.crashing.org wrote:
On Dec 20, 2010, at 8:59 AM, Ben Dooks wrote:
On Mon, Dec 20, 2010 at 03:37:34PM +0800, Xulei wrote:
Currently I2C_MPC supports 32bit system only, then this
modification makes it support 32bit and 64bit system
On Mar 15, 2011, at 10:56 AM, Timur Tabi wrote:
On Tue, Mar 15, 2011 at 10:44 AM, Kumar Gala ga...@kernel.crashing.org
wrote:
On Dec 20, 2010, at 8:59 AM, Ben Dooks wrote:
On Mon, Dec 20, 2010 at 03:37:34PM +0800, Xulei wrote:
Currently I2C_MPC supports 32bit system only, then this
Currently i2c-mpc supports 32bit system only, this modification makes it
supported on both 32-bit and 64-bit systems. The P5020 is the first
64-bit PPC system with the i2c-mpc controller.
Based in patch from Xulei b33...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
On Jan 19, 2011, at 4:30 PM, Stuart yoder wrote:
From: Stuart Yoder stuart.yo...@freescale.com
define the binding for compatible = fsl,mpic, including
the definition of 4-cell interrupt specifiers. The
3rd and 4th cells are needed to define additional
types of interrupt source outside
ok, it seems that no one is interested to fix Pegasos1 G3 600MHz support.
But if someone is capable (i don't have this skill) here what it
happens reading from serial debug console untill it freezes with
linux-2.6.36.4
Pegasos Boot Strap (c) 2002 bplan GmbH
Running on CPU PVR:00083311
PLL
On Tue, Mar 15, 2011 at 03:52:38PM +0800, Américo Wang wrote:
On Tue, Mar 15, 2011 at 2:13 AM, Mahesh J Salgaonkar
mah...@linux.vnet.ibm.com wrote:
During free we do free all of them including RMO region. But since the rtas
region is always on top of RMO, crashkernel memory overlaps rtas
On Tue, Mar 15, 2011 at 05:44:49PM +0100, nello martuscielli wrote:
But if someone is capable (i don't have this skill) here what it
happens reading from serial debug console untill it freezes with
linux-2.6.36.4
What is the last kernel version working on that machine? If you have a
working
Original-Nachricht
Datum: Tue, 15 Mar 2011 17:44:49 +0100
Von: nello martuscielli ppc.ad...@gmail.com
An:
CC: linuxppc-dev@lists.ozlabs.org, acrux @ cruxppc acrux...@libero.it
Betreff: Re: any chance to use a modern linux kernel on Pegasos1 G3 ?
ok, it seems that no one
On Jan 17, 2011, at 2:25 PM, Scott Wood wrote:
Now handles multiple ranges, doesn't make assumptions about interrupt
specifier format, and doesn't claim interrupts that don't correspond to an
available range.
Also has some better error checking.
The device tree binding is updated to
Hi Kumar,
I allready had it in the watchdog tree for a couple of weeks (and thus also in
linux-next).
Are you going to sent it of to Linus or will I sent it over via the watchdog
tree?
Thanks in advance,
Wim.
On Feb 8, 2011, at 5:39 PM, Timur Tabi wrote:
Improve the status messages
On Tue, Mar 15, 2011 at 11:02:43AM -0500, Kumar Gala wrote:
Currently i2c-mpc supports 32bit system only, this modification makes it
supported on both 32-bit and 64-bit systems. The P5020 is the first
64-bit PPC system with the i2c-mpc controller.
Based in patch from Xulei
On Tue, Mar 15, 2011 at 06:14:48PM +0100, Gerhard Pircher wrote:
Original-Nachricht
Datum: Tue, 15 Mar 2011 17:44:49 +0100
Von: nello martuscielli ppc.ad...@gmail.com
An:
CC: linuxppc-dev@lists.ozlabs.org, acrux @ cruxppc acrux...@libero.it
Betreff: Re: any chance
On Mar 15, 2011, at 1:19 PM, Wim Van Sebroeck wrote:
Hi Kumar,
I allready had it in the watchdog tree for a couple of weeks (and thus also
in linux-next).
Are you going to sent it of to Linus or will I sent it over via the watchdog
tree?
Thanks in advance,
Wim.
I'll drop it from my
From: Stuart Yoder stuart.yo...@freescale.com
-changed name from 'no-reset' to 'pic-not-reset' be consisent with
Meador Inge's open pic binding patch
-update definition
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
Documentation/powerpc/dts-bindings/fsl/mpic.txt |7 +--
1
On Mar 15, 2011, at 1:37 PM, Stuart Yoder wrote:
From: Stuart Yoder stuart.yo...@freescale.com
-changed name from 'no-reset' to 'pic-not-reset' be consisent with
Meador Inge's open pic binding patch
-update definition
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
On Oct 17, 2010, at 9:51 AM, Vasiliy Kulikov wrote:
sram_params.sram_size and sram_params.sram_offset were unsigned.
If get_cache_sram_size() or get_cache_sram_offset() returns error code
then it is not seen to the caller. Made sram_size and sram_offset signed.
Signed-off-by: Vasiliy
On Oct 14, 2010, at 8:51 AM, Timur Tabi wrote:
On Thu, Oct 14, 2010 at 8:25 AM, Kumar Gala ga...@kernel.crashing.org wrote:
+CONFIG_MATH_EMULATION=y
Don't these chips have hardware FP?
removed.
+CONFIG_E1000=y
+CONFIG_E1000E=y
Are you sure you want these on by default? We may
Original-Nachricht
Datum: Tue, 15 Mar 2011 18:49:24 +0100
Von: Sven Luther s...@z-innov.com
An: Gerhard Pircher gerhard_pirc...@gmx.net
CC: nello martuscielli ppc.ad...@gmail.com, linuxppc-dev@lists.ozlabs.org,
acrux...@libero.it
Betreff: Re: any chance to use a modern
The following changes since commit 964a29962c278ddff8a199f23d7c9ef35152a0fe:
powerpc/pseries: Disable MSI using new interface if possible (2011-03-11
14:18:24 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Anatolij
- all the integration parameters have been captured by the binding.
- the block name really uniquely identifies this hardware.
Some advocate putting SoC names everywhere in case software needs
to work around some chip-specific bug, but more precise SoC
information already exists in SVR, and board
On Tue, Mar 15, 2011 at 09:08:55PM +0100, Gerhard Pircher wrote:
Well, since this is long dead hardware not produced anymore, i don't see
how the OF could have unbroken itself by moving to powerpc.
It has been age since i looked into this, but to the best of my knowledge
(and i wrote
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Hash: SHA1
On Tue, 15 Mar 2011 22:41:49 +0100
Sven Luther sven.lut...@z-innov.com wrote:
On Tue, Mar 15, 2011 at 09:08:55PM +0100, Gerhard Pircher wrote:
Well, since this is long dead hardware not produced anymore, i
don't see how the OF could have
On Tue, Mar 15, 2011 at 04:52:20PM -0500, Kim Phillips wrote:
- all the integration parameters have been captured by the binding.
- the block name really uniquely identifies this hardware.
Some advocate putting SoC names everywhere in case software needs
to work around some chip-specific
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