POWER8 allows read and write of the DSCR in userspace. We added
kernel emulation so applications could always use the instructions
regardless of the CPU type.
Unfortunately there are two SPRs for the DSCR and we only added
emulation for the privileged one. Add code to match the non
privileged
Jeff --
Thanks for the quick reply -- sorry that it took me a few days to get
back to you.
[Also, apologies if anyone gets a dupe -- I'm working on a new mail
configuration, and while I did test it, something went sideways the
first time I tried to send this.]
Jeff Garzik writes:
Regarding
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, April 30, 2013 4:30 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; Segher Boessenkool; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org
Subject: Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to
fix
Hi Linus !
Here's the next pack of powerpc changes !
The main highlights this time around are:
- A pile of addition POWER8 bits and nits, such as updated performance
counter support (Michael Ellerman), new branch history buffer support
(Anshuman Khandual), base support for the new PCI host
Currently, the OPAL exception vectors are registered before the feature
fixups are processed. This means that the now-firmware-owned vectors
will likely be overwritten by the kernel.
This change moves the exception registration code to an early initcall,
rather than at machine_init time.
On Tue, Apr 30, 2013 at 05:09:32PM +, Sethi Varun-B16395 wrote:
Would you take this patchset for 3.10 merge?
Not this time. The final patch came in very late and is pretty big too.
For code of that size I would like to have a few weeks more testing in
next and probably also a non-Freescale
On 02.05.2013, at 07:17, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
Add the missing unlock before return from function set_base_addr()
when disables the mapping.
Introduced by commit 5df554ad5b7522ea62b0ff9d5be35183494efc21
(kvm/ppc/mpic: in-kernel MPIC
-Original Message-
From: j...@8bytes.org [mailto:j...@8bytes.org]
Sent: Thursday, May 02, 2013 3:46 PM
To: Sethi Varun-B16395
Cc: io...@lists.linux-foundation.org; linuxppc-dev@lists.ozlabs.org;
linux-ker...@vger.kernel.org; ga...@kernel.crashing.org;
b...@kernel.crashing.org;
This is SCLPC device driver for the Freescale MPC512x.
It is needed for Direct Memory Access to the devices on LocalPlus Bus.
Signed-off-by: Alexander Popov a13xp0p0...@gmail.com
---
arch/powerpc/boot/dts/mpc5121.dtsi| 8 +-
arch/powerpc/include/asm/mpc5121.h| 32 ++
This module tests Direct Memory Access to some device on LocalPlus Bus
for Freescale MPC512x. In other words it tests the bundle
of mpc512x_lpbfifo and mpc512x_dma drivers.
This testing driver was multiply used with static RAM (CY62167EV30LL-45ZXI)
which lives on LocalPlus Bus on our board. This
On 04/25/2013 02:34 PM, Lucas Kannebley Tavares wrote:
On 04/24/2013 08:48 PM, Tony Breeds wrote:
diff --git a/arch/powerpc/platforms/pseries/pci.c
b/arch/powerpc/platforms/pseries/pci.c
index 0b580f4..7f9c956 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++
On 04/30/2013 10:54:25 PM, Alan Modra wrote:
On Tue, Apr 30, 2013 at 07:24:20PM -0700, Eric Dumazet wrote:
li 11,1
ld 0,0(9)
rldimi 0,11,31,32
std 0,0(9)
blr
.ident GCC: (GNU) 4.6.3
You can see ld 0,0(9) is used : its a 64 bit load.
Yup. This is not a powerpc64
On 04/28/2013 12:20:08 AM, Jia Hongtao wrote:
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is
Kumar,
In fsl_pci.c there is a change you made a while back:
powerpc/fsl: Setup PCI inbound window based on actual amount of memory
...and there is this comment in the code:
/* PCIe can overmap inbound outbound since RX TX are separated */
if (early_find_capability(hose, 0, 0,
On 05/02/2013 12:05:42 PM, Yoder Stuart-B08248 wrote:
Kumar,
In fsl_pci.c there is a change you made a while back:
powerpc/fsl: Setup PCI inbound window based on actual amount of
memory
...and there is this comment in the code:
/* PCIe can overmap inbound outbound since RX TX are
On Wed, May 01, 2013 at 03:28:09PM +0400, Alexander Popov wrote:
The initial version of this driver supports only memory to memory
data transfers.
Data transfers between memory and i/o memory require more delicate TCD
(Transfer Control Descriptor) configuration and DMA channel service
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, May 02, 2013 10:44 PM
To: Yoder Stuart-B08248
Cc: ga...@kernel.crashing.org; Sethi Varun-B16395; linuxppc-
d...@lists.ozlabs.org
Subject: Re: pci overmapping
On 05/02/2013 12:05:42 PM, Yoder Stuart-B08248 wrote:
On 05/02/2013 01:09:53 PM, Sethi Varun-B16395 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, May 02, 2013 10:44 PM
To: Yoder Stuart-B08248
Cc: ga...@kernel.crashing.org; Sethi Varun-B16395; linuxppc-
d...@lists.ozlabs.org
Subject: Re: pci overmapping
On
On Wed, 2013-05-01 at 08:10 -0700, Stephen Hemminger wrote:
These kind of errors are pretty hard to find, its a pity to spend
time
on them.
There is a checkbin target inside arch/powerpc/Makefile
Shouldn't a check be added there to block building kernel with known
bad GCC versions?
In
Signed-off-by: Lijun Pan lijun@freescale.com
---
arch/powerpc/include/asm/reg_fsl_emb.h |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h
b/arch/powerpc/include/asm/reg_fsl_emb.h
index 77bb71c..1cf8ab0 100644
---
There are 6 counters in e6500 core instead of 4 in e500 core.
Signed-off-by: Lijun Pan lijun@freescale.com
---
arch/powerpc/include/asm/reg_fsl_emb.h | 12
arch/powerpc/kernel/cputable.c |2 +-
arch/powerpc/oprofile/op_model_fsl_emb.c | 30
e6500 core performance monitors has the following features:
- 6 performance monitor counters
- 512 events supported
- no threshold events
e6500 PMU has more specific events (Data L1 cache misses, Instruction L1
cache misses, etc ) than e500 PMU (which only had Data L1 cache reloads,
etc). Where
On Tue, Apr 30, 2013 at 10:04:32PM -0700, Eric Dumazet wrote:
These kind of errors are pretty hard to find, its a pity to spend time
on them.
Well, yes. From the first comment in gcc PR52080. For the following
testcase we generate a 8 byte RMW cycle on IA64 which causes locking
problems in
Make sure that current-thread.reg exists before we deference it in
flush_hash_page.
Signed-off-by: Michael Neuling mi...@neuling.org
Reported-by: John J Miller mille...@us.ibm.com
Cc: sta...@vger.kernel.org
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index
Hi Kumar,
Could you apply these patches?
Thanks.
-Original Message-
From: Wang Dongsheng-B40534
Sent: Tuesday, April 23, 2013 6:10 PM
To: ga...@kernel.crashing.org
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421
Subject: RE: [PATCH v3 1/4] powerpc/mpic: add irq_set_wake
-Original Message-
From: Wood Scott-B07421
Sent: Friday, May 03, 2013 1:04 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-
B07421; seg...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH 2/2 V8]
On Mon, Apr 29, 2013 at 01:21:42AM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
THP code does PTE page allocation along with large page request and deposit
them
for later use. This is to ensure that we won't have any failures when we split
hugepages
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, May 02, 2013 11:50 PM
To: Sethi Varun-B16395
Cc: Wood Scott-B07421; Yoder Stuart-B08248; ga...@kernel.crashing.org;
linuxppc-dev@lists.ozlabs.org
Subject: Re: pci overmapping
On 05/02/2013 01:09:53 PM, Sethi
On Mon, Apr 29, 2013 at 01:21:46AM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Replace find_linux_pte with find_linux_pte_or_hugepte and explicitly
document why we don't need to handle transparent hugepages at callsites.
Signed-off-by: Aneesh Kumar
On Mon, Apr 29, 2013 at 01:21:49AM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We enable only if the we support 16MB page size.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pgtable-ppc64.h | 3 +--
On Mon, Apr 29, 2013 at 01:21:45AM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
What's the difference in meaning between pmd_huge() and pmd_large()?
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/mm/hugetlbpage.c
On Mon, Apr 29, 2013 at 01:21:48AM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
The deposted PTE page in the second half of the PMD table is used to
track the state on hash PTEs. After updating the HPTE, we mark the
coresponding slot in the deposted
On Mon, Apr 29, 2013 at 01:21:47AM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Reviewed-by: David Gibson da...@gibson.dropbear.id.au
--
David Gibson| I'll have my
On Mon, Apr 29, 2013 at 01:21:50AM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Hugepage invalidate involves invalidating multiple hpte entries.
Optimize the operation using H_BULK_REMOVE on lpar platforms.
On native, reduce the number of tlb flush.
On Mon, Apr 29, 2013 at 01:21:51AM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
With THP we set pmd to none, before we do pte_clear. Hence we can't
walk page table to get the pte lock ptr and verify whether it is locked.
THP do take pte lock before
35 matches
Mail list logo
