Aruna Balakrishnaiah ar...@linux.vnet.ibm.com wrote:
Currently the kernel provides the contents of p-series NVRAM only as a
simple stream of bytes via /dev/nvram, which must be interpreted in user
space by the nvram command in the powerpc-utils package. This patch set
exploits the pstore
On Wed, Jun 19, 2013 at 02:11:53PM +0800, Gavin Shan wrote:
On Wed, Jun 19, 2013 at 01:58:06PM +1000, Michael Neuling wrote:
Bunch of whitespace issues here:
% git am ~/Mail/linuxppc/31202
Applying: powerpc/eeh: Move common part to kernel directory
On Tue, Jun 18, 2013 at 04:33:38PM +0800, Gavin Shan wrote:
On PowerNV platform, the EEH event caused by interrupt won't have
binding PE. The patch enables EEH core to handle the special event.
To avoid the current logic we have, The eeh_handle_event() is renamed
to eeh_handle_normal_event(), and
Michael Neuling mi...@neuling.org writes:
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Book3E uses the hugepd at PMD level and don't encode pte directly
at the pmd level. So it will find the lower bits of pmd set
and the
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
Michael Neuling mi...@neuling.org writes:
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Book3E uses the hugepd at PMD level and don't encode pte directly
at the
Hi Michael,
On Wednesday 19 June 2013 11:45 AM, Michael Neuling wrote:
Aruna Balakrishnaiah ar...@linux.vnet.ibm.com wrote:
Currently the kernel provides the contents of p-series NVRAM only as a
simple stream of bytes via /dev/nvram, which must be interpreted in user
space by the nvram command
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Book3E uses the hugepd at PMD level and don't encode pte directly
at the pmd level. So it will find the lower bits of pmd set
and the pmd_bad check throws error. Infact the current code
will never take the free_hugepd_range call at all
Aruna Balakrishnaiah ar...@linux.vnet.ibm.com wrote:
Hi Michael,
On Wednesday 19 June 2013 11:45 AM, Michael Neuling wrote:
Aruna Balakrishnaiah ar...@linux.vnet.ibm.com wrote:
Currently the kernel provides the contents of p-series NVRAM only as a
simple stream of bytes via /dev/nvram,
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We can find pte that are splitting while walking page tables. Return
None pte in that case.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_book3s_64.h | 51 ++--
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
When we collapse normal pages to hugepage, we first clear the pmd, then
invalidate all
the PTE entries. The assumption here is that any low level page fault will see
pmd as
none and take the slow path that will wait on mmap_sem. But we
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
When we collapse normal pages to hugepage, we first clear the pmd, then
invalidate all
the PTE entries. The assumption here is that any low level page fault will
see pmd as
Michael Neuling mi...@neuling.org writes:
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
When we collapse normal pages to hugepage, we first clear the pmd, then
invalidate all
the PTE entries. The assumption here is that any
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We can find pte that are splitting while walking page tables. Return
None pte in that case.
Can you expand on this more please. There are a lot of details below
like removing a
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
Michael Neuling mi...@neuling.org writes:
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
When we collapse normal pages to hugepage, we first clear the pmd, then
δΊ 2013/6/18 16:33, Gavin Shan ει:
There're several types of PEs can be supported for now: PHB, Bus
and Device dependent PE. For PCI bus dependent PE, tracing the
corresponding PCI bus from PE (struct eeh_pe) would make the code
more efficient. The patch also enables the retrieval of PCI bus
On Tue, Jun 18, 2013 at 04:33:25PM +0800, Gavin Shan wrote:
The patch moves the common part of EEH core into arch/powerpc/kernel
directory so that we needn't PPC_PSERIES while compiling POWERNV
platform:
* Move the EEH common part into arch/powerpc/kernel
* Move the functions for
On Wed, Jun 19, 2013 at 03:21:07PM +0800, Mike Qiu wrote:
.../...
+ /*
+ * For PCI bus sensitive PE, we can reset the parent
+ * bridge in order for hot-reset. However, the PCI
+ * devices including the associated EEH devices might
+
This is based on the codes in head_44x.S. With this patch the kernel
can only boot from 0 with CONFIG_RELOCATABLE enabled. We will add the
support to boot from a non 0 address in the following patches.
Signed-off-by: Kevin Hao haoke...@gmail.com
---
arch/powerpc/Kconfig | 2
This patch series enables the relocatable support for 6xx boards.
With these patches:
* the kernel can boot from any address between 0x1 ~ 0x200
* kdump is workable
* a single kernel image can be used as boot or kdump kernel
Boot test on a mpc8260 board. Also passed the build test
For some platform such as 6xx we need to setup the exception
trampoline for a relocatable kernel even through the CONFIG_CRASH_DUMP
is disabled. So move these functions to a separate file so they can
be used by non dump kernel. This patch doesn't introduce any function
change.
Signed-off-by:
These functions are not just kdump specific. Replace the 'kdump' with
the 'exception' to make them more general.
Signed-off-by: Kevin Hao haoke...@gmail.com
---
arch/powerpc/include/asm/exception_trampoline.h | 20 ++--
arch/powerpc/kernel/exception_trampoline.c | 14
Add the support to boot the kernel from a non 0 address for 6xx.
Setup the exception trampoline if the physical start address is
not 0.
For a kdump kernel, enable the relocatable support implicitly.
Since the memstart_adddr of the kdump is not 0, we definitely
should regard this when setting up
On 19.06.2013, at 06:59, Benjamin Herrenschmidt wrote:
On Wed, 2013-06-19 at 13:05 +0930, Rusty Russell wrote:
symbol_get() won't try to load a module; it'll just fail. This is what
you want, since they must have vfio in the kernel to get a valid fd...
Ok, cool. I suppose what we want
On Wed, 2013-06-19 at 17:14 +1000, Michael Neuling wrote:
This is a bug fix. The details can be found at
Can you make this more obvious in the changelog (as well as making it 80
col). I don't see 'bug' mentioned anywhere. 'Fix' is mentioned
somewhere in the middle of the changelog.
On Tue, Jun 18, 2013 at 04:33:29PM +0800, Gavin Shan wrote:
There're several types of PEs can be supported for now: PHB, Bus
and Device dependent PE. For PCI bus dependent PE, tracing the
corresponding PCI bus from PE (struct eeh_pe) would make the code
more efficient. The patch also enables the
In the Power7 PMU guide:
https://www.power.org/documentation/commonly-used-metrics-for-performance-analysis/
PM_BRU_MPRED is referred to as PM_BR_MPRED.
This patch fix the typo by changing the name of the event in kernel and
documentation accordingly.
Signed-off-by: Runzhen Wang
Michael Neuling mi...@neuling.org writes:
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We can find pte that are splitting while walking page tables. Return
None pte in that case.
Can you expand on this more please. There
Hi,
We have two Freescale PowerPC boards on which we're trying to enable
DEBUG_PAGEALLOC with the hope that we'll see an exception whenever some
code tries to modify a page that's been already freed. To test it, we wrote
this sample code -
===
#define BUF_SIZE4096
void
pagealloc_test(void)
{
Hi,
We have two Freescale PowerPC boards on which we're trying to enable
DEBUG_PAGEALLOC with the hope that we'll see an exception whenever some
code tries to modify a page that's been already freed. To test it, we wrote
this sample code -
===
#define BUF_SIZE4096
void
pagealloc_test(void)
{
On Jun 18, 2013, at 3:14 PM, Scott Wood wrote:
This fixes a regression that causes 83xx to oops on boot if a
non-express PCI bus is present.
The following changes since commit 17858ca65eef148d335ffd4cfc09228a1c1cbfb5:
Merge tag 'please-pull-fixia64' of
On Thu, 2013-06-20 at 00:50 +1000, Benjamin Herrenschmidt wrote:
On Wed, 2013-06-19 at 11:58 +0200, Alexander Graf wrote:
Alex, any objection ?
Which Alex? :)
Heh, mostly Williamson in this specific case but your input is still
welcome :-)
I think validate works, it keeps
Runzhen Wang [runz...@linux.vnet.ibm.com] wrote:
| In the Power7 PMU guide:
|
https://www.power.org/documentation/commonly-used-metrics-for-performance-analysis/
| PM_BRU_MPRED is referred to as PM_BR_MPRED.
|
| This patch fix the typo by changing the name of the event in kernel and
|
Runzhen Wang [runz...@linux.vnet.ibm.com] wrote:
| Power7 supports over 530 different perf events but only a small
| subset of these can be specified by name, for the remaining
| events, we must specify them by their raw code:
|
| perf stat -e r2003c application
|
| This patch makes all
On 06/19/2013 10:06:38 AM, Kumar Gala wrote:
On Jun 18, 2013, at 3:14 PM, Scott Wood wrote:
This fixes a regression that causes 83xx to oops on boot if a
non-express PCI bus is present.
The following changes since commit
17858ca65eef148d335ffd4cfc09228a1c1cbfb5:
Merge tag
You need to mount pstore to access the files.
# mkdir /dev/pstore
# mount -t pstore - /dev/pstore
to unmount
# umount /dev/pstore
References: http://lwn.net/Articles/421297/
Note that /dev/pstore has fallen out of fashion as the mount point ... we now
(since 3.9)
suggest
On 06/19/2013 08:09:44 AM, saikia.partha wrote:
Hi,
We have two Freescale PowerPC boards on which we're trying to enable
DEBUG_PAGEALLOC with the hope that we'll see an exception whenever
some
code tries to modify a page that's been already freed. To test it, we
wrote
this sample code -
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -162,33 +162,40 @@ static inline int hpte_cache_flags_ok(unsigned long
ptel, unsigned long io_type)
* Lock and read a linux PTE. If it's present and writable, atomically
* set dirty
On Wed, 2013-06-19 at 17:15 +0800, Runzhen Wang wrote:
In the Power7 PMU guide:
https://www.power.org/documentation/commonly-used-metrics-for-performance-analysis/
PM_BRU_MPRED is referred to as PM_BR_MPRED.
This patch fix the typo by changing the name of the event in kernel and
On Wed, 2013-06-19 at 17:15 +0800, Runzhen Wang wrote:
Power7 supports over 530 different perf events but only a small
subset of these can be specified by name, for the remaining
events, we must specify them by their raw code:
perf stat -e r2003c application
This patch makes all
Michael Ellerman [mich...@ellerman.id.au] wrote:
| On Wed, 2013-06-19 at 17:15 +0800, Runzhen Wang wrote:
| In the Power7 PMU guide:
|
https://www.power.org/documentation/commonly-used-metrics-for-performance-analysis/
| PM_BRU_MPRED is referred to as PM_BR_MPRED.
|
| This patch fix the
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We can find pte that are splitting while walking page tables. Return
None pte in that case.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_book3s_64.h | 57 ++--
On Thu, 2013-06-20 at 10:11 +0530, Aneesh Kumar K.V wrote:
+ while (1) {
+ old_pte = pte_val(*ptep);
+ /*
+* wait until _PAGE_BUSY is clear then set it
atomically
+*/
+ if (unlikely(old_pte _PAGE_BUSY))
+
On 06/20/2013 01:49 AM, Alex Williamson wrote:
On Thu, 2013-06-20 at 00:50 +1000, Benjamin Herrenschmidt wrote:
On Wed, 2013-06-19 at 11:58 +0200, Alexander Graf wrote:
Alex, any objection ?
Which Alex? :)
Heh, mostly Williamson in this specific case but your input is still
welcome :-)
Initially, the series of patches is built based on 3.10.RC1 and the patchset
doesn't intend to enable EEH functionality for PHB3 for now. Obviously, PHB3
EEH support on PowerNV platform is something to do in future.
The series of patches intends to support EEH for PowerNV platform. The EEH
core
Cleanup on EEH core to remove unnecessary whitespaces.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/pseries/eeh.c| 22 +++---
arch/powerpc/platforms/pseries/eeh_driver.c | 14 +++---
2 files changed, 18 insertions(+), 18
One of the possible cases indicated by P7IOC interrupt is fenced
PHB. For that case, we need fetch the PE corresponding to the PHB
and disable the PHB and all subordinate PCI buses/devices, recover
from the fenced state and eventually enable the whole PHB. We need
one function to fetch the PHB PE
While processing EEH event interrupt from P7IOC, we need function
to retrieve the PE according to the indicated EEH device. The patch
makes function eeh_pe_get() public so that other source files can call
it for that purpose. Also, the patch fixes referring to wrong BDF
(Bus/Device/Function)
The patch adds new EEH operation post_init. It's used to notify
the platform that EEH core has completed the EEH probe. By that,
PowerNV platform starts to use the services supplied by EEH
functionality.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/eeh.h |
For EEH on PowerNV platform, we will do EEH probe based on the
real PCI devices. The PCI devices are available after PCI probe.
So we have to call eeh_init() explicitly on PowerNV platform
after PCI probe. The patch also does EEH probe for PowerNV platform
in eeh_init().
Signed-off-by: Gavin Shan
There're several types of PEs can be supported for now: PHB, Bus
and Device dependent PE. For PCI bus dependent PE, tracing the
corresponding PCI bus from PE (struct eeh_pe) would make the code
more efficient. The patch also enables the retrieval of PCI bus based
on the PCI bus dependent PE.
We possiblly have multiple kthreads running for multiple EEH errors
(events) and use one spinlock to make the process of handling those
EEH events serialized. That's unnecessary and the patch creates only
one kthread, which is started during EEH core initialization time in
eeh_init(). A new
We shouldn't check that the returned PE status is exactly equal to
(EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE) but instead only check
that they are both set.
[benh: changelog]
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/eeh.c |3 ++-
1 files changed, 2
While doing EEH recovery, the PCI devices of the problematic PE
should be removed and then added to the system again. During the
so-called hotplug event, the PCI devices of the problematic PE
will be probed through early/late phase. We would delay EEH probe
on late point for PowerNV platform since
On PowerNV platform, the EEH event caused by interrupt won't have
binding PE. The patch enables EEH core to handle the special event.
To avoid the current logic we have, The eeh_handle_event() is renamed
to eeh_handle_normal_event(), and the eeh_handle_special_event() is
introduced. The function
We're not expecting that one specific PE got frozen for over 5
times in last hour. Otherwise, the PE will be removed from the
system upon newly coming EEH errors. The patch introduces time
stamp to trace the first error on specific PE in last hour and
function to update that accordingly. Besides,
On PowerNV platform, we might run into the situation where subsequent
events are duplicated events of former one, which is being processed.
For the case, we need the function implemented by the patch to purge
EEH events accordingly.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
The patch adds the backend to enable or disable EEH functionality
for the specified PE. The backend is also used to enable MMIO or
DMA path for the problematic PE. It's notable that all PEs on
PowerNV platform support EEH functionality by default, and we
disallow to disable EEH for the specific
The patch adds I/O chip backend to retrieve the state for the
indicated PE. While the PE state is temperarily unavailable,
the upper layer (powernv platform) should return default delay
(1 second).
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-ioda.c
The patch adds the I/O chip backend to do PE reset. For now, we
focus on PCI bus dependent PE. If PHB PE has been put into error
state, the PHB will take complete reset. Besides, the root bridge
will take fundamental or hot reset accordingly if the indicated
PE locates at the toppest of PCI
The patch synchronizes OPAL APIs between kernel and firmware. Also,
we starts to replace opal_pci_get_phb_diag_data() with the similar
opal_pci_get_phb_diag_data2() and the former OPAL API would return
OPAL_UNSUPPORTED from now on.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
The patch adds EEH backends for PowerNV platform. It's notable that
part of those EEH backends call to the I/O chip dependent backends.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/Makefile |2 +-
arch/powerpc/platforms/powernv/eeh-powernv.c |
The patch enables EEH check and let EEH core to process the EEH
errors for PowerNV platform while accessing config space. Originally,
the implementation already had mechanism to check EEH errors and
tried to recover from them. However, we never let EEH core to handle
the EEH errors.
The patch initializes EEH for PowerNV platform. Because the OPAL
APIs requires HUB ID, we need trace that through struct pnv_phb.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 16 +---
This patch implements a notifier to receive a notification on OPAL
event mask changes. The notifier is only called as a result of an OPAL
interrupt, which will happen upon reception of FSP messages or PCI errors.
Any event mask change detected as a result of opal_poll_events() will not
result in a
It's meaningless to handle frozen PE if we already had fenced PHB.
The patch intends to check the PHB state before checking PE. If the
PHB has been put into fenced state, we need take care of that firstly.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/eeh.c | 60
While we're restarting or powering off the system, we needn't
the OPAL notifier any more. So just to disable that.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/setup.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git
The patch creates one debugfs directory (powerpc/PCI) for
each PHB so that we can hook EEH error injection debugfs entry
there in proceeding patch.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 22 ++
The patch creates debugfs entries (powerpc/PCI/err_injct) for
injecting EEH errors for testing purpose.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 31 +
1 files changed, 31 insertions(+), 0 deletions(-)
The patch registers OPAL event notifier and process the PCI errors
from firmware. If we have pending PCI errors, special EEH event
(without binding PE) will be sent to EEH core for processing.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-ioda.c |
An EEH event is created and queued to the event queue for each
ingress EEH error. When there're mutiple EEH errors, we need serialize
the process to keep consistent PE state (flags). The spinlock
confirm_error_lock was introduced for the purpose. We'll inject
EEH event upon error reporting
For EEH on PowerNV platform, the overall architecture is different
from that on pSeries platform. In order to support multiple I/O chips
in future, we split EEH to 3 layers for PowerNV platform: EEH core,
platform layer, I/O layer. It would give EEH implementation on PowerNV
platform much more
The post initialization (struct eeh_ops::post_init) is called after
the EEH probe is done. On the other hand, the EEH core post
initialization is designed to call platform and then I/O chip backend
on PowerNV platform.
The patch adds the backend for I/O chip to notify the platform
that the
The patch implements the backend for EEH core to retrieve next
EEH error to handle. For the informational errors, we won't bother
the EEH core. Otherwise, the EEH should take appropriate actions
depending on the return value:
0 - No further errors detected
1 - Frozen PE
2
The patch adds backends to retrieve error log and configure p2p
bridges for the indicated PE.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 57 -
1 files changed, 55 insertions(+), 2 deletions(-)
diff --git
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