On Fri, Aug 16, 2013 at 12:43:31PM +0800, Nicolin Chen wrote:
Hi Tomasz,
Thank you for the comments. I'll revise them in v6.
And below is my reply for you comments.
On Thu, Aug 15, 2013 at 02:18:22PM +0200, Tomasz Figa wrote:
+ - clock-names : Includes the following entries:
Hi,
Please find the patch set that performs the machine check handling inside linux
host. The design is to be able to handle re-entrancy so that we do not clobber
the machine check information during nested machine check interrupt.
The patch 2 introduces separate emergency stack in paca
Hi Sascha,
Thank you for the detailed comments.
On Fri, Aug 16, 2013 at 09:08:18AM +0200, Sascha Hauer wrote:
Which of them the driver should use is configuration and thus normally
should *not* be described in the devicetree. However, there may be no
good way for the driver to know which
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch splits the common exception prolog logic into two parts to
facilitate reuse of existing code in the next patch. The second part will
be reused in the machine check exception routine in the next patch.
Please note that this patch does
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch introduces exclusive emergency stack for machine check exception.
We use emergency stack to handle machine check exception so that we can save
MCE information (srr1, srr0, dar and dsisr) before turning on ME bit and be
ready for
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check routine that saves the MCE
information (srr1, srr0, dar
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch adds the early machine check function pointer in cputable for
CPU specific early machine check handling. The early machine handle routine
will be called in real mode to handle SLB and TLB errors. This patch just
sets up a mechanism
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch introduces flush_tlb operation in cpu_spec structure. This will
help us to invoke appropriate CPU-side flush tlb routine. This patch
adds the foundation to invoke CPU specific flush routine for respective
architectures. Currently this
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
If we get a machine check exception due to SLB or TLB errors, then flush
SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning
on MMU. Otherwise we would run into nested machine checks.
If we get a machine check when we are
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch handles the memory errors on power8. If we get a machine check
exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to
recover.
I do not have access to power8 box, hence this patch haven't been tested
yet.
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Now that we handle machine check in linux, the MCE decoding should also
take place in linux host. This info is crucial to log before we go down
in case we can not handle the machine check errors. This patch decodes
and populates a machine check
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Now that we are ready to handle machine check directly in linux, do not
register with firmware to handle machine check exception.
Signed-off-by: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/opal.c |8
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Add basic error handling in machine check exception handler.
- If MSR_RI isn't set, we can not recover.
- Check if disposition set to OpalMCE_DISPOSITION_RECOVERED.
- Check if address at fault is inside kernel address space, if not then send
From: Wang Dongsheng dongsheng.w...@freescale.com
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is
From: Wang Dongsheng dongsheng.w...@freescale.com
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions
On 16/08/13 05:50, Benjamin Herrenschmidt wrote:
On Thu, 2013-08-15 at 18:09 +0100, Sudeep KarkadaNagesha wrote:
/* Check for ibm,ppc-interrupt-server#s. If it doesn't exist
* fallback to reg property and assume no threads
*/
-
Oh and I
On 16/08/13 05:49, Benjamin Herrenschmidt wrote:
On Thu, 2013-08-15 at 18:09 +0100, Sudeep KarkadaNagesha wrote:
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
Currently different drivers requiring to access cpu device node are
parsing the device tree themselves. Since the ordering
On Fri, Aug 16, 2013 at 04:01:25PM +0800, Nicolin Chen wrote:
Hi Sascha,
Thank you for the detailed comments.
On Fri, Aug 16, 2013 at 09:08:18AM +0200, Sascha Hauer wrote:
Which of them the driver should use is configuration and thus normally
should *not* be described in the
On Friday 16 August 2013 01:34 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch introduces exclusive emergency stack for machine check exception.
We use emergency stack to handle machine check exception so that we can save
MCE information (srr1,
On 08/16/2013 02:29 PM, Madhavan Srinivasan wrote:
On Friday 16 August 2013 01:34 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch introduces exclusive emergency stack for machine check exception.
We use emergency stack to handle machine check
On 15/08/13 18:09, Sudeep KarkadaNagesha wrote:
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
This patch removes the declaration of the function 'of_get_cpu_node'
which is not defined for openrisc. This is in preparation to move
it's definition from PPC to DT common code.
On Fri, Aug 16, 2013 at 10:56:32AM +0200, Sascha Hauer wrote:
tx0-8 OptionalTx clock source for spdif playback.
If absent, will use core clock.
The index from 0 to 8 is identical
to the clock
---
arch/powerpc/kernel/iommu.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index b20ff17..5abf7c3 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -1149,7 +1149,8 @@ static int
In some cases, one device may not associated with any iommu_group.
For example, not enough DMA address space.
For those devices, kernel will crash when try to remove it from an iommu_group.
This patch do the check before remove it.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
Had a talk with Alexey, who suggest me to send this for comments.
On powernv platform, the P7IOC provide limited range of DMA space. For
example, there are only 8 DMA segments on each PHB. When there are more
than 8 PEs, some of PE's tce32_table is not initialized.
In the normal case, 8 PE is
On Fri, Aug 16, 2013 at 05:53:58PM +0800, Nicolin Chen wrote:
On Fri, Aug 16, 2013 at 10:56:32AM +0200, Sascha Hauer wrote:
tx0-8 OptionalTx clock source for spdif playback.
If absent, will use core clock.
The index from 0 to 8
On 08/16/2013 08:08 PM, Wei Yang wrote:
---
arch/powerpc/kernel/iommu.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index b20ff17..5abf7c3 100644
--- a/arch/powerpc/kernel/iommu.c
+++
On Fri, Aug 16, 2013 at 12:11:51PM +0200, Sascha Hauer wrote:
Some clocks are not from CCM and we haven't defined in imx6q-clk.txt,
so in most cases we can't provide a phandle for them, eg: spdif_ext.
I think it's a bit hard to force it to be 'required'. An 'optional'
looks more flexible
On Aug 16, 2013, at 2:23 AM, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions
On Aug 15, 2013, at 11:57 PM, Henry Bausley wrote:
Is there any reason that a Critical Input Interrupt will not work reliably on
a 44x powerpc?
I am using an AMCC now Applied Micro AMCC460EX
and changed
CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
to
On Fri, 2013-08-16 at 09:48 +0100, Sudeep KarkadaNagesha wrote:
Naming is a bit gross. You might want to make it clearer that
we are talking about CPU IDs in the device-tree here.
Any particular preference to the name or just a note is sufficient.
Also unlike PPC, in ARM we don't set
On 16/08/13 13:32, Benjamin Herrenschmidt wrote:
On Fri, 2013-08-16 at 09:48 +0100, Sudeep KarkadaNagesha wrote:
Naming is a bit gross. You might want to make it clearer that
we are talking about CPU IDs in the device-tree here.
Any particular preference to the name or just a note is
Changelog:
v5-v6:
* Sorted out rxtx clk source in DT binding.
* Use devm_() functions.
* Use platform_get_resource() instead.
v4-v5:
* Dropped rx/tx-clksrc-names DT bindings.
* Use standard clock binding instead to pass the clock source list.
* Update the compatible list by using imx35,
Add S/PDIF machine driver for Freescale i.MX series SoC.
Signed-off-by: Nicolin Chen b42...@freescale.com
---
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +
sound/soc/fsl/Kconfig | 11 ++
sound/soc/fsl/Makefile |2 +
This patch add S/PDIF controller driver for Freescale SoC.
Signed-off-by: Nicolin Chen b42...@freescale.com
---
.../devicetree/bindings/sound/fsl,spdif.txt| 56 +
sound/soc/fsl/Kconfig |3 +
sound/soc/fsl/Makefile |2 +
Changes from v1:
- Allocate compression workspace during initialisation as
per Tony's suggestion
- Copy the recent messages from big_oops_buf to psinfo-buf
when compression fails, since the printk buffer
would be fetched for compression calling it again
(De)compression support is provided in pstore in subsequent patches which
needs an additional argument 'compressed' to determine if the data
is compressed or not. This patch will take care of removing (de)compression
in nvram with pstore which was making use of 'hsize' argument in pstore write
as
Pstore will make use of deflate and inflate algorithm to compress and decompress
the data. So when Pstore is enabled select zlib_deflate and zlib_inflate.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
fs/pstore/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git
Addition of new argument 'compressed' in the write call back will
help the backend to know if the data passed from pstore is compressed
or not (In case where compression fails.). If compressed, the backend
can add a tag indicating the data is compressed while writing to
persistent store.
Add compression support to pstore which will help in capturing more data.
Initially, pstore will make a call to kmsg_dump with a bigger buffer
and will pass the size of bigger buffer to kmsg_dump and then compress
the data to registered buffer of registered size.
In case compression fails, pstore
Backends will set the flag 'compressed' after reading the log from
persistent store to indicate the data being returned to pstore is
compressed or not.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
arch/powerpc/platforms/pseries/nvram.c |2 +-
drivers/acpi/apei/erst.c
Based on the flag 'compressed' set or not, pstore will decompress the
data returning a plain text file. If decompression fails for a particular
record it will have the compressed data in the file which can be
decompressed with 'openssl' command line tool.
Signed-off-by: Aruna Balakrishnaiah
In pstore write, set the section type to CPER_SECTION_TYPE_DMESG_COMPR
if the data is compressed. In pstore read, read the section type and
update the 'compressed' flag accordingly.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
drivers/acpi/apei/erst.c | 13 -
1
In pstore write, add character 'C'(compressed) or 'D'(decompressed)
in the header while writing to Ram persistent buffer. In pstore read,
read the header and update the 'compressed' flag accordingly.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
fs/pstore/ram.c | 36
In pstore write, Efi will add a character 'C'(compressed) or
D'(decompressed) in its header while writing to persistent store.
In pstore read, read the header and update the 'compressed' flag
accordingly.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
If data returned from pstore is compressed, nvram's write callback
will add a flag ERR_TYPE_KERNEL_PANIC_GZ indicating the data is compressed
while writing to nvram. If the data read from nvram is compressed, nvram's
read callback will set the flag 'compressed'. The patch adds backward
In case decompression fails, add a .enc.z to indicate the file has
compressed data. This will help user space utilities to figure
out the file contents.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
fs/pstore/inode.c|7 ---
fs/pstore/internal.h |5 +++--
On Fri, 2013-08-16 at 06:02 -0500, Kumar Gala wrote:
On Aug 16, 2013, at 2:23 AM, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
Hi,
This series needs to be prepended with the original series[1][2][3]
Except the first patch in the original series(which is merged into this
as last patch), there is no other change(apart from function signature)
I am posting only this
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
Currently different drivers requiring to access cpu device node are
parsing the device tree themselves. Since the ordering in the DT need
not match the logical cpu ordering, the parsing logic needs to consider
that. However, this has
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
This patch moves the generalized implementation of of_get_cpu_node from
PowerPC to DT core library, thereby adding support for retrieving cpu
node for a given logical cpu index on any architecture.
The CPU subsystem can now use this
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of Nicolin
Chen
Sent: Friday, August 16, 2013 6:27 PM
To: broo...@kernel.org; l...@metafoo.de; p.za...@pengutronix.de;
s.ha...@pengutronix.de
Cc:
On Fri, 2013-08-09 at 16:24 +1000, Stephen Rothwell wrote:
We cannot put the unsetting of config options in the Kconfig file, nor
the integer or string options.
I checked that after this we get the same .config files generated (except
for the addition of the new PPC64_DEFCONFIG* config
On Tue, Aug 6, 2013 at 11:41 PM, Leon Ravich lrav...@gmail.com wrote:
From comparison of pci printout from the two kernel ,
beside the EDAC errors I noticed other strange differences:
In 3.8.13 I got BAR 7 and BAR 8:
[ 39.017749] pci :00:00.0: BAR 8: assigned [mem 0xc000-0xdfff]
On Fri, 2013-08-16 at 18:39 +0100, Sudeep KarkadaNagesha wrote:
+static bool __of_find_n_match_cpu_property(struct device_node *cpun,
+ const char *prop_name, int cpu, unsigned int
*thread)
+{
+ const __be32 *cell;
+ int ac, prop_len, tid;
+ u64 hwid;
Needs testing with erst backend, efivars and persistent ram.
Tested against ERST - works fine for me now.
Need to stare at the code to see if there are any more bits that could be
cleaned up.
Thanks for addressing my issues from v1
-Tony
___
On Fri, 2013-08-16 at 18:39 +0100, Sudeep KarkadaNagesha wrote:
+#ifdef CONFIG_PPC
+ /* Check for historical ibm,ppc-interrupt-server#s property
+* for thread ids on PowerPC. If it doesn't exist fallback to
+* standard reg property.
+
On 08/15/2013 03:24 AM, Shawn Guo wrote:
On Thu, Aug 15, 2013 at 10:18:23AM +0800, Nicolin Chen wrote:
Hi Stephen,
On Wed, Aug 14, 2013 at 09:47:19AM -0600, Stephen Warren wrote:
If the clock source name list is different, then it needs a different
compatible value, so that each compatible
Greetings.
I've been experiencing occasional lockups at reboot for a few weeks,
but only once every 10-20 boots. A good reboot looks like this:
[47529.721640] lm77 0-0048: shutdown
[47529.725160] rtc-m41t80 0-0068: shutdown
[47529.729169] i2c i2c-0: shutdown
[47529.732534] fsl-ehci
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of Anthony
Foiani
Sent: Saturday, August 17, 2013 7:10 AM
To: linuxppc-dev@lists.ozlabs.org
Subject: MPC8315 reboot failure, lockdep splat possibly related?
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