On Wednesday 04 September 2013 07:14 AM, Seiji Aguchi wrote:
Aruna,
Sorry for the late response.
Seiji,
Could you let us know the efivars buffer size with which the pstore is
registered when
the failure occurred.
I looked into the issue today.
I added some debug message just before
On 09/03/2013 10:52 PM, Daniel Borkmann wrote:
On 09/03/2013 09:58 PM, Vladimir Murzin wrote:
[...]
Do you have a test case/suite by any chance ?
Ben.
Hi Ben!
Thanks for your feedback.
This patch is only compile tested. I have no real hardware, but I'll
probably bring up qemu ppc64 till
Use __free_reserved_page() to simplify the code in the others.
Signed-off-by: Xishi Qiu qiuxi...@huawei.com
---
drivers/video/acornfb.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c
index 6488a73..4ef302a 100644
---
Use __free_reserved_page() to simplify the code in arch.
It used split_page() in
consistent_alloc()/__dma_alloc_coherent()/dma_alloc_coherent(),
so page-_count == 1, and we can free it safely.
__free_reserved_page()
ClearPageReserved()
init_page_count() // it won't change the
The reason behind compression failure is the size of big_oops_buf which is too
big for efivars case. I will do some experiments with different kind of texts
for buffer size 1024 to check if 100/53 suits for all the cases.
...
Yes this can be changed to zlib_inflateInit2().
Original patch
On Mon, 2013-09-02 at 18:11 +0800, Xie Xiaobo wrote:
+soc {
+ usb@22000 {
+ phy_type = ulpi;
+ };
+
+ mdio@24000 {
+ phy0: ethernet-phy@2 {
+ interrupt-parent = mpic;
+ interrupts = 1 1;
+ reg
On Mon, 2013-09-02 at 18:11 +0800, Xie Xiaobo wrote:
Define two QE init functions in common file, and avoid
the same codes being duplicated in board files.
Signed-off-by: Xie Xiaobo x@freescale.com
---
V3 - V2: Nochange
arch/powerpc/platforms/85xx/common.c | 47
But let's make sure that efivars, erst,
etc. are all happy with the changes we make before I ask Linus to pull another
pstore piece.
I will test efivars when Aruna posts the bugfix patches.
Seiji
-Original Message-
From: Luck, Tony [mailto:tony.l...@intel.com]
Sent: Wednesday,
Hi,
Idle routines on pseries were rearranged so that cpuidle can do
an optimized idle state selection. However, until cpuidle takes
over during boot, the idle loop spins for a short while. This
actually affected bootup time since spinning idle sibling threads
slows down master cpu that executes
Hi S.Saravanan,
You'll have two drivers;
* The root-complex.
This is a standard PCIe driver, so you'll just follow convention
there
* The end-point driver.
This driver needs to use the PCIe bus, but its not responsible
for the PCIe bus in the way a root-complex is. The driver
On Sep 3, 2013, at 2:35 AM, Yijing Wang wrote:
Use pci_is_pcie() to simplify code.
Signed-off-by: Yijing Wang wangyij...@huawei.com
Cc: Gavin Shan sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc:
Hi All,
On Fri, Aug 30, 2013 at 11:36 PM, David Hawkins d...@ovro.caltech.eduwrote:
Hi S.Saravanan,
I successfully mapped the Programmable Interrupt Controller registers
in the EP to the PCI space. Thus now I can write the shared message
interrupt registers in the EP from the RC over
From: Chen Yu chen.y...@zte.com.cn
In current 85xx smp kexec implementation,master cpu reset slave cpus by
mpic_reset_core,
before jump to second kernel.In order to wake slave cpus up in second
kernel,we debug
this patch on p2041rdb.
What problem causes that you do the modification? I
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used.
The sub-nodes are also reorganized according to right I2C topology.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V2 change log:
Reorganized the sub-nodes under I2C multiplexer to represent right topology.
-Original Message-
From: Jia Hongtao-B38951
Sent: Monday, July 01, 2013 5:36 PM
To: Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Subject: RE: [V2,2/2] powerpc/85xx: workaround for chips with MSI
hardware errata
-Original Message-
From:
On Tue, 2013-09-03 at 13:53 +0300, Gleb Natapov wrote:
Or supporting all IOMMU links (and leaving emulated stuff as is) in on
device is the last thing I have to do and then you'll ack the patch?
I am concerned more about API here. Internal implementation details I
leave to powerpc experts
Add support for the Motorola/Emerson MVME5100 Single Board Computer.
The MVME5100 is a 6U form factor VME64 computer with:
- A single MPC7410 or MPC750 CPU
- A HAWK Processor Host Bridge (CPU to PCI) and
MultiProcessor Interrupt Controller (MPIC)
- Up to 500Mb
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