From: Wang Dongsheng dongsheng.w...@freescale.com
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is
From: Wang Dongsheng dongsheng.w...@freescale.com
E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Add bit definitions for PWRMGTCR0.
arch/powerpc/include/asm/reg.h | 2 ++
From: Wang Dongsheng dongsheng.w...@freescale.com
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle
Set wait entry
From: Wang Dongsheng dongsheng.w...@freescale.com
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions
On 09/11/2013 04:20 AM, Guenter Roeck wrote:
On Wed, Sep 11, 2013 at 08:02:49AM +1000, Benjamin Herrenschmidt wrote:
On Mon, 2013-09-09 at 16:55 -0700, Asai Thambi S P wrote:
On 09/08/2013 5:28 PM, Guenter Roeck wrote:
Hi all,
Guenter, Ben,
Sorry for the inconvenience. I never realized my
On 09/10/2013 10:08 PM, Vladimir Murzin wrote:
While cross-building for PPC64 I've got
Vladimir,
Below commit ID fixes this issue.
commit 256588fda10f2a712631f8a4e72641a66adebdb8
Author: Guenter Roeck li...@roeck-us.net
Date: Mon Sep 9 18:37:56 2013 -0700
powerpc: Export
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking telecommunications.
T1042 personality is a reduced personality of T1040 without Integrated
Add support for T104x board in board file t104x_qds.c, It is common for
both T1040 and T1042 as they share same QDS board.
T1040QDS board Overview
---
- SERDES Connections, 8 lanes supporting:
— PCI Express: supporting Gen 1 and Gen 2;
— SGMII
— QSGMII
T1040 supports both 32 64 bit kernel.
so enable T1040QDS by default in the config files.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
arch/powerpc/configs/corenet32_smp_defconfig |1 +
From: Tang Yuantian yuantian.t...@freescale.com
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
v4:
- add binding document
- update
On 09/11/2013 03:33 AM, Benjamin Herrenschmidt wrote:
On Mon, 2013-09-09 at 18:37 -0700, Guenter Roeck wrote:
powerpc allmodconfig build fails with:
ERROR: .cpu_to_chip_id [drivers/block/mtip32xx/mtip32xx.ko] undefined!
The problem was introduced with commit 15863ff3b (powerpc: Make chip-id
Hello guys,
would like to ask if there is a proper possibility on PPC to
set default date (basically the year). The board has no RTC chip,
and I would need instead of 1970 another year.
For some reason does e.g:
--- a/linux/arch/powerpc/kernel/time.c
+++ b/linux/arch/powerpc/kernel/time.c
@@
When backends (ex: efivars) have smaller registered buffers, the big_oops_buf
is quite too big for them as number of repeated occurences in the text captured
will be less. Patch takes care of adjusting the buffer size based on the
registered buffer size. cmpr values has been arrived after doing
Since zlib_deflateInit2() is used for specifying window bit during compression,
zlib_inflateInit2() is appropriate for decompression.
Reported-by: Seiji Aguchi seiji.agu...@hds.com
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
fs/pstore/platform.c |2 +-
1 file changed, 1
On Sep 10, 2013, at 10:49 PM, Zhao Qiang wrote:
Since P1010RDB-PA and P1010RDB-PB boards use different external PHY
interrupt signals.
And actually the PHY interrupt is not used effectively with
corresponding interrupt handler.
So we can remove the interrupts node without side-effect to
Currently DIVWU stands for *signed* divw opcode:
7d 2a 4b 96 divwu r9,r10,r9
7d 2a 4b d6 divwr9,r10,r9
Use the *unsigned* divw opcode for DIVWU.
Signed-off-by: Vladimir Murzin murzi...@gmail.com
---
arch/powerpc/include/asm/ppc-opcode.h |2 +-
1 file changed, 1 insertion(+),
On Wed, Sep 11, 2013 at 12:07:45PM +0530, Vasant Hegde wrote:
On 09/10/2013 10:08 PM, Vladimir Murzin wrote:
While cross-building for PPC64 I've got
Vladimir,
Below commit ID fixes this issue.
Great! For whatever reason I thought _GPL is default policy for exported
symbols... but, never
From: Jiang Liu jiang@huawei.com
Commit 9a46ad6d6df3b54 smp: make smp_call_function_many() use logic
similar to smp_call_function_single() has unified the way to handle
single and multiple cross-CPU function calls. Now only one interrupt
is needed for architecture specific code to support
On Wed, 2013-09-11 at 11:15 +1000, Benjamin Herrenschmidt wrote:
On Tue, 2013-09-10 at 18:47 -0500, Scott Wood wrote:
No blank line before }
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=console=ttyS0,9600 ip=dhcp root=/dev/nfs
I take it there's no way to pass a command line in from
On Wed, Sep 04, 2013 at 09:04:04AM +0200, Daniel Borkmann wrote:
On 09/03/2013 10:52 PM, Daniel Borkmann wrote:
On 09/03/2013 09:58 PM, Vladimir Murzin wrote:
[...]
Do you have a test case/suite by any chance ?
Ben.
Hi Ben!
Thanks for your feedback.
This patch is only
The commit e0908085fc2391c85b85fb814ae1df377c8e0dcb is not needed anymore.
The issue was because dcbst wrongly sets the store bit when causing a DTLB
error, but this is now fixed by commit 0a2ab51ffb8dfdf51402dcfb446629648c96bc78
which handles the buggy dcbx instructions on data page faults on the
Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three
8Mbytes pages. But the setting of the MD_CTR was missing so as the index is
decremented every DTLB update, the pinning of the third 8Mbytes page was
overwriting the DTLB entry for IMMR.
Signed-off-by: Christophe Leroy
The commit e0908085fc2391c85b85fb814ae1df377c8e0dcb is not needed anymore.
The issue was because dcbst wrongly sets the store bit when causing a DTLB
error, but this is now fixed by commit 0a2ab51ffb8dfdf51402dcfb446629648c96bc78
which handles the buggy dcbx instructions on data page faults on the
On Wed, 2013-09-11 at 08:21 +0530, Preeti U Murthy wrote:
arch/powerpc/platforms/ps3/smp.c|2 +-
The PS3 part is trivial and looks OK.
Acked-by: Geoff Levand ge...@infradead.org
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
On Wed, 2013-09-11 at 08:21 +0530, Preeti U Murthy wrote:
arch/powerpc/platforms/ps3/smp.c|2 +-
The PS3 part is trivial and looks OK.
Acked-by: Geoff Levand ge...@infradead.org
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
Hi,
no matter anymore - got it:
--- a/linux/arch/powerpc/kernel/time.c
+++ b/linux/arch/powerpc/kernel/time.c
@@ -832,7 +832,7 @@ static void __read_persistent_clock(struct timespec *ts)
}
}
if (!ppc_md.get_rtc_time) {
- ts-tv_sec = 0;
+
- big_oops_buf_sz = (psinfo-bufsize * 100) / 45;
+ big_oops_buf_sz = (psinfo-bufsize * 100) / cmpr;
Tested on an ERST backed system. Seems to be working (we save a little less
information
per ERST record than before this change (uncompressed size goes down from
~17500 to
~16400
+ /* buffer range for efivars */
+ case 1000 ... 2000:
+ cmpr = 56;
+ break;
Seiji: let me know how the efivars tests go.
efivars works fine.
Uncompressed size about 1800 bytes. It matches the value of cmpr, 56.
Please feel free to add my Tested-by to all
On 09/11/2013 09:37 PM, Jiang Liu wrote:
From: Jiang Liu jiang@huawei.com
Commit 9a46ad6d6df3b54 smp: make smp_call_function_many() use logic
similar to smp_call_function_single() has unified the way to handle
single and multiple cross-CPU function calls. Now only one interrupt
is
On Wed, 2013-09-11 at 18:44 +0200, Christophe Leroy wrote:
Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three
8Mbytes pages. But the setting of the MD_CTR was missing so as the index is
decremented every DTLB update, the pinning of the third 8Mbytes page was
overwriting
On Wed, 2013-09-11 at 13:56 +0800, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec
On Wed, 2013-09-11 at 13:56 +0800, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
Enable/Disable interface:
0, disable. 1, enable.
On Wed, 2013-09-11 at 12:28 +0530, Prabhakar Kushwaha wrote:
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking
telecommunications.
Commit 9837b43c5f3514e5d28f65f1513f4dc6759d2810 (powerpc/85xx: enable
coreint for all the 64bit boards) removed the ifdef that avoided
coreint on 64-bit, but it missed b4_qds.c.
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Kevin Hao haoke...@gmail.com
Cc: Shaveta Leekha
On Wed, 2013-09-11 at 12:28 +0530, Prabhakar Kushwaha wrote:
Add support for T104x board in board file t104x_qds.c, It is common for
both T1040 and T1042 as they share same QDS board.
T1040QDS board Overview
---
- SERDES Connections, 8 lanes supporting:
— PCI
On Wed, 2013-09-11 at 17:36 -0500, Scott Wood wrote:
I wonder why we don't start from entry 31 so we can actually make use of
that autodecrement. What will happen when we load the first normal TLB
entry later on? I don't see any setting of SPRN_MD_CTR after this code,
so won't it overwrite
Vladimir Murzin murzi...@gmail.com wrote:
Currently DIVWU stands for *signed* divw opcode:
7d 2a 4b 96 divwu r9,r10,r9
7d 2a 4b d6 divwr9,r10,r9
Use the *unsigned* divw opcode for DIVWU.
This looks like it's in only used in the BPF JIT code.
Matt, any chance you an ACK/NACK
On 12 Sep 2013, at 10:02, Michael Neuling mi...@neuling.org wrote:
Vladimir Murzin murzi...@gmail.com wrote:
Currently DIVWU stands for *signed* divw opcode:
7d 2a 4b 96divwu r9,r10,r9
7d 2a 4b d6divwr9,r10,r9
Use the *unsigned* divw opcode for DIVWU.
This looks like
On Wed, 2013-09-11 at 14:57 +0800, yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang
On Tue, 2013-09-10 at 21:07 -0500, Hu Mingkai-B21284 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, September 11, 2013 7:33 AM
To: Hu Mingkai-B21284
Cc: linuxppc-...@ozlabs.org
Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions
Hi Ben, Vladimir,
*dusts off very thick PPC cobwebs* Sorry for the delay as I'm travelling,
didn't get to this until now.
On 02/09/2013, at 9:45 PM, Benjamin Herrenschmidt wrote:
On Mon, 2013-09-02 at 19:48 +0200, Vladimir Murzin wrote:
Ping
On Wed, Aug 28, 2013 at 02:49:52AM +0400,
-Original Message-
From: Wood Scott-B07421
Sent: 2013年9月12日 星期四 9:10
To: Tang Yuantian-B29983
Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
devicet...@vger.kernel.org; Li Yang-Leo-R58472
Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree
nodes
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, September 12, 2013 6:43 AM
To: Wang Dongsheng-B40534
Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v3 2/4] powerpc/85xx: add hardware automatically
enter altivec idle state
On Wed,
On Thu, Sep 12, 2013 at 10:28:03AM +0930, Matt Evans wrote:
On 12 Sep 2013, at 10:02, Michael Neuling mi...@neuling.org wrote:
Vladimir Murzin murzi...@gmail.com wrote:
Currently DIVWU stands for *signed* divw opcode:
7d 2a 4b 96divwu r9,r10,r9
7d 2a 4b d6divw
On Thu, Sep 12, 2013 at 02:18:37AM +0100, Matt Evans wrote:
Hi Ben, Vladimir,
*dusts off very thick PPC cobwebs* Sorry for the delay as I'm travelling,
didn't get to this until now.
On 02/09/2013, at 9:45 PM, Benjamin Herrenschmidt wrote:
On Mon, 2013-09-02 at 19:48 +0200, Vladimir
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, September 12, 2013 7:04 AM
To: Wang Dongsheng-B40534
Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and
altivec idle
On Wed, 2013-09-11 at
Le 12/09/2013 02:15, Benjamin Herrenschmidt a écrit :
On Wed, 2013-09-11 at 17:36 -0500, Scott Wood wrote:
I wonder why we don't start from entry 31 so we can actually make use of
that autodecrement. What will happen when we load the first normal TLB
entry later on? I don't see any setting
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