Re: [PATCH] powerpc, perf: Configure BHRB filter before enabling PMU interrupts

2013-10-14 Thread Michael Ellerman
On Fri, Oct 11, 2013 at 10:02:28AM +0530, Anshuman Khandual wrote: On 10/11/2013 07:41 AM, Michael Ellerman wrote: On Thu, Oct 10, 2013 at 02:20:22PM +0530, Anshuman Khandual wrote: Even I think this is not right. Instruction sampling should have been enabled before we enable PMU

[PATCH 1/2] powerpc/p1010rdb:add P1010RDB-PB platform support

2013-10-14 Thread Zhao Qiang
The P1010RDB-PB is similar to P1010RDB(P1010RDB-PA). So, P1010RDB-PB use the same platform file as P1010RDB. Then Add support for P1010RDB-PB platform. Signed-off-by: Zhao Qiang b45...@freescale.com --- arch/powerpc/platforms/85xx/p1010rdb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[PATCH v4 2/2] powerpc/p1010rdb:update dts to adapt to both old and new p1010rdb

2013-10-14 Thread Zhao Qiang
P1010rdb-pa and p1010rdb-pb have different phy interrupts. So update dts to adapt to both p1010rdb-pa and p1010rdb-pb. Signed-off-by: Shengzhou Liu shengzhou@freescale.com Signed-off-by: Zhao Qiang b45...@freescale.com --- Changes for v2 - Take p1010rdb_36b.dts into account Changes

[PATCH] powerpc/kexec: kexec_sequence() is in misc_64.S

2013-10-14 Thread Geert Uytterhoeven
Correct reference to the location of the kexec_sequence() assembly helper. There never was a kexec_stub.S in mainline. Signed-off-by: Geert Uytterhoeven ge...@linux-m68k.org --- arch/powerpc/kernel/machine_kexec_64.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH] powerpc: Add VMX optimised xor for RAID5

2013-10-14 Thread Anton Blanchard
Add a VMX optimised xor, used primarily for RAID5. On a POWER7 blade this is a decent win: 32regs: 17932.800 MB/sec altivec : 19724.800 MB/sec The bigger gain is when the same test is run in SMT4 mode, as it would if there was a lot of work going on: 8regs : 8377.600 MB/sec

RE: [PATCH 2/7] iommu: add api to get iommu_domain of a device

2013-10-14 Thread Sethi Varun-B16395
-Original Message- From: Alex Williamson [mailto:alex.william...@redhat.com] Sent: Friday, October 11, 2013 2:12 AM To: Sethi Varun-B16395 Cc: Bhushan Bharat-R65777; ag...@suse.de; Wood Scott-B07421; linux- p...@vger.kernel.org; ga...@kernel.crashing.org; linux-

Re: [PATCH 2/7] iommu: add api to get iommu_domain of a device

2013-10-14 Thread Alex Williamson
On Mon, 2013-10-14 at 12:58 +, Sethi Varun-B16395 wrote: -Original Message- From: Alex Williamson [mailto:alex.william...@redhat.com] Sent: Friday, October 11, 2013 2:12 AM To: Sethi Varun-B16395 Cc: Bhushan Bharat-R65777; ag...@suse.de; Wood Scott-B07421; linux-

How to setup linux to the vxworks system?

2013-10-14 Thread Alexey Karpov
Hello! I have a xerox print controller (an serial number HFT), used in xerox 8825, 8830 and 510 wide format print systems, and wish to use it as a little home server. It based on powerpc G4 (MPC7410) and equipped with 2 PCI slots, 2 DIMM slots, intel-based integrated network card and 2

Re: [PATCH] powerpc/qe_lib: Share the qe_lib for the others architecture

2013-10-14 Thread Scott Wood
On Mon, 2013-10-14 at 19:37 +0800, Xie Xiaobo wrote: The QUICC Engine (QE) is a communications coprocessors on Freescale embedded processors. The QE had been applied in PowerPC architecture previously, and it will be applied in ARM architecture too. So move the qe_lib from arch/powerpc to

Re: [PATCH] powerpc/qe_lib: Share the qe_lib for the others architecture

2013-10-14 Thread Kumar Gala
On Oct 14, 2013, at 6:37 AM, Xie Xiaobo wrote: The QUICC Engine (QE) is a communications coprocessors on Freescale embedded processors. The QE had been applied in PowerPC architecture previously, and it will be applied in ARM architecture too. So move the qe_lib from arch/powerpc to driver/

Re: [PATCH] powerpc/qe_lib: Share the qe_lib for the others architecture

2013-10-14 Thread Kumar Gala
On Oct 14, 2013, at 2:26 PM, Kumar Gala wrote: On Oct 14, 2013, at 6:37 AM, Xie Xiaobo wrote: The QUICC Engine (QE) is a communications coprocessors on Freescale embedded processors. The QE had been applied in PowerPC architecture previously, and it will be applied in ARM architecture

Re: [PATCH] powerpc/qe_lib: Share the qe_lib for the others architecture

2013-10-14 Thread Kumar Gala
On Oct 14, 2013, at 2:26 PM, Kumar Gala wrote: On Oct 14, 2013, at 6:37 AM, Xie Xiaobo wrote: The QUICC Engine (QE) is a communications coprocessors on Freescale embedded processors. The QE had been applied in PowerPC architecture previously, and it will be applied in ARM architecture

Re: [PATCH] powerpc/qe_lib: Share the qe_lib for the others architecture

2013-10-14 Thread Greg Kroah-Hartman
On Mon, Oct 14, 2013 at 02:40:44PM -0500, Kumar Gala wrote: On Oct 14, 2013, at 2:26 PM, Kumar Gala wrote: On Oct 14, 2013, at 6:37 AM, Xie Xiaobo wrote: The QUICC Engine (QE) is a communications coprocessors on Freescale embedded processors. The QE had been applied in PowerPC

Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree

2013-10-14 Thread Scott Wood
On Fri, 2013-10-11 at 21:52 -0500, Tang Yuantian-B29983 wrote: Thanks for your review. -Original Message- From: Wood Scott-B07421 Sent: 2013年10月12日 星期六 3:07 To: Mark Rutland Cc: Tang Yuantian-B29983; devicet...@vger.kernel.org; linuxppc- d...@lists.ozlabs.org; Li

Re: [PATCH 1/3] iommu/fsl: Factor out PCI specific code.

2013-10-14 Thread Bjorn Helgaas
On Sun, Oct 13, 2013 at 02:02:32AM +0530, Varun Sethi wrote: Factor out PCI specific code in the PAMU driver. Signed-off-by: Varun Sethi varun.se...@freescale.com --- drivers/iommu/fsl_pamu_domain.c | 81 +++ 1 file changed, 40 insertions(+), 41

[PATCH] powerpc: Use 32 bit loads and stores when operating on condition register values

2013-10-14 Thread Anton Blanchard
The condition register (CR) is a 32 bit quantity so we should use 32 bit loads and stores. Signed-off-by: Anton Blanchard an...@samba.org --- diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S index cd809ea..432cf54 100644 --- a/arch/powerpc/kernel/tm.S +++

Re: [PATCH] powerpc: Use 32 bit loads and stores when operating on condition register values

2013-10-14 Thread Paul Mackerras
On Tue, Oct 15, 2013 at 02:36:31PM +1100, Anton Blanchard wrote: The condition register (CR) is a 32 bit quantity so we should use 32 bit loads and stores. Does this make any practical difference or fix any bugs, or is this just for aesthetics? Paul.

Re: [PATCH] powerpc: Use 32 bit loads and stores when operating on condition register values

2013-10-14 Thread Anton Blanchard
Hi Paul, Does this make any practical difference or fix any bugs, or is this just for aesthetics? There is talk of the other 32 bits of that word being used for a stack canary in a future ABI revision. So right now it is just cosmetic, but it could be important in the future. I guess it