On Mon, 2014-05-05 at 12:09 +1000, Gavin Shan wrote:
Commit 7f52a526f (powerpc/eeh: Allow to disable EEH) caused
following build error with celleb_defconfig as being catched
by Mikey on linux-next.
arch/powerpc/kernel/eeh.c: In function 'eeh_init_proc':
arch/powerpc/kernel/eeh.c:1173:37:
This patch series adds five new ELF core note sections which can be
used with existing ptrace request PTRACE_GETREGSET/SETREGSET for accessing
various transactional memory and miscellaneous register sets on PowerPC
platform. Please find a test program exploiting these new ELF core note
This patch adds four new note sections for transactional memory
and one note section for some miscellaneous registers. This addition
of new elf note sections extends the existing elf ABI without affecting
it in any manner.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
This patch enables get and set of transactional memory related register
sets through PTRACE_GETREGSET/PTRACE_SETREGSET interface by implementing
four new powerpc specific register sets i.e REGSET_TM_SPR, REGSET_TM_CGPR,
REGSET_TM_CFPR, REGSET_CVMX support corresponding to these following new
ELF
This patch enables get and set of miscellaneous registers through ptrace
PTRACE_GETREGSET/PTRACE_SETREGSET interface by implementing new powerpc
specific register set REGSET_MISC support corresponding to the new ELF
core note NT_PPC_MISC added previously in this regard.
Signed-off-by: Anshuman
Generic powerpc branch analysis support added in the code patching
library which will help the subsequent patch on SW based filtering
of branch records in perf.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/code-patching.h | 16 +++
Adding perf record support for new branch stack filter criteria
PERF_SAMPLE_BRANCH_COND.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
Reviewed-by: Andi Kleen a...@linux.intel.com
---
tools/perf/builtin-record.c | 1 +
1 file
This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
This patch enables SW based post processing of BHRB captured branches
to be able to meet more user defined branch filtration criteria in perf
branch stack sampling framework. These changes increase the number of
branch filters and their valid combinations on any powerpc64 server
platform with BHRB
This patchset is the re-spin of the original branch stack
sampling
patchset which introduced new PERF_SAMPLE_BRANCH_COND branch filter. This
patchset
also enables SW based branch filtering support for book3s powerpc platforms
which
have PMU HW backed branch stack sampling
This patch simply changes the name of the variable from 'bhrb_filter' to
'bhrb_hw_filter' in order to add one more variable which will track SW
filters in generic powerpc book3s code which will be implemented in the
subsequent patch. This patch does not change any functionality.
Signed-off-by:
Adding documentation support for conditional branch filter.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
Reviewed-by: Andi Kleen a...@linux.intel.com
---
tools/perf/Documentation/perf-record.txt | 3 ++-
1 file changed, 2
This patch enables privilege mode SW branch filters. Also modifies
POWER8 PMU branch filter configuration so that the privilege mode
branch filter implemented as part of base PMU event configuration
is reflected in bhrb filter mask. As a result, the SW will skip and
not try to process the
Powerpc kernel now supports SW based branch filters for book3s systems with some
specifc requirements while dealing with HW supported branch filters in order to
achieve overall OR semantics prevailing in perf branch stack sampling framework.
This patch adapts the BHRB branch filter configuration
This patch introduces new branch filter PERF_SAMPLE_BRANCH_COND which
will extend the existing perf ABI. Various architectures can provide
this functionality with either with HW filtering support (if present)
or with SW filtering of captured branch instructions.
Signed-off-by: Anshuman Khandual
This patch cleans up some existing indentation problem and
re-organizes the BHRB processing code with an helper function
named `update_branch_entry` making it more readable. This patch
does not change any functionality.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
This patch does some code re-arrangements to make it clear that
it ignores any separate privilege level branch filter request
and does not support any combinations of HW PMU branch filters.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 21
Hi Michael,
Thanks a lot for your answer. They reasoned that starting cpu hw idx
0... failed is reported because that core of the CPU is already up and
running.
I have built a git kernel from 2014-04-02.
- git clone
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git linux-git
On 05/05/2014 05:09 AM, Aneesh Kumar K.V wrote:
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Thanks, applied to kvm-ppc-queue.
Alex
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
Changes from V3:
* Use make_dsisr instead of checking
On 05/04/2014 07:25 PM, Aneesh Kumar K.V wrote:
We reserve 5% of total ram for CMA allocation and not using that can
result in us running out of numa node memory with specific
configuration. One caveat is we may not have node local hpt with pinned
vcpu configuration. But currently libvirt also
On 05/04/2014 07:26 PM, Aneesh Kumar K.V wrote:
With debug option sleep inside atomic section checking enabled we get
the below WARN_ON during a PR KVM boot. This is because upstream now
have PREEMPT_COUNT enabled even if we have preempt disabled. Fix the
warning by adding preempt_disable/enable
On 05/04/2014 07:30 PM, Aneesh Kumar K.V wrote:
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
No patch description, no proper explanations anywhere why you're doing
what. All of that in a pretty sensitive piece of code. There's no way
this patch can go upstream in its
On 05/05/2014 03:27 AM, Gavin Shan wrote:
The series of patches intends to support EEH for PCI devices, which have been
passed through to PowerKVM based guest via VFIO. The implementation is
straightforward based on the issues or problems we have to resolve to support
EEH for PowerKVM based
On 04/30/2014 11:09 PM, Alexander Graf wrote:
On 30.04.14 22:03, Stuart Yoder wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Wednesday, April 30, 2014 2:56 PM
To: Yoder Stuart-B08248; b...@kernel.crashing.org; Wood Scott-B07421
Cc:
On 05/05/2014 02:17 PM, Tudor Laurentiu wrote:
On 04/30/2014 11:09 PM, Alexander Graf wrote:
On 30.04.14 22:03, Stuart Yoder wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Wednesday, April 30, 2014 2:56 PM
To: Yoder Stuart-B08248;
On 05/05/2014 03:21 PM, Alexander Graf wrote:
On 05/05/2014 02:17 PM, Tudor Laurentiu wrote:
On 04/30/2014 11:09 PM, Alexander Graf wrote:
On 30.04.14 22:03, Stuart Yoder wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Wednesday, April 30, 2014 2:56 PM
Anton Blanchard wrote:
Unaligned stores take alignment exceptions on POWER7 running in little-endian.
This is a dumb little-endian base memcpy that prevents unaligned stores.
Once booted the feature fixup code switches over to the VMX copy loops
(which are already endian safe).
The question is
On Mon, 2014-05-05 at 13:56 +0200, Alexander Graf wrote:
On 05/05/2014 03:27 AM, Gavin Shan wrote:
The series of patches intends to support EEH for PCI devices, which have
been
passed through to PowerKVM based guest via VFIO. The implementation is
straightforward based on the issues or
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
Changes from
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:25 PM, Aneesh Kumar K.V wrote:
We reserve 5% of total ram for CMA allocation and not using that can
result in us running out of numa node memory with specific
configuration. One caveat is we may not have node local hpt with pinned
vcpu
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:30 PM, Aneesh Kumar K.V wrote:
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
No patch description, no proper explanations anywhere why you're doing
what. All of that in a pretty sensitive piece of code. There's no way
Alexander Graf ag...@suse.de writes:
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these
Olof Johansson ol...@google.com writes:
2014-05-05 7:43 GMT-07:00 Alexander Graf ag...@suse.de:
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM POWER cpus always had DAR value
[Now without HTML email -- it's what you get for cc:ing me at work
instead of my upstream email :)]
2014-05-05 7:43 GMT-07:00 Alexander Graf ag...@suse.de:
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Am 05.05.2014 um 16:57 schrieb Olof Johansson ol...@google.com:
[Now without HTML email -- it's what you get for cc:ing me at work
instead of my upstream email :)]
2014-05-05 7:43 GMT-07:00 Alexander Graf ag...@suse.de:
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf
Am 05.05.2014 um 16:50 schrieb Aneesh Kumar K.V
aneesh.ku...@linux.vnet.ibm.com:
Alexander Graf ag...@suse.de writes:
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM
Am 05.05.2014 um 16:35 schrieb Aneesh Kumar K.V
aneesh.ku...@linux.vnet.ibm.com:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:25 PM, Aneesh Kumar K.V wrote:
We reserve 5% of total ram for CMA allocation and not using that can
result in us running out of numa node memory with
Alexander Graf ag...@suse.de writes:
Am 05.05.2014 um 16:35 schrieb Aneesh Kumar K.V
aneesh.ku...@linux.vnet.ibm.com:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:25 PM, Aneesh Kumar K.V wrote:
We reserve 5% of total ram for CMA allocation and not using that can
result in us
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/b4860emu.dts | 7 ++-
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4
P1023RDS is no longer supported/manufactured by Freescale while P1023RDB is.
Signed-off-by: Lijun Pan lijun@freescale.com
---
arch/powerpc/boot/dts/p1023rds.dts | 219 -
arch/powerpc/configs/mpc85xx_defconfig | 1 -
On Mon, 2014-05-05 at 13:23 -0500, Lijun Pan wrote:
P1023RDS is no longer supported/manufactured by Freescale while P1023RDB is.
Signed-off-by: Lijun Pan lijun@freescale.com
---
arch/powerpc/boot/dts/p1023rds.dts | 219
-
-Original Message-
From: Wood Scott-B07421
Sent: Monday, May 05, 2014 2:05 PM
To: Pan Lijun-B44306
Cc: linuxppc-...@ozlabs.org; Medve Emilian-EMMEDVE1
Subject: Re: [PATCH v2] powerpc/mpc85xx: Remove P1023 RDS support
On Mon, 2014-05-05 at 13:23 -0500, Lijun Pan wrote:
P1023RDS
On Mon, 2014-05-05 at 18:58 +0300, Diana Craciun wrote:
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
index 922c30a..09dbc5f 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
+++
Am 05.05.14 16:57, schrieb Olof Johansson:
[Now without HTML email -- it's what you get for cc:ing me at work
instead of my upstream email :)]
2014-05-05 7:43 GMT-07:00 Alexander Graf ag...@suse.de:
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On
2014-05-05 8:03 GMT-07:00 Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com:
Olof Johansson ol...@google.com writes:
2014-05-05 7:43 GMT-07:00 Alexander Graf ag...@suse.de:
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:21 PM, Aneesh
-Original Message-
From: Preeti U Murthy [mailto:pre...@linux.vnet.ibm.com]
Sent: Monday, May 05, 2014 1:17 AM
To: linuxppc-dev@lists.ozlabs.org
Cc: b...@kernel.crashing.org; an...@samba.org; Motohiro Kosaki JP
Subject: [PATCH] powerpc: Fix comment around arch specific definition of
On Sun, 2014-05-04 at 05:59 -0500, Emil Medve wrote:
Hello Scott,
On 04/21/2014 05:14 PM, Scott Wood wrote:
On Fri, 2014-04-18 at 07:21 -0500, Shruti Kanetkar wrote:
FMan 1 Gb/s MACs (dTSEC and mEMAC) have support for SGMII PHYs.
Add support for the internal SerDes TBI PHYs
Based
On Mon, 2014-05-05 at 19:56 +0530, Aneesh Kumar K.V wrote:
Paul mentioned that BOOK3S always had DAR value set on alignment
interrupt. And the patch is to enable/collect correct DAR value when
running with Little Endian PR guest. Now to limit the impact and to
enable Little Endian PR guest,
On Mon, 2014-05-05 at 17:16 +0200, Alexander Graf wrote:
Isn't this a greater problem? We should start swapping before we hit
the point where non movable kernel allocation fails, no?
Possibly but the fact remains, this can be avoided by making sure that
if we create a CMA reserve for KVM, then
On Mon, 2014-05-05 at 16:43 +0200, Alexander Graf wrote:
Paul mentioned that BOOK3S always had DAR value set on alignment
interrupt. And the patch is to enable/collect correct DAR value when
running with Little Endian PR guest. Now to limit the impact and to
enable Little Endian PR guest,
On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
+#ifdef CONFIG_PPC_BOOK3S_64
+return vcpu-arch.fault_dar;
How about PA6T and G5s?
G5 sets DAR on an alignment interrupt.
As for PA6T, I don't know for sure, but if it
The only way Freescale booke chips support mappings larger than 4K
is via TLB1. The only way we support (direct) TLB1 entries is via
hugetlb, which is not what map_kernel_page() does when given a large
page size.
Without this, a kernel with CONFIG_SPARSEMEM_VMEMMAP enabled crashes on
boot with
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 4
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 1 +
On May 5, 2014, at 10:58 AM, Diana Craciun diana.crac...@freescale.com wrote:
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a
On Mon, 2014-05-05 at 21:12 -0500, Kumar Gala wrote:
On May 5, 2014, at 10:58 AM, Diana Craciun diana.crac...@freescale.com
wrote:
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the
On Mon, May 05, 2014 at 08:17:00PM +0530, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:30 PM, Aneesh Kumar K.V wrote:
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
No patch description, no proper explanations anywhere why you're doing
On Mon, May 05, 2014 at 08:00:12AM -0600, Alex Williamson wrote:
On Mon, 2014-05-05 at 13:56 +0200, Alexander Graf wrote:
On 05/05/2014 03:27 AM, Gavin Shan wrote:
The series of patches intends to support EEH for PCI devices, which have
been
passed through to PowerKVM based guest via VFIO.
61 matches
Mail list logo
