Was wondering how reboot works from linux kernel for t1040qds.
When checked, @arch/powerpc/sysdev/fsl_soc.c
__setup_rstcr, an ioremap is done for the offset 0xb0 and writes 0x2 to
that to reboot the machine. and it works properly.
when checked the reference manual for T1040QDS, it was given that
These patchs is to refine esai for tdm support.
Changes for V4
- update the comments for patch 2
Changes for V3
- update the comments for patch 2
Changes for V2
- update the comments according the reviewer's suggestion
- add init value for slots and change pin to pins.
Shengjiu Wang (2):
This reverts commit a603c8ee526f5ea9ad9b40710308766299ad8a69.
fsl_asoc_xlate_tdm_slot_mask() is different with snd_soc_xlate_tdm_slot_mask().
fsl_asoc_xlate_tdm_slot_mask() will set the enabled bit to 0, disabled bit
to 1. snd_soc_xlate_tdm_slot_mask() will set the enabled bit to 1, disabled
bit
On Fri, Aug 08, 2014 at 02:47:20PM +0800, Shengjiu Wang wrote:
These patchs is to refine esai for tdm support.
Changes for V4
- update the comments for patch 2
Changes for V3
- update the comments for patch 2
Changes for V2
- update the comments according the reviewer's suggestion
-
Original driver didn't store the number of slots, just fix the slot number
to 2, use this default number to calculate bclk and pins for TX/RX.
In this patch, add one parameter for slots, and update the calculation of
bclk and pins of TX/RX. Then driver will be compatible with slots 2 in
TDM mode.
This patchset:
* provides several MMU TLB handling optimisation on MPC8xx.
* adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
Tested-by: Christophe Leroy
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 17 +++--
1 files
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S |7 +++
1 files changed, 3
SCRATCH0 and SCRATCH1 are only used in Exceptions prologs where no other
exception can happen. There is therefore no need to preserve them accross
TLB handlers, we can use them there as in other exceptions. One of the
advantages is that they do not suffer CPU6 errata unlike M_TW register.
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 23 ++-
1 files changed, 10 insertions(+), 13
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S |4 ++--
1 files changed, 2 insertions(+), 2
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S |8 ++--
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S |6 ++
1 files changed, 2 insertions(+), 4
Lets save one cycle by aligning swapper_pg_dir on 16 bits boundary.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 13 +
1 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 29 ++---
1 files changed, 18 insertions(+), 11 deletions(-)
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 30 +-
1 files changed, 13 insertions(+), 17 deletions(-)
diff --git
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S |8 +---
1 files changed, 5
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 29 -
1 files changed,
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/pgtable-ppc32.h | 21 +
arch/powerpc/include/asm/pte-8xx.h |7 +--
arch/powerpc/kernel/head_8xx.S
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S |4
3 files changed, 7 insertions(+),
Thanks Vineeth for pointing this.
We will check this on T1040QDS and get back.
Regards
Priyanka
From: Linuxppc-dev
[mailto:linuxppc-dev-bounces+priyanka.jain=freescale@lists.ozlabs.org] On
Behalf Of Vineeth
Sent: Friday, August 08, 2014 11:35 AM
To: linuxppc-dev@lists.ozlabs.org
Subject:
Again, warm-reboot WORKS. there's no issue with that.
My ONLY concern is i am not able to understand how it works; the ref.manual
information and the code doesnt match.
Vineeth
On Fri, Aug 8, 2014 at 12:35 PM, Priyanka Jain priyanka.j...@freescale.com
wrote:
Thanks Vineeth for pointing this.
From: Julia Lawall julia.law...@lip6.fr
Simplify the error path to avoid calling of_node_put when it is not needed.
The semantic patch that finds this problem is as follows:
(http://coccinelle.lip6.fr/)
// smpl
@@
expression e;
@@
-if (e)
of_node_put(e);
// /smpl
Signed-off-by: Julia
From: Julia Lawall julia.law...@lip6.fr
Of_node_put supports NULL as its argument, so the initial test is not
necessary.
Suggested by Uwe Kleine-König.
The semantic patch that fixes this problem is as follows:
(http://coccinelle.lip6.fr/)
// smpl
@@
expression e;
@@
-if (e)
of_node_put(e);
From: Julia Lawall julia.law...@lip6.fr
Of_node_put supports NULL as its argument, so the initial test is not
necessary.
Suggested by Uwe Kleine-König.
The semantic patch that fixes this problem is as follows:
(http://coccinelle.lip6.fr/)
// smpl
@@
expression e;
@@
-if (e)
of_node_put(e);
From: Julia Lawall julia.law...@lip6.fr
Of_node_put supports NULL as its argument, so the initial test is not
necessary.
Suggested by Uwe Kleine-König.
The semantic patch that fixes this problem is as follows:
(http://coccinelle.lip6.fr/)
// smpl
@@
expression e;
@@
-if (e)
of_node_put(e);
From: Julia Lawall julia.law...@lip6.fr
Simplify the error path to avoid calling of_node_put when it is not needed.
The semantic patch that finds this problem is as follows:
(http://coccinelle.lip6.fr/)
// smpl
@@
expression e;
@@
-if (e)
of_node_put(e);
// /smpl
Signed-off-by: Julia
The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added
new Device Tree bindings for Asynchronous and Synchronous modes support.
However, these two shall not be present at the same time.
So this patch just simply makes them exclusive so as to avoid incorrect
Device Tree binding
On Fri, 2014-07-25 at 15:23 +0100, Pawel Moll wrote:
The code selecting a device for the sdhci host has been
continuously tweaked (4b711cb13843f5082e82970dd1e8031383134a65
mmc: sdhci-pltfm: Add structure for host-specific data and
a4d2177f00a5252d825236c5124bc1e9918bdb41 mmc: sdhci-pltfm: dt
On Thu, 2014-08-07 at 12:47 +1000, Gavin Shan wrote:
The patchset is mainly for fixing errors from building VFIO compoments
as dynamic modules. PATCH[4/4] allows VFIO can be used though EEH fails
to initialize for VFIO PCI devices.
Alexey Kardashevskiy (2):
drivers/vfio: Allow EEH to be
On Fri, 2014-08-08 at 11:35 +0530, Vineeth wrote:
Was wondering how reboot works from linux kernel for t1040qds.
When checked, @arch/powerpc/sysdev/fsl_soc.c
__setup_rstcr, an ioremap is done for the offset 0xb0 and writes 0x2
to that to reboot the machine. and it works properly.
On Thu, Aug 07, 2014 at 11:48:24PM +0200, Uwe Kleine-König wrote:
The ucc_geth_probe function assigns to ug_info-tbi_node and
ug_info-phy_node a value returned by of_parse_phandle which returns a
new reference. Put this reference again in the error path of
ucc_geth_probe and when removing the
3.13.11.6 -stable review patch. If anyone has any objections, please let me
know.
--
From: Peter Zijlstra pet...@infradead.org
commit 4badad352a6bb202ec68afa7a574c0bb961e5ebc upstream.
The optimistic spin code assumes regular stores and cmpxchg() play nice;
this is found to
From: Uwe Kleine-König u.kleine-koe...@pengutronix.de
Date: Fri, 8 Aug 2014 22:34:56 +0200
@davem: Should I send a fixup or a new version?
Fixup, please.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
Platform code can call limit_zone_pfn() to set appropriate limits
for ZONE_DMA and ZONE_DMA32, and dma_direct_alloc_coherent() will
select a suitable zone based on a device's mask and the pfn limits that
platform code has configured.
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Shaohui
FSL PCI cannot directly address the whole lower 4 GiB due to
conflicts with PCICSRBAR and outbound windows, and thus
max_direct_dma_addr is less than 4GiB. Honor that limit in
dma_direct_alloc_coherent().
Note that setting the DMA mask to 31 bits is not an option, since many
PCI drivers would
A DMA zone is still needed with swiotlb, for coherent allocations.
This doesn't affect platforms that don't use swiotlb or that don't call
swiotlb_detect_4g().
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Shaohui Xie shaohui@freescale.com
---
arch/powerpc/kernel/dma-swiotlb.c | 8
FSL PCI cannot directly address the whole lower 4 GiB due to
conflicts with PCICSRBAR and outbound windows. By the time
max_direct_dma_addr is set to the precise limit, it will be too late to
alter the zone limits, but we should always have at least 2 GiB mapped
(unless RAM is smaller than that).
__early_init_mmu() does some things that are really only needed by the
boot cpu. On FSL booke, This includes calling
memblock_enforce_memory_limit(), which is labelled __init. Secondary
cpu init code can't be __init as that would break CPU hotplug.
While it's probably a bug that
Once again, we see
arch/powerpc/kernel/exceptions-64s.S: Assembler messages:
arch/powerpc/kernel/exceptions-64s.S:865: Error: attempt to move .org backwards
arch/powerpc/kernel/exceptions-64s.S:866: Error: attempt to move .org backwards
arch/powerpc/kernel/exceptions-64s.S:890: Error: attempt to
Platforms like IBM Power Systems supports service processor
assisted dump. It provides interface to add memory region to
be captured when system is crashed.
During initialization/running we can add kernel memory region
to be collected.
Presently we don't have a way to get the log buffer base
PowerNV platform is capable of capturing host memory region when system
crashes (because of host/firmware). We have new OPAL API to register/
unregister memory region to be captured when system crashes.
This patch adds support for new API. Also during boot time we register
kernel log buffer and
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