I have done a boot test on p5040ds and mpc5121eads board.
v3:
- Rebase on next.
- CC stable for patch 1.
- Add Scott and Michael's ack.
v2:
- Revert the commit da788acb2838 first.
- Invoke of_clk_init() from a common place.
v1
This tries to fix a kernel panic introduced by commit
This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver
So the boards which has COMMON_CLK enabled don't have to
invoke this in its board specific file.
Signed-off-by: Kevin Hao haoke...@gmail.com
Acked-by: Scott Wood scottw...@freescale.com
Acked-by: Michael Turquette mturque...@linaro.org
---
v3: Add ack.
v2: A new patch in v2.
In order to fix the following section mismatch warning:
WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference
from the variable ppc_corenet_clk_driver to the function
.init.text:ppc_corenet_clk_probe()
The variable ppc_corenet_clk_driver references
the function __init
This supports SoC(s) with multiple QMan instances
Signed-off-by: Emil Medve emilian.me...@freescale.com
---
Documentation/devicetree/bindings/soc/fsl/qman.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt
v4: Add binding for the portals phandle
Fix portals phandle
v3: Remove no-map
Adjust alloc-ranges for the 32-/36-bit SoC(s)
v2: Remove some reserved-memory properties
Split the patchset per IP block
Refined patch assignment
Emil Medve (2):
This supports SoC(s) with multiple BMan instances
Signed-off-by: Emil Medve emilian.me...@freescale.com
---
Documentation/devicetree/bindings/soc/fsl/bman.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt
From: Kumar Gala ga...@kernel.crashing.org
Change-Id: I16e63db731e55a3d60d4e147573c1af8718082d3
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Geoff Thorpe geoff.tho...@freescale.com
Signed-off-by: Hai-Ying Wang haiying.w...@freescale.com
[Emil Medve: Sync with the upstream
From: Kumar Gala ga...@kernel.crashing.org
Change-Id: I16e63db731e55a3d60d4e147573c1af8718082d3
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Geoff Thorpe geoff.tho...@freescale.com
Signed-off-by: Hai-Ying Wang haiying.w...@freescale.com
[Emil Medve: Sync with the upstream
From: Kumar Gala ga...@kernel.crashing.org
Change-Id: If643fa5ba0a903aef8f5056a2c90ebecc995b760
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Geoff Thorpe geoff.tho...@freescale.com
Signed-off-by: Hai-Ying Wang haiying.w...@freescale.com
Signed-off-by: Chunhe Lan
From: Kumar Gala ga...@kernel.crashing.org
Change-Id: If643fa5ba0a903aef8f5056a2c90ebecc995b760
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Geoff Thorpe geoff.tho...@freescale.com
Signed-off-by: Hai-Ying Wang haiying.w...@freescale.com
Signed-off-by: Chunhe Lan
This patch series adds pstore support on powernv platform to
read different nvram partitions and write compressed data to
oops-log nvram partition. As pseries platform already has
pstore support, this series moves most of the common code
for pseries and powernv platforms to a common file. Tested
This patch adds a pstore type id to be used for opal specific
nvram partitions.
Signed-off-by: Hari Bathini hbath...@linux.vnet.ibm.com
---
fs/pstore/inode.c |3 +++
include/linux/pstore.h |1 +
2 files changed, 4 insertions(+)
diff --git a/fs/pstore/inode.c b/fs/pstore/inode.c
This patch extends pstore, a generic interface to platform dependent
persistent storage, support for powernv platform to capture certain
useful information, during dying moments. Such support is already in
place for pseries platform. This patch while adding pstore support
for powernv platform,
This parameter basically leaves unwanted cpus executing in firmware or
wherever they happen to be. This is a hack that shoudn't be used in a
production environment.
It also has an evil side effect on the split-core feature for powernv. The
code needs all the cpus to participate to the split mode
On Wed, 26 Nov 2014 09:28:47 +1100
Gavin Shan gws...@linux.vnet.ibm.com wrote:
On Tue, Nov 25, 2014 at 05:10:06PM +0100, Greg Kurz wrote:
This is what we get in dmesg when booting a pseries guest and
the hypervisor doesn't provide EEH support.
[0.166655] EEH functionality not supported
Michael Ellerman m...@ellerman.id.au writes:
On Tue, 2014-12-02 at 12:20 +0530, Aneesh Kumar K.V wrote:
upatepp get called for a nohpte fault, when we find from the linux
page table that the translation was hashed before. In that case
we are sure that there is no existing translation, hence
On Tuesday 02 December 2014 07:34 AM, Scott Wood wrote:
On Thu, 2014-11-27 at 17:48 +0530, Madhavan Srinivasan wrote:
- I really appreciate feedback on the patchset.
- Kindly comment if I should try with any other benchmark or
workload to check the numbers.
- Also, kindly recommand any
On Tuesday 02 December 2014 03:05 AM, Gabriel Paubert wrote:
On Thu, Nov 27, 2014 at 05:48:40PM +0530, Madhavan Srinivasan wrote:
This patch create the infrastructure to handle the CR based
local_* atomic operations. Local atomic operations are fast
and highly reentrant per CPU counters.
On Monday 01 December 2014 11:31 PM, Gabriel Paubert wrote:
On Thu, Nov 27, 2014 at 05:48:41PM +0530, Madhavan Srinivasan wrote:
This patch re-write the current local_* functions to CR5 based one.
Base flow for each function is
{
set cr5(eq)
load
..
store
clear
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Tue, 2014-12-02 at 12:57 +0530, Aneesh Kumar K.V wrote:
Now, hash_preload can possibly insert an hpte in hash page table even if
the access is not allowed by the pte permissions. But i guess even that
is ok. because we will fault
On Wed, Dec 03, 2014 at 08:53:37PM +0530, Aneesh Kumar K.V wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Tue, 2014-12-02 at 12:57 +0530, Aneesh Kumar K.V wrote:
Now, hash_preload can possibly insert an hpte in hash page table even if
the access is not allowed by the
On Wed, Dec 03, 2014 at 08:29:37PM +0530, Madhavan Srinivasan wrote:
On Tuesday 02 December 2014 03:05 AM, Gabriel Paubert wrote:
On Thu, Nov 27, 2014 at 05:48:40PM +0530, Madhavan Srinivasan wrote:
diff --git a/arch/powerpc/include/asm/exception-64s.h
Mel Gorman mgor...@suse.de writes:
On Wed, Dec 03, 2014 at 08:53:37PM +0530, Aneesh Kumar K.V wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Tue, 2014-12-02 at 12:57 +0530, Aneesh Kumar K.V wrote:
Now, hash_preload can possibly insert an hpte in hash page table even if
On Wednesday 03 December 2014 01:53:39 Emil Medve wrote:
On 12/02/2014 06:32 PM, Scott Wood wrote:
On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
diff --git a/arch/powerpc/boot/dts/t4240rdb.dts
b/arch/powerpc/boot/dts/t4240rdb.dts
index 53761d4..431bf4e 100644
---
Hello Arnd,
Thanks for taking the time to review this
On 12/03/2014 01:42 PM, Arnd Bergmann wrote:
On Wednesday 03 December 2014 01:53:39 Emil Medve wrote:
On 12/02/2014 06:32 PM, Scott Wood wrote:
On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
diff --git
On Wed, 2014-12-03 at 15:52 +, Mel Gorman wrote:
It's implied but can I assume it passed? If so, Ben and Paul, can I
consider the series to be acked by you other than the minor comment
updates?
Yes. Assuming it passed :-)
Acked-by: Benjamin Herrenschmidt b...@kernel.crashing.org
On Tue, 2014-12-02 at 17:03 -0600, Scott Wood wrote:
On Tue, 2014-12-02 at 06:12 -0600, Bucur Madalin-Cristian-B32716 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, December 02, 2014 6:40 AM
No need for the SoC part. As we previously discussed, the only
On Wed, Dec 03, 2014 at 03:20:46PM +0100, Greg Kurz wrote:
On Wed, 26 Nov 2014 09:28:47 +1100
Gavin Shan gws...@linux.vnet.ibm.com wrote:
On Tue, Nov 25, 2014 at 05:10:06PM +0100, Greg Kurz wrote:
This is what we get in dmesg when booting a pseries guest and
the hypervisor doesn't provide EEH
On Tuesday, December 02, 2014 01:54:16 PM Tony Jones wrote:
On 12/02/2014 01:27 PM, Richard Guy Briggs wrote:
Since both ppc and ppc64 have LE variants which are now reported by uname,
add that flag (__AUDIT_ARCH_LE) to syscall_get_arch() and add
AUDIT_ARCH_PPC*LE variants.
Without
On Thu, 2014-12-04 at 09:14 +1100, Gavin Shan wrote:
On Wed, Dec 03, 2014 at 03:20:46PM +0100, Greg Kurz wrote:
On Wed, 26 Nov 2014 09:28:47 +1100
Gavin Shan gws...@linux.vnet.ibm.com wrote:
On Tue, Nov 25, 2014 at 05:10:06PM +0100, Greg Kurz wrote:
This is what we get in dmesg when booting
As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
when removing pci devices on a bus which has VFs, we need to remove them in
the reverse order.
This patch applies this patten on the hotplug remove patch on powerpc arch.
Signed-off-by: Wei Yang
On 12/01/2014 11:09 PM, Michael Ellerman wrote:
On Mon, 2014-12-01 at 09:41 -0600, Nathan Fontenot wrote:
On 11/26/2014 09:12 PM, Benjamin Herrenschmidt wrote:
Hi Greg,
So Nathan is working on a patch series to cleanup and improve our
DLPAR infrastructure which is basically our hotplug
On 12/01/2014 10:26 PM, Greg KH wrote:
On Mon, Dec 01, 2014 at 09:41:03AM -0600, Nathan Fontenot wrote:
On 11/26/2014 09:12 PM, Benjamin Herrenschmidt wrote:
Hi Greg,
So Nathan is working on a patch series to cleanup and improve our
DLPAR infrastructure which is basically our hotplug
As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
when removing pci devices on a bus which has VFs, we need to remove them in
the reverse order.
This patch applies this pattern on the hotplug remove path on powerpc arch.
Signed-off-by: Wei Yang
Please ignore this one, I create an old version of the patch.
The new one is sent.
On Thu, Dec 04, 2014 at 11:04:32AM +0800, Wei Yang wrote:
As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
when removing pci devices on a bus which has VFs, we need to remove them in
the
On Wed, 2014-12-03 at 20:42 +0100, Arnd Bergmann wrote:
On Wednesday 03 December 2014 01:53:39 Emil Medve wrote:
On 12/02/2014 06:32 PM, Scott Wood wrote:
On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
diff --git a/arch/powerpc/boot/dts/t4240rdb.dts
On Wed, 2014-12-03 at 16:53 +0800, Kevin Hao wrote:
This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the
On Wed, Dec 03, 2014 at 09:07:27PM -0600, Nathan Fontenot wrote:
On 12/01/2014 10:26 PM, Greg KH wrote:
On Mon, Dec 01, 2014 at 09:41:03AM -0600, Nathan Fontenot wrote:
On 11/26/2014 09:12 PM, Benjamin Herrenschmidt wrote:
Hi Greg,
So Nathan is working on a patch series to cleanup and
On Wed, Dec 03, 2014 at 10:04:51PM -0600, Scott Wood wrote:
On Wed, 2014-12-03 at 16:53 +0800, Kevin Hao wrote:
This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section.
On Thu, 2014-12-04 at 12:38 +0800, Kevin Hao wrote:
On Wed, Dec 03, 2014 at 10:04:51PM -0600, Scott Wood wrote:
On Wed, 2014-12-03 at 16:53 +0800, Kevin Hao wrote:
This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
That commit tried to fix the section mismatch warning by
On Wed, 2014-12-03 at 04:02 -0600, Emil Medve wrote:
This supports SoC(s) with multiple BMan instances
Signed-off-by: Emil Medve emilian.me...@freescale.com
---
Documentation/devicetree/bindings/soc/fsl/bman.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git
On Wed, Nov 26, 2014 at 10:04:57AM +1100, Benjamin Herrenschmidt wrote:
On Tue, 2014-11-25 at 09:49 +1100, Gavin Shan wrote:
When loading rpaphp.ko on a P7 box, I didn't see any PCI slots
created under /sys/bus/pci/slots as expected. It seems that the
RPA PCI slot stuff has been broken for long
On Tue, Nov 25, 2014 at 09:38:42AM +1100, Gavin Shan wrote:
Please ignore this revision. v2 is on the way...
Thanks,
Gavin
The patchset corresponds to skiboot changes, which manages PCI slots
in a unified way: OPAL APIs used to do slot reset, power management,
presence status retrival. The
diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7
b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7
index 32f3f5f..cf70084 100644
--- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7
+++
On Wed, 2014-03-12 at 11:03:15 UTC, Hari Bathini wrote:
This patch extends pstore, a generic interface to platform dependent
persistent storage, support for powernv platform to capture certain
useful information, during dying moments. Such support is already in
place for pseries platform.
upatepp can get called for a nohpte fault when we find from the linux
page table that the translation was hashed before. In that case
we are sure that there is no existing translation, hence we could
avoid doing tlbie.
We could possibly race with a parallel fault filling the TLB. But
that should
On Thu, 2014-04-12 at 03:24:37 UTC, Wei Yang wrote:
As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
when removing pci devices on a bus which has VFs, we need to remove them in
the reverse order.
This patch applies this pattern on the hotplug remove path on powerpc
Function pnv_pci_reset_secondary_bus() is used to reset specified
PCI bus, which is leaded by root complex or PCI bridge. That means
the function shouldn't be called on PCI root bus and the patch
removes the logic for the case.
Also, some adapters may require fundamental reset to reload their
The patchset corresponds to skiboot changes, which manages PCI slots
in a unified way: OPAL APIs used to do slot reset, power management,
presence status retrival. The patchset shouldn't be merged before
the OPAL firmware counterpart is merged.
The kernel changes have been split into 2 parts: (A)
The patch refactors ioda_eeh_reset() to eliminate unnecessary
nested if statements to improve code readability. Except printing
the PHB index in the error message when failing to clear PHB error
injection registers, no logic changed.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
For PowerPC PowerNV platform, running on top of skiboot, all PE
level reset should be routed to firmware, which exported PCI slot
reset capability with device-node property ibm,reset-by-firmware.
Otherwise, the kernel still has to simulate hot reset on PCI bridge's
secondary bus. So the code
The patch intends to add standalone driver to support PCI hotplug
for PowerPC PowerNV platform, which runs on top of skiboot firmware.
The firmware identified hotpluggable slots and marked their device
tree node with proper ibm,slot-pluggable and ibm,reset-by-firmware.
The driver simply scans
The patch moves pcibios_find_pci_bus() to PPC kerenl directory so
that it can be reused by hotplug code for pSeries and PowerNV
platform at the same time.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
Acked-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
We might not get some PCI slot information (e.g. power status)
immediately by OPAL API. Instead, opal_pci_poll() need to be called
for the required information.
The patch introduces pnv_pci_poll(), which bases on original
ioda_eeh_poll(), to cover the above case
Signed-off-by: Gavin Shan
In hotplug case, function pcibios_add_pci_devices() is called to
rescan the specified PCI bus, which possibly doesn't have any child
devices. Access to the PCI bus's child device node will cause kernel
crash without exception. The patch adds conditions to skip scanning
the PCI bus, which doesn't
The series of patches depends on the OPAL firmware changes. If the firmware
doesn't have the changes, PCI hotplug slots won't be populated properly.
Other than that, no more problems found.
A new driver powernv-php.ko is introduced by the patchset to support
PCI hotplug for PowerNV platform. The
The patch exports two functions, which base on corresponding OPAL
APIs to retrieve PCI slot status. Those functions are going to be
used by PCI hotplug module in subsequent patches:
pnv_pci_get_power_status() opal_pci_get_power_status()
pnv_pci_get_presence_status()
On Wed, 2014-03-12 at 13:58:13 UTC, Greg Kurz wrote:
This parameter basically leaves unwanted cpus executing in firmware or
wherever they happen to be. This is a hack that shoudn't be used in a
production environment.
It also has an evil side effect on the split-core feature for powernv. The
On Wed, Dec 03, 2014 at 10:46:24PM -0600, Scott Wood wrote:
Since only this first patch is a critical bugfix, and there's no
arch/powerpc content in that patch, I think it should go via Mike's tree
if it's to go in for 3.18 (if it's not already too late). Or, to keep
things simple given the
On Thu, Dec 04, 2014 at 04:40:35PM +1100, Michael Ellerman wrote:
On Thu, 2014-04-12 at 03:24:37 UTC, Wei Yang wrote:
As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
when removing pci devices on a bus which has VFs, we need to remove them in
the reverse order.
Deep idle states like sleep and winkle are per core idle states. A core
enters these states only when all the threads enter either the particular
idle state or a deeper one. There are tasks like fastsleep hardware bug
workaround and hypervisor core state save which have to be done only by
the last
From: Paul Mackerras pau...@samba.org
Currently, when going idle, we set the flag indicating that we are in
nap mode (paca-kvm_hstate.hwthread_state) and then execute the nap
(or sleep or rvwinkle) instruction, all with the MMU on. This is bad
for two reasons: (a) the architecture specifies that
Deep idle states like sleep and winkle are per core idle states. A core
enters these states only when all the threads enter either the
particular idle state or a deeper one. There are tasks like fastsleep
hardware bug workaround and hypervisor core state save which have to be
done only by the last
From: Preeti U. Murthy pre...@linux.vnet.ibm.com
The secondary threads should enter deep idle states so as to gain maximum
powersavings when the entire core is offline. To do so the offline path
must be made aware of the available deepest idle state. Hence probe the
device tree for the possible
Winkle is a deep idle state supported in power8 chips. A core enters
winkle when all the threads of the core enter winkle. In this state
power supply to the entire chiplet i.e core, private L2 and private L3
is turned off. As a result it gives higher powersavings compared to
sleep.
But entering
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