On Mon, Mar 09, 2015 at 09:52:18AM -0700, Linus Torvalds wrote:
On Mon, Mar 9, 2015 at 4:29 AM, Dave Chinner da...@fromorbit.com wrote:
Also, is there some sane way for me to actually see this behavior on a
regular machine with just a single socket? Dave is apparently running
in some
On Tue, 2015-03-10 at 18:36 +1100, Michael Ellerman wrote:
We currently have a special syscall for switching endianness. This is
syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall
exception entry.
That has a few problems, firstly the syscall number is outside of the
On Mon, Mar 09, 2015 at 06:31:25PM +1100, Benjamin Herrenschmidt wrote:
On Mon, 2015-03-09 at 09:13 +0800, Kevin Hao wrote:
On Sun, Mar 08, 2015 at 08:13:26PM +1100, Benjamin Herrenschmidt wrote:
On Sat, 2015-03-07 at 19:14 +0800, Kevin Hao wrote:
All the cache line size of the current
On Tue, 2015-03-10 at 20:34 +1100, Benjamin Herrenschmidt wrote:
On Tue, 2015-03-10 at 18:36 +1100, Michael Ellerman wrote:
We currently have a special syscall for switching endianness. This is
syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall
exception entry.
On Mon, Mar 09, 2015 at 09:02:19PM +, Mel Gorman wrote:
On Sun, Mar 08, 2015 at 08:40:25PM +, Mel Gorman wrote:
Because if the answer is 'yes', then we can safely say: 'we regressed
performance because correctness [not dropping dirty bits] comes before
performance'.
If
Hi Wolfram,
You can add my
Acked-by and Tested-By: Ludovic Desroches ludovic.desroc...@atmel.com
Tested on sama5d3, some problems with at24 eeprom on sama5d4 but it
doesn't come from the i2c quirks patch series.
Regards
Ludovic
On Sun, Mar 08, 2015 at 09:28:45AM +0100, Wolfram Sang wrote:
All the cache line size of the current book3e 64bit SoCs are 64 bytes.
So we should use this size to align the member of paca_struct.
This only change the paca_struct's members which are private to book3e
CPUs, and should not have any effect to book3s ones. With this, we save
192 bytes. Also
On Tue, Mar 10, 2015 at 11:15:18AM +1100, Michael Ellerman wrote:
On Mon, 2015-03-09 at 17:53 +1100, Benjamin Herrenschmidt wrote:
On Sat, 2015-03-07 at 19:19 +0800, Kevin Hao wrote:
It makes no sense to use a variant lock token on a platform which
doesn't support for shared-processor
On 27/02/15 03:05, Kevin Hao wrote:
On Fri, Feb 27, 2015 at 11:11:15AM +1100, Benjamin Herrenschmidt wrote:
On Sat, 2015-01-31 at 21:47 +0800, Kevin Hao wrote:
The PPC_OF is a ppc specific option which is used to mean that the
firmware device tree access functions are available. Since all the
On Mon, Mar 09, 2015 at 11:17:31AM +0800, Wei Yang wrote:
As the comment indicates, powernv_eeh_get_state() will inform EEH core to
delay 1 second. This means the delay doesn't happen when
powernv_eeh_get_state() returns.
This patch moves the delay subtraction just before msleep(), which is the
On Wed, 2015-03-11 at 11:08 +0530, Anshuman Khandual wrote:
On 03/10/2015 04:25 PM, Michael Ellerman wrote:
On Tue, 2015-03-10 at 20:34 +1100, Benjamin Herrenschmidt wrote:
On Tue, 2015-03-10 at 18:36 +1100, Michael Ellerman wrote:
We currently have a special syscall for switching
On Mon, Mar 02, 2015 at 03:41:32PM +0800, Wei Yang wrote:
On Tue, Feb 24, 2015 at 02:52:34AM -0600, Bjorn Helgaas wrote:
On Tue, Feb 24, 2015 at 02:34:42AM -0600, Bjorn Helgaas wrote:
From: Wei Yang weiy...@linux.vnet.ibm.com
On PHB3, PF IOV BAR will be covered by M64 window to have
On Mon, Mar 09, 2015 at 11:17:29AM +0800, Wei Yang wrote:
struct pci_io_addr_range{} stores the information of pci resources. It
would be better to keep these related fields have the same type as in
struct resource{}.
This patch fixes the start/end/flags type in struct pci_io_addr_range{} to
have
On Mon, Mar 02, 2015 at 03:50:37PM +0800, Wei Yang wrote:
On Tue, Feb 24, 2015 at 02:46:53AM -0600, Bjorn Helgaas wrote:
On Tue, Feb 24, 2015 at 02:34:35AM -0600, Bjorn Helgaas wrote:
From: Wei Yang weiy...@linux.vnet.ibm.com
Current iommu_table of a PE is a static field. This will have
On Mon, Mar 09, 2015 at 11:17:30AM +0800, Wei Yang wrote:
To retrieve the PCI slot state, EEH driver would set a timeout for that.
While current comment is not aligned to what the code does.
This patch fixes those comments according to the code.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
On Tue, 10 Mar 2015 11:28:03 +1100
Michael Ellerman m...@ellerman.id.au wrote:
Mine is running:
CFE version PAS-2.0.29 for ATHENA (64bit,MP,BE,PPC)
Build Date: Mon Jun 30 11:47:25 PDT 2008 (mpl@mitch-1)
Steve is your CFE older than that?
Seems so:
CFE version PAS-2.0.20 for
I tested the i2c opal driver after updating the patch as below.
Basically I think we can also support write-then-{read/write}
for the number of messages = 2.
Ben, any issues if we support both write plus read/write in the
opal driver ?
Regards,
Neelesh
drivers/i2c/busses/i2c-opal.c | 20
From: Madalin Bucur madalin.bu...@freescale.com
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
arch/powerpc/include/asm/mpc85xx.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/mpc85xx.h
b/arch/powerpc/include/asm/mpc85xx.h
index 3bef74a..213f3a8
On 03/10/2015 04:25 PM, Michael Ellerman wrote:
On Tue, 2015-03-10 at 20:34 +1100, Benjamin Herrenschmidt wrote:
On Tue, 2015-03-10 at 18:36 +1100, Michael Ellerman wrote:
We currently have a special syscall for switching endianness. This is
syscall number 0x1ebe, which is handled explicitly
On 03/11/2015 04:42 AM, Benjamin Herrenschmidt wrote:
On Tue, 2015-03-10 at 22:43 +0530, Neelesh Gupta wrote:
I tested the i2c opal driver after updating the patch as below.
Basically I think we can also support write-then-{read/write}
for the number of messages = 2.
Ben, any issues if we
On Tue, Mar 10, 2015 at 02:23:12PM +0200, Tomi Valkeinen wrote:
I just sent out a v2 [1] a few hours earlier with some minor updates. We
plan
to merge this patch series via the powerpc tree in 4.1 cycle if I can
collect
all the acks from the corresponding driver maintainers.
Fbdev
On Mon, Mar 02, 2015 at 03:32:47PM +0800, Wei Yang wrote:
On Tue, Feb 24, 2015 at 02:41:52AM -0600, Bjorn Helgaas wrote:
On Tue, Feb 24, 2015 at 02:34:06AM -0600, Bjorn Helgaas wrote:
From: Wei Yang weiy...@linux.vnet.ibm.com
When sizing and assigning resources, we divide the resources
On Tue, 2015-03-10 at 01:07 +1100, Alexey Kardashevskiy wrote:
This adds create/remove window ioctls to create and remove DMA windows.
sPAPR defines a Dynamic DMA windows capability which allows
para-virtualized guests to create additional DMA windows on a PCI bus.
The existing linux kernels
On Wed, Mar 04, 2015 at 11:01:24AM +0800, Wei Yang wrote:
On Tue, Feb 24, 2015 at 03:00:37AM -0600, Bjorn Helgaas wrote:
On Tue, Feb 24, 2015 at 02:34:57AM -0600, Bjorn Helgaas wrote:
From: Wei Yang weiy...@linux.vnet.ibm.com
On PowerNV platform, resource position in M64 implies the PE#
On Mon, Mar 09, 2015 at 11:17:32AM +0800, Wei Yang wrote:
Currently, the macro IS_BRIDGE is not used any where.
This patch just removes it.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
Acked-by: Gavin Shan gws...@linux.vnet.ibm.com
Thanks,
Gavin
---
arch/powerpc/kernel/eeh.c |2 --
On Wed, Mar 11, 2015 at 04:13:46PM +1100, Gavin Shan wrote:
On Mon, Mar 09, 2015 at 11:17:31AM +0800, Wei Yang wrote:
As the comment indicates, powernv_eeh_get_state() will inform EEH core to
delay 1 second. This means the delay doesn't happen when
powernv_eeh_get_state() returns.
This patch
On Tue, 2015-03-10 at 01:06 +1100, Alexey Kardashevskiy wrote:
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of
On Fri, Mar 06, 2015 at 12:38:59PM -0600, Bjorn Helgaas wrote:
On Fri, Feb 20, 2015 at 04:53:08PM +1100, Gavin Shan wrote:
On Thu, Feb 19, 2015 at 04:57:47PM -0200, casca...@linux.vnet.ibm.com wrote:
On Tue, Feb 17, 2015 at 09:36:47AM +1100, Gavin Shan wrote:
On Mon, Feb 16, 2015 at 11:14:27AM
On 10/03/2015 01:33 a.m., Olof Johansson wrote:
* Electra: First development/eval board. Funky USB on localbus, plenty
of PCI-e. Two GigE, one 10GigE XAUI. CompactFlash and IDE on localbus
too. Usually shipped with a PCI-e SATA card and a USB card.
* Chitra: Second edition dev/eval board. Moved
We currently have a special syscall for switching endianness. This is
syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall
exception entry.
That has a few problems, firstly the syscall number is outside of the
usual range, which confuses various tools. For example strace
This adds a test of the switch_endian() syscall we added in the previous
commit.
We test it by calling the endian switch syscall, and then executing some
code in the other endian which writes to stdout and then does exit(0).
If the endian switch failed to happen that code sequence will be
On Wed, 2015-03-11 at 09:57 +1100, Alexey Kardashevskiy wrote:
On 03/11/2015 06:56 AM, Alex Williamson wrote:
On Tue, 2015-03-10 at 01:06 +1100, Alexey Kardashevskiy wrote:
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its
On Tue, 2015-03-10 at 22:43 +0530, Neelesh Gupta wrote:
I tested the i2c opal driver after updating the patch as below.
Basically I think we can also support write-then-{read/write}
for the number of messages = 2.
Ben, any issues if we support both write plus read/write in the
opal driver ?
On Wed, 2015-03-11 at 10:14 +1100, Benjamin Herrenschmidt wrote:
On Tue, 2015-03-10 at 17:03 -0600, Alex Williamson wrote:
return (PAGE_SHIFT + compound_order(compound_head(page) = page_shift);
This won't be bool though.
Yes, it will.
Don't you have your parenthesis in the
On 03/11/2015 06:56 AM, Alex Williamson wrote:
On Tue, 2015-03-10 at 01:06 +1100, Alexey Kardashevskiy wrote:
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted
On Tue, 2015-03-10 at 17:03 -0600, Alex Williamson wrote:
return (PAGE_SHIFT + compound_order(compound_head(page) = page_shift);
This won't be bool though.
Yes, it will.
Don't you have your parenthesis in the wrong place, Alex ? :-)
This will (I'll do this)
shift = PAGE_SHIFT
On Tue, 2015-03-10 at 01:07 +1100, Alexey Kardashevskiy wrote:
This is a pretty mechanical patch to make next patches simpler.
New tce_iommu_unuse_page() helper does put_page() now but it might skip
that after the memory registering patch applied.
As we are here, this removes unnecessary
On 03/11/2015 10:03 AM, Alex Williamson wrote:
On Wed, 2015-03-11 at 09:57 +1100, Alexey Kardashevskiy wrote:
On 03/11/2015 06:56 AM, Alex Williamson wrote:
On Tue, 2015-03-10 at 01:06 +1100, Alexey Kardashevskiy wrote:
This checks that the TCE table page size is not bigger that the size of
a
On 10.03.2015 [10:55:05 +1100], Michael Ellerman wrote:
On Thu, 2015-03-05 at 21:27 -0800, Nishanth Aravamudan wrote:
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 0257a7d659ef..0c1716cd271f 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -958,6
On Mon, Mar 9, 2015 at 12:19 PM, Dave Chinner da...@fromorbit.com wrote:
On Mon, Mar 09, 2015 at 09:52:18AM -0700, Linus Torvalds wrote:
What's your virtual environment setup? Kernel config, and
virtualization environment to actually get that odd fake NUMA thing
happening?
I don't have the
On Tue, 2015-03-10 at 01:07 +1100, Alexey Kardashevskiy wrote:
The existing IOMMU code takes/releases ownership over the existing IOMMU
tables created by the platform code, i.e. the tables remain in memory
all the time. Also, the existing IOMMU requires VFIO_IOMMU_ENABLE call to
start working
On Tue, 2015-03-10 at 01:07 +1100, Alexey Kardashevskiy wrote:
Before the IOMMU user would take control over the IOMMU table belonging to
a specific IOMMU group. This approach did not allow sharing tables between
IOMMU groups attached to the same container.
This introduces a new IOMMU
On 03/11/2015 11:09 AM, Alex Williamson wrote:
On Tue, 2015-03-10 at 01:07 +1100, Alexey Kardashevskiy wrote:
Before the IOMMU user would take control over the IOMMU table belonging to
a specific IOMMU group. This approach did not allow sharing tables between
IOMMU groups attached to the same
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